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2024-11-28drm/i915/dsb: Nuke the MMIO->indexed register write logicVille Syrjälä
We've determined that indexed DSB writes are only faster than MMIO writes when writing the same register ~5 or more times. That seems very unlikely to happen in any other case than when using indexed LUT registers. Simplify the code by removing the MMIO->indexed write conversion logic and just emit the instruction as an indexed write from the get go. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120164123.12706-4-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2024-11-28drm/i915/color: Stop using non-posted DSB writes for legacy LUTVille Syrjälä
DSB LUT register writes vs. palette anti-collision logic appear to interact in interesting ways: - posted DSB writes simply vanish into thin air while anti-collision is active - non-posted DSB writes actually get blocked by the anti-collision logic, but unfortunately this ends up hogging the bus for long enough that unrelated parallel CPU MMIO accesses start to disappear instead Even though we are updating the LUT during vblank we aren't immune to the anti-collision logic because it kicks in briefly for pipe prefill (initiated at frame start). The safe time window for performing the LUT update is thus between the undelayed vblank and frame start. Turns out that with low enough CDCLK frequency (DSB execution speed depends on CDCLK) we can exceed that. As we are currently using non-posted writes for the legacy LUT updates, in which case we can hit the far more severe failure mode. The problem is exacerbated by the fact that non-posted writes are much slower than posted writes (~4x it seems). To mititage the problem let's switch to using posted DSB writes for legacy LUT updates (which will involve using the double write approach to avoid other problems with DSB vs. legacy LUT writes). Despite writing each register twice this will in fact make the legacy LUT update faster when compared to the non-posted write approach, making the problem less likely to appear. The failure mode is also less severe. This isn't the 100% solution we need though. That will involve estimating how long the LUT update will take, and pushing frame start and/or delayed vblank forward to guarantee that the update will have finished by the time the pipe prefill starts... Cc: stable@vger.kernel.org Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates") Fixes: 25ea3411bd23 ("drm/i915/dsb: Use non-posted register writes for legacy LUT") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12494 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120164123.12706-3-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2024-11-28drm/i915/dsb: Don't use indexed register writes needlesslyVille Syrjälä
Turns out the DSB indexed register write command has rather significant initial overhead compared to the normal MMIO write command. Based on some quick experiments on TGL you have to write the register at least ~5 times for the indexed write command to come out ahead. If you write the register less times than that the MMIO write is faster. So it seems my automagic indexed write logic was a bit misguided. Go back to the original approach only use indexed writes for the cases we know will benefit from it (indexed LUT register updates). Currently we shouldn't have any cases where this truly matters (just some rare double writes to the precision LUT index registers), but we will need to switch the legacy LUT updates to write each LUT register twice (to avoid some palette anti-collision logic troubles). This would be close to the worst case for using indexed writes (two writes per register, and 256 separate registers). Using the MMIO write command should shave off around 30% of the execution time compared to using the indexed write command. Cc: stable@vger.kernel.org Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates") Fixes: 25ea3411bd23 ("drm/i915/dsb: Use non-posted register writes for legacy LUT") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120164123.12706-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2024-11-28Revert "drm/i915/dpt: Make DPT object unshrinkable"Ville Syrjälä
This reverts commit 51064d471c53dcc8eddd2333c3f1c1d9131ba36c. Now that we forcefully evict all DPT VMAs during suspend there should be no problem allowing the shrinker to eat the DPT objects. Cc: Brian Geffon <bgeffon@google.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12965 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241127061117.25622-5-ville.syrjala@linux.intel.com Acked-by: Brian Geffon <bgeffon@google.com> Reviewed-by: Vidya Srinivas <vidya.srinivas@intel.com> Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
2024-11-28drm/i915/dpt: Evict all DPT VMAs on suspendVille Syrjälä
Currently intel_dpt_resume() tries to blindly rewrite all the PTEs for currently bound DPT VMAs. That is problematic because the CPU mapping for the DPT is only really guaranteed to exist while the DPT object has been pinned. In the past we worked around this issue by making DPT objects unshrinkable, but that is undesirable as it'll waste physical RAM. Let's instead forcefully evict all the DPT VMAs on suspend, thus guaranteeing that intel_dpt_resume() has nothing to do. To guarantee that all the DPT VMAs are evictable by intel_dpt_suspend() we need to flush the cleanup workqueue after the display output has been shut down. And for good measure throw in a few extra WARNs to catch any mistakes. Cc: Brian Geffon <bgeffon@google.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241127061117.25622-4-ville.syrjala@linux.intel.com Reviewed-by: Vidya Srinivas <vidya.srinivas@intel.com> Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
2024-11-28drm/i915: Intruduce display.wq.cleanupVille Syrjälä
Introduce a dedicated workqueue for the commit cleanup work. In the future we'll need this to guarantee all the cleanup works have finished at a specific point during suspend. Cc: Brian Geffon <bgeffon@google.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241127061117.25622-3-ville.syrjala@linux.intel.com Reviewed-by: Vidya Srinivas <vidya.srinivas@intel.com> Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
2024-11-28drm/i915: Don't reuse commit_work for the cleanupVille Syrjälä
Currently we reuse the commit_work for a later cleanup step. Let's not do that so that atomic ioctl handler won't accidentally wait for the cleanup work when it really wants to just wait on the commit_tail() part. We'll just add another work struct for the cleanup. Cc: Brian Geffon <bgeffon@google.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241127061117.25622-2-ville.syrjala@linux.intel.com Reviewed-by: Vidya Srinivas <vidya.srinivas@intel.com> Tested-by: Vidya Srinivas <vidya.srinivas@intel.com>
2024-11-27drm/i915/dislay: convert i9xx_display_sr.[ch] to struct intel_displayJani Nikula
Going forward, struct intel_display is the main device data structure for display. Switch to it. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241126101222.2671224-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-27drm/i915/display: prefer DISPLAY_VER over GRAPHICS_VER in display s/rJani Nikula
Use display version checks for display scratch registers, not graphics version. And for the older platforms it's the same thing anyway. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241126101222.2671224-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-26drm/i915/ddi: clarify intel_ddi_connector_get_hw_state() for DP MSTJani Nikula
encoder->get_hw_state() returns false for DP MST, and currently always interprets 128b/132b as MST. Therefore the DDI MST mode checks in intel_ddi_connector_get_hw_state() are redundant. Prepare for future, and handle 128b/132b SST and warn on 8b/10b MST. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241125120959.2366419-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-25drm/i915: Fixed an typo in i915_gem_gtt.cZhang He
in function `i915_gem_gtt_reserve` @node comment, i915_vma has no `mode` member, `i915_vma.node` is the correct name Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Zhang He <zhanghe9702@163.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241120123245.71101-1-zhanghe9702@163.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-22drm/i915/irq: emphasize display_irqs_enabled is only about VLV/CHVJani Nikula
Use display_irqs_enabled only on VLV/CHV where it's relevant. Rename to vlv_display_irqs_enabled, to emphasize it's really only about VLV/CHV. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f60104ea59687cb8c65b18b4f9ddd832a643407d.1732102179.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/irq: hide display_irqs_enabled accessJani Nikula
Move the check for display_irqs_enabled within vlv_display_irq_reset() and vlv_display_irq_postinstall() to avoid looking at struct intel_display members within i915 core irq code. Within display irq code, vlv_display_irq_reset() may need to be called with !display_irqs_enabled, so add a small wrapper. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ef43e26ebab7f84768391f5053c0eba44b647c89.1732102179.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/plane: convert initial plane setup to struct intel_displayJani Nikula
struct intel_display replaces struct drm_i915_private as the main display device pointer. Convert initial plane setup to it, as much as possible. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9e370d8e90235165539f81ca2d00fdd2e883397f.1732102179.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/overlay: add intel_overlay_available() and use itJani Nikula
Avoid accessing struct intel_display members directly from i915_getparam_ioctl(). Add intel_overlay_available() function to provide the information for I915_PARAM_HAS_OVERLAY. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/26041645168ce3e76cb8f73bcb4c747619117e06.1732102179.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/overlay: convert to struct intel_displayJani Nikula
struct intel_display replaces struct drm_i915_private as the main display device pointer. Convert overlay to it, as much as possible. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3680586c05e82fd01d173cfb4f8df015d6db663c.1732102179.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/ddi: simplify intel_ddi_get_encoder_pipes() slightlyJani Nikula
Use a temporary variable for DDI mode to simplify the conditions. This is in line with the other places that read DDI mode. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/84892d31807bd8118474dd873e73c4d459f61448.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/ddi: refactor intel_ddi_connector_get_hw_state()Jani Nikula
Refactor the switch-case into an if-ladder similar to intel_ddi_read_func_ctl() for clarity. This highlights how TRANS_DDI_MODE_SELECT_FDI_OR_128B132B works on different platforms. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/191f0210d720f3113a092e1ef0c7996a7dee85a0.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/ddi: split up intel_ddi_read_func_ctl() by output typeJani Nikula
The function has become quite long, and the switch-case statement quite complex with the fallthrougs. Simplify by splitting to individual functions and an if-ladder. This highlights how TRANS_DDI_MODE_SELECT_FDI_OR_128B132B works on different platforms. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2621df6e6b0b7ac75159cfb112755c35b30ce906.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/ddi: rename temp to ddi_func_ctl in intel_ddi_read_func_ctl()Jani Nikula
The temp name is a bit vague for something used so much in the function. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/29d21b8f829e8139cc8ad857a86d3fc967f2ac07.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/dp: refactor clear/wait for act sentJani Nikula
Move clear_act_sent() and wait_for_act_sent() to intel_ddi.[ch] and make independent of DP MST. They'll be needed for 128b/132b SST operation. Rename accordingly. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ef05f5bc222e8ba48d84f75a9ea5dd29667055d2.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/reg: convert DP_TP_CTL/DP_TP_STATUS to REG_BIT() and friendsJani Nikula
Use the modern style for defining register contents. Expand the status register contents a bit. TODO: There are more VC payload mapping fields, spanning more registers, and have more bits on more recent platforms. v2: - Fix DP_TP_STATUS_STREAMS_ENABLED_MASK mask (Imre) - Drop status VC3 payload mapping for now Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1ef15e6bb58ca847f89c9b39cbc9771cb57db408.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/ddi: use intel_ddi_* naming convention for encoder enable/disableJani Nikula
All the other encoder hooks are named intel_ddi_*, follow suit with intel_ddi_enable() and intel_ddi_disable(), and the dp/hdmi variants. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9533cf61773f2cab3a6a29acf9e6ecfc00b6e8fd.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/mst: unify MST topology callback naming to mst_topology_*Jani Nikula
Make it easier to keep track of what belongs where. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e8efc8fddc3ca93e1256a1dad13bc4eca07c3382.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/mst: simplify mst_connector_get_hw_state()Jani Nikula
Use a variable for the encoder to simplify. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eb8595ae36c6330cce1615059bd2c89a7db79668.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/mst: unify MST connector function naming to mst_connector_*Jani Nikula
Similar to commit 5674e700d43e ("drm/i915/mst: change naming from fake encoders to MST stream encoders"), name all MST connector related functions to mst_connector_*. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3d4814a94b97fcff88722e0effd2fb5893b256af.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-22drm/i915/mst: pass intel_dp around in mst stream helpersJani Nikula
All of the functions in question operate on the primary encoder, and more specifically the primary intel_dp, so pass it around instead of the encoder for less ambiguity. Suggested-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/165ee8b723c42bcdeb3adf6a1b34ea09371e5d64.1732106557.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-19drm/i915/display/xe3lpd: Avoid setting YUV420_MODE in PIPE_MISCAnkit Nautiyal
For Xe3_LPD the PIPE_MISC YUV420 Enable (bit 27), already implies enabling full blend YUV420 mode and YUV420 Mode (bit 26) is removed. Therefore, avoid setting YUV420 Mode for Xe3_LPD+ while programming PIPE_MISC for YCbCr420 output format. Bspec: 69749 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113115531.3394962-1-ankit.k.nautiyal@intel.com
2024-11-19drm/i915/psr: Disable psr1 if setup_time > vblankAnimesh Manna
Issue is seen when PSR enabled with setup frames and when try to disable PSR at SRDONACK State (0x1). PSR FSM is stuck at SRDONACK(0x1) for more than 5 seconds. Issue not seen with Setup frames disabled. Currently disable psr1 if setuptime > vblank to workaround the above issue. HSD: 16024594674 WA: 18037818876 v1: Initial version v2: Add debug log and some cosmetic changes. [Jouni, Jani, Nemesa] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241105103916.1857731-1-animesh.manna@intel.com
2024-11-18drm/i915/dp_mst: Fix connector initialization in intel_dp_add_mst_connector()Imre Deak
The connector initialization in intel_dp_add_mst_connector() depends on the device pointer in connector to be valid, at least by connector debug printing. The device pointer is initialized by drm_connector_init(), however that function also exposes the connector to in-kernel users, which can't be done before the connector is fully initialized. For now make sure the device pointer is valid before it's used, until a follow-up change moving this to DRM core. This issue was revealed by the commit in the Fixes: line below, before which the above debug printing checked and handled a NULL device pointer gracefully in DRM core. Cc: Jani Nikula <jani.nikula@intel.com> Fixes: 529798bd786a ("drm/i915/mst: convert to struct intel_display") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12799 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241118131044.1278028-1-imre.deak@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-18drm/i915/dp: Include the time taken by AUX Tx for timeoutArun R Murthy
As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this timeout value is exclusively for the Aux RD Interval and excludes the time consumed for the AUX Tx (i.e reading/writing FFE presets). Add another 50ms for these AUX Tx to the 400ms timeout. Ref: "Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence" of DP2.1a spec. Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240925034432.1777029-4-arun.r.murthy@intel.com
2024-11-18drm/i915/dp: read Aux RD interval just before setting the FFE presetArun R Murthy
Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of DP2.1a spec. After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets. AUX_RD_INTERVAL and then write the new FFE presets. v4: Read AUX_RD_INTERVAL before get/set TX FFE preset (Jani) Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241011045825.2629469-1-arun.r.murthy@intel.com
2024-11-18drm/i915/dp: use fsleep instead of usleep_range for LTArun R Murthy
Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range() and for > 10ms use msleep. flseep() will call the particular API based on the above condition. (Documentation/timers/timers-howto.rst) Aux RD Interval value depends on the value read from the dpcd register which is updated from the sink device, hence use flseep. Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240925034432.1777029-2-arun.r.murthy@intel.com
2024-11-14drm/{i915, xe}: Move power_domains suspend/resume to display_powerRodrigo Vivi
Move intel_power_domains_{suspend,resume} to inside intel_display_power_{suspend_late, resume_early}. With this also change the VLV suspend failure to call the intel_display_power_resume_early. In the end, the only function executed there for VLV is the intel_power_domains_resume. Besides make the code more consistency give the call that was immediately before: intel_display_power_suspend_late. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-7-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/xe/display: Delay dsm handler registrationRodrigo Vivi
Bring some consistency to register/unregister order at the same time it aligns with i915 sequence order. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-6-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/xe/display: Delay hpd_init resumeRodrigo Vivi
Align with i915 and only initialize hotplugs after the display driver access has been resumed. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-5-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/{i915, xe}/display: Move DP MST calls to display_driverRodrigo Vivi
Move dp_mst suspend/resume functions from the drivers towards intel_display_driver to continue with the unification. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-4-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/i915/display: Move regfile registers intel_display.restoreRodrigo Vivi
The intel_display struct already has a place for save/restore stuff. Move the i915's regfile there since they are only related to display. Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-3-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/i915/display: Convert i915_suspend into i9xx_display_srRodrigo Vivi
These save & restore functions inside i915_suspend are old display functions to save and restore a bunch of display related registers. Move it under display and rename accordantly. Just don't move it entirely towards intel_display struct yet because it depends on drm_i915_private for the IS_MOBILE. While doing this conversion also update the MIT header using the new SPDX ones. v2: Fix Makefile and include (Jani) Removed vga and gmbus (Jani, Ville) Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-2-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-14drm/i915: Remove vga and gmbus seq out of i915_restore_displayRodrigo Vivi
Restrict this function to only save and restore registers functionality. Then, that can be moved out later to under display with a proper name. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241113225016.208673-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-11-13drm/i915/dp: Limit max compressed bpp to 18 when forcing DSCAnkit Nautiyal
While forcing DSC when it is not actually required, the max compressed bpp from the source gets picked for compression for some pipe bpps. Apparently, when DSC is not required, forcing DSC to the maximum compressed bpp seems to cause underruns. To avoid this, limit the max compressed bpp to 18 while forcing DSC. This value works across platforms with different pipe bpps and prevents underruns. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Naga Venkata Srikanth V <nagavenkata.srikanth.v@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030084100.1361689-1-ankit.k.nautiyal@intel.com
2024-11-12drm/i915/dp: add comments about hooks called from MST stream encodersJani Nikula
It would be best to have self-explanatory code, but lacking that, add some comments about the way the DDI encoder hooks get called from DP MST stream encoders. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5941b8ef48cac4d61de2e2806a80645de48e856c.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: change naming from fake encoders to MST stream encodersJani Nikula
The fake encoders pretty much match individual MST streams. The encoders remain as fake as ever, but change the naming to MST stream encoders. Rename all the encoder hooks and related functions called from them to mst_stream_* to clarify what type of encoders the hooks are called on. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/37d9572e884ca2fdd84ea6722b4b7cefde04eed9.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: convert to struct intel_displayJani Nikula
struct intel_display will replace struct drm_i915_private as the main display device data structure. Convert the DP MST code to struct intel_display as much as possible. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/84c9923fccdd779f0ca713cab1d26a0c802b140c.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/display: make CHICKEN_TRANS() display version awareJani Nikula
Making register macros platform or display version aware is not exactly something I want to promote widely, but in this case it's the lesser of two evils. hsw_chicken_trans_reg() is not pretty, and it doesn't have a suitable home. v2: Rebase Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/712c17ee22537b0628aa32695743bc017b3fe332.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: use primary_encoder in fake mst encoder creationJani Nikula
Use a primary_encoder local variable in intel_dp_create_fake_mst_encoder() for clarity. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7c9ad1db97550b7eacb1f010521704f623b0c689.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: introduce to_primary_encoder() and to_primary_dp()Jani Nikula
Add helpers to_primary_encoder() and to_primary_dp() to convert fake MST encoder pointers to primary encoder and DP pointers, respectively, and use them. The main point is to highlight the primary encoder and DP usage. Very few places actually need the struct intel_dp_mst_encoder pointer, or the primary struct intel_digital_port, so ditch them where possible for clarity. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ff8786c04bae053055783f720f89a4d9f9815c70.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: rename intel_encoder to encoderJani Nikula
Switch to the modern style in fake mst encoder creation. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4d29387fba64b925c6ab4c108782a7b5ac22628a.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/mst: pass primary encoder to primary encoder hooksJani Nikula
Pass the primary encoder to the primary encoder hooks. This is pedantically correct, but intel_ddi_post_pll_disable() also works with the fake encoder by coincidence. Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a0151fddfdd5ec11a26345232cdd3ae59c8cf56a.1731409802.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-11-12drm/i915/display: add mobile platform groupJani Nikula
Identify mobile platforms separately in display, using the platform group mechanism. This enables dropping the dependency on i915_drv.h IS_MOBILE() from display code. v2: Make snb_display static (kernel test robot) Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2389fd58446e83a79ec57bc0b037679662037b9e.1731321183.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit (git 2.34.1) at 2025-09-10 18:41:33 +0000