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2020-06-29ARM: dts: omap: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski
Fix dtschema validator warnings like: l2-cache-controller@48242000: $nodename:0: 'l2-cache-controller@48242000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-06-29ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2Adam Ford
Various OMAP3 boards have two AES blocks, but only one is currently available, because the hwmods are only configured for one. This patch migrates the hwmods for the AES engine to sysc-omap2 which allows the second AES crypto engine to become available. omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6 omap-aes 480a6000.aes1: will run requests pump with realtime priority omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6 omap-aes 480c5000.aes2: will run requests pump with realtime priority Signed-off-by: Adam Ford <aford173@gmail.com> [tony@atomide.com: updated to disable both aes_targets on hs boards] Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-06-29ARM: dts: r8a7778: Enable IRLM setup via DTUlrich Hecht
Make use of the IRLM setup feature in the renesas-intc-irqpin driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/1441726946-30131-3-git-send-email-ulrich.hecht+renesas@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26ARM: dts: at91: sama5d2_xplained: Remove pdmic nodeCodrin Ciubotariu
The PDMIC needs PDM microphones to work. sama5d2 xplained doesn't have such microphones, so there is no reason to enable PDMIC and take the pins since there is no-one using them. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200618152845.682723-1-codrin.ciubotariu@microchip.com
2020-06-26ARM: dts: sam9x60: add rttClaudiu Beznea
Add RTT. Allong with it enable GBPR as it is requested by RTT. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1591779936-18577-4-git-send-email-claudiu.beznea@microchip.com
2020-06-26dt-bindings: rtc: add microchip,sam9x60-rttClaudiu Beznea
Add microchip,sam9x60-rtt to compatible list. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1591779936-18577-3-git-send-email-claudiu.beznea@microchip.com
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2N Rev2.0/3.0/4.0 board with idk-1110wr ↵Lad Prabhakar
display The HiHope RZ/G2N variants are advertised as compatible with panel idk-1110wr from Advantech, however the panel isn't sold alongside the board. New dts's, enabling the lvds node to get the panel to work with all the HiHope RZ/G2N variants. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-12-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 sub board supportLad Prabhakar
The HiHope RZ/G2N sub board sits below the HiHope RZ/G2N Rev.3.0/4.0 main board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2N Rev.3.0/4.0 main board supportLad Prabhakar
Add support for HiHope RZ/G2N Rev.3.0/4.0 main board support based on r8a774b1 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 board with idk-1110wr displayLad Prabhakar
Add support for idk-1110wr display as similarly done for Rev.2.0 Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: hihope-rzg2-ex: Separate out lvds specific nodes into ↵Lad Prabhakar
common file Separate out LVDS specific nodes into common file hihope-rzg2-ex-lvds.dtsi so that this can be re-used by RZ/G2M[N] variants. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 sub board supportLad Prabhakar
The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M Rev.3.0/4.0 main board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2M Rev.3.0/4.0 main board supportLad Prabhakar
Add support for HiHope RZ/G2M Rev.3.0/4.0 main board support based on r8a774a1 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: Add HiHope RZ/G2M[N] Rev.3.0/4.0 specific into common fileLad Prabhakar
Rev.3.0 and Rev.4.0 are identical and can be identified by using GP5_19 and GP5_21. Rev GP5_19 GP5_21 ============================== Rev.3.0 0 0 Rev.4.0 0 1 This patch creates hihope-rev4.dtsi file with Rev.3.0/4.0 specific changes for HopeRun HiHope RZ/G2M[N] boards. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: hihope-common: Separate out Rev.2.0 specific into ↵Lad Prabhakar
hihope-rev2.dtsi file Separate out Rev.2.0 specific hardware changes into hihope-rev2.dtsi file so that hihope-common.dtsi can be used by all the variants for RZ/G2M[N] boards. LED node names have been updated according to Rev.4.0 schematics. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: r8a774b1-hihope-rzg2n[-ex]: Rename HiHope RZ/G2N boardsLad Prabhakar
The existing DTS files for HiHope RZ/G2N boards are for Rev.2.0 version so reflect the same for the DTS file names so that the existing naming convention can be used for Rev.3.0/4.0 boards. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: r8a774a1-hihope-rzg2m[-ex/-ex-idk-1110wr]: Rename ↵Lad Prabhakar
HiHope RZ/G2M boards The existing DTS files for HiHope RZ/G2M boards are for Rev.2.0 version so reflect the same for the DTS file names so that the existing naming convention can be used for Rev.3.0/4.0 boards. While at it also added a comment about switch SW43 to be OFF for pciec1 to be activated. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1593004330-5039-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26arm64: dts: renesas: r8a77961: Add IPMMU nodesYoshihiro Shimoda
Add IPMMU nodes for r8a77961 (R-Car M3-W+). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1591874021-10209-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26ARM: dts: r8a7742: Add MSIOF[0123] supportLad Prabhakar
Add the DT nodes needed by MSIOF[0123] interfaces to the SoC dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1591736054-568-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-26ARM: dts: exynos: Align L2 cache-controller nodename with dtschemaAnand Moon
Fix dtschema warning message by changing nodename to 'cache-controller': DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/l2c2x0.yaml arch/arm/boot/dts/exynos4210-i9100.dt.yaml: l2-cache-controller@10502000: $nodename:0: 'l2-cache-controller@10502000' does not match ' ^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-06-25ARM: dts: bcm2711: Add firmware clocks nodeMaxime Ripard
Now that we have a clock driver for the clocks exposed by the firmware, let's add the device tree nodes for it. Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/9a6f113140b3115150bfb18ecb248a48d58562cf.1592210452.git-series.maxime@cerno.tech
2020-06-25ARM: tegra: The Tegra30 SDHCI is not backwards-compatibleThierry Reding
The SDHCI on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: The Tegra30 DC is not backwards-compatibleThierry Reding
The display controller on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Remove spurious comma from node nameThierry Reding
This was probably left there by mistake or perhaps was a typo in the first place. Remove it. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add parent clock to DSI outputThierry Reding
The DSI output needs to specify a parent clock that will be used to drive both the output and the display controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use standard names for SRAM nodesThierry Reding
SRAM nodes should be named sram@<unit-address> to match the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: seaboard: Use standard battery bindingsThierry Reding
Seaboard uses a non-existing, possibly obsoleted, binding for the battery. Move to the standard binding which seems to be a super- set of the odl binding. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use standard names for LED nodesThierry Reding
LED nodes should be named led-* to match the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use numeric unit-addressesThierry Reding
Unit-addresses should be numeric. This fixes a validation failure seen using the json-schema tooling. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: medcom-wide: Remove extra panel power supplyThierry Reding
Simple panels can only have a single power supply. The second listed supply is not needed because it is also the input supply of the first supply and therefore will always be on at the same time. In retrospect the panel probably doesn't qualify as simple since it apparently does need both of these supplies, even if in the case of the Medcom Wide it isn't necessary to explicitly hook them up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use proper unit-addresses for OPPsThierry Reding
Use commas rather than underscores to separate the various parts of the unit-address in CPU OPPs to make them properly validate under the json- schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing clock-names for SDHCI controllersThierry Reding
The Tegra SDHCI controllers need to have a clock-names property according to the bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Fix order of XUSB controller clocksThierry Reding
This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add #reset-cells to Tegra124 memory controllerThierry Reding
The memory controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advertise the number of cells needed to describe each of the resets. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing panel power suppliesThierry Reding
Both Nyan boards as well as Venice2 are missing panel power supplies. Add them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add micro-USB A/B port on Jetson TK1Thierry Reding
Run the micro-USB A/B port on Jetson TK1 in host mode by default. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use proper tuple notationThierry Reding
Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use standard name for Ethernet devicesThierry Reding
Ethernet device should be named "ethernet@<unit-address>". Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing #sound-dai-cells property to codecsThierry Reding
Audio codecs need a #sound-dai-cells property, so add one to the audio codecs on various Tegra-based boards that don't have one. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing #phy-cells property to USB PHYsThierry Reding
USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Tegra114 SDHCI is not backwards-compatibleThierry Reding
The SDHCI controller instantiated on Tegra114 is not backwards- compatible with the version on Tegra30, so remove the corresponding compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Rename sdhci nodes to mmcThierry Reding
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Drop display controller parent clocks on Tegra124Thierry Reding
The parent clocks are determined by the output that will be used, not by the display controller that drives the output. On previous generations a simple RGB output used to be part of the display controller and hence an explicit parent clock needed to be assigned to the display controller to drive the RGB output. Starting with Tegra124, that RGB output has been dropped and the parent clock can therefore be removed from the display controller device tree nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-24arm64: dts: sc7180: Add interconnect for QUP and QSPIAkash Asthana
Add interconnect ports for GENI QUPs and QSPI to set bus capabilities. Signed-off-by: Akash Asthana <akashast@codeaurora.org> Link: https://lore.kernel.org/r/1592908737-7068-9-git-send-email-akashast@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-24arm64: dts: ipq8074: enable USB supportSivaprakash Murugesan
IPQ8074 has two super speed usb ports, add phy and dwc3 nodes to enable them. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-6-git-send-email-sivaprak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: angler: Add qcom,msm-id and pmic-idKonrad Dybcio
Add properties required for the bootloader to select the correct bootloader blob. They have been removed from the SoC device tree as they should be set on a per-device basis. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add PSCI nodeKonrad Dybcio
Add PSCI node to enable multi-processor startup. Note that not every 8994 device firmware supports PSCI, and even if, then it can only start the cores and not shut them down. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add pmu nodeKonrad Dybcio
Add the CPU PMU to get perf support for hardware events. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add I2C, SPI and BLSP DMA nodesKonrad Dybcio
Add support for I2C and SPI buses to enable peripherals such as touchscreens or sensors. Also add DMA nodes, configuration and BLSP2 UART2 interface. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-23arm64: dts: qcom: msm8994: Add SDHCI1 nodeKonrad Dybcio
Enable support for SDHCI on msm8994-based devices. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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