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2018-10-11mlxsw: reg: Add Tunneling NVE Underlay Multicast Table RegisterIdo Schimmel
This register builds the linked list of underlay destination IPs used for BUM traffic on the overlay. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: reg: Add Tunnel Port Configuration RegisterIdo Schimmel
This register enables / disables learning on different types of tunnel ports (e.g., NVE, VPLS). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: reg: Add Tunneling NVE General Configuration RegisterIdo Schimmel
This register configures global NVE configuration such as source IP of the NVE tunnel and UDP source port calculation. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum: Seed LAG hash functionIdo Schimmel
Currently, the seed of the LAG hash function is always set to 0, which means it is identical across all switches. Instead, use a random number. This is especially important now that VxLAN is supported, as the LAG hash function is used to calculate the UDP source port of the encapsulated packet. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: reg: Extend FDB flush types for NVEIdo Schimmel
The device has the ability to flush all the FDB records that perform NVE encapsulation or only a subset of these with a specific filtering identifier (FID). Expose these types so that they could be used by subsequent patches where we need to flush the FDB records when an NVE device is unlinked from a bridge (FID). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum: Add a new type of KVD linear recordIdo Schimmel
When the device needs to flood an overlay packet to remote VTEPs it retrieves a pointer to the head of a linked-list of records that store the IP addresses of these VTEPs. These records are stored in the KVD linear memory and configured via the Tunneling NVE Underlay Multicast Table (TNUMT) register. Add a new KVD linear entry type for these records, so that we will be able to allocate and free them. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum: Move L3 protocol and address definitions to global header fileIdo Schimmel
The L3 protocol and address definitions are going to be used by the NVE code, so move them to the global header file from the one private to the router. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum_switchdev: Do not assume notifier information typeIdo Schimmel
VxLAN notifications are going to use a different notifier information type, so cast to the correct type based on the received event. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum_switchdev: Check notification relevance based on upper deviceIdo Schimmel
VxLAN FDB updates are sent with the VxLAN device which is not our upper and will therefore be ignored by current code. Solve this by checking whether the upper device (bridge) is our upper. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum_switchdev: Prepare for VxLAN FDB notificationsIdo Schimmel
VxLAN FDB notifications need to be handled differently than bridge FDB notifications, so initialize the work item based on the received notification and rename the invoked function accordingly. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11mlxsw: spectrum: Remove misuses of private header fileIdo Schimmel
The spectrum_router.h header file is private to the router block and should only be included by direct consumers of it, such as dpipe and the multicast routing code. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11octeontx2-af: Remove set but not used variable 'dev'YueHaibing
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/marvell/octeontx2/af/cgx.c: In function 'cgx_fwi_event_handler': drivers/net/ethernet/marvell/octeontx2/af/cgx.c:257:17: warning: variable 'dev' set but not used [-Wunused-but-set-variable] It never be used since introduction in commit 1463f382f58d ("octeontx2-af: Add support for CGX link management") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11block: describe difference between flags IO_STAT and STATSKonstantin Khlebnikov
This adds reasonable comments, but they definitely needs better names. Signed-off-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2018-10-11net: mscc: allow extracting the FCS into the skbAntoine Tenart
This patch adds support for the NETIF_F_RXFCS feature in the Mscc Ethernet driver. This feature is disabled by default and allow a user to request the driver not to drop the FCS and to extract it into the skb for debugging purposes. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11PCI/IOV: Use VF0 cached config space size for other VFsKarimAllah Ahmed
Cache the config space size from VF0 and use it for all other VFs instead of reading it from the config space of each VF. We assume that it will be the same across all associated VFs. This is an optimization when enabling SR-IOV on a device with many VFs. Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> [bhelgaas: use CONFIG_PCI_IOV (not CONFIG_PCI_ATS)] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-10-11NTB: switchtec_ntb: Update switchtec documentation with prerequisites for NTBWesley Yung
The ntb_hw_switchtec driver has requirements on kernel configuration so add these notes to the documentation and also clean up a few other sentences in the documentation. Signed-off-by: Wesley Yung <wesley.yung@microchip.com> Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2018-10-11PCI: Fix Switchtec DMA aliasing quirk dmesg noiseLogan Gunthorpe
Currently the Switchtec quirk runs on all endpoints in the switch, including all the upstream and downstream ports. These other functions do not contain BARs, so the quirk fails when trying to map the BAR and prints the error "Cannot iomap Switchtec device". The user will see a few of these useless and scary errors, one for each port in the switch. At most, the quirk should only run on either a management endpoint (PCI_CLASS_MEMORY_OTHER) or an NTB endpoint (PCI_CLASS_BRIDGE_OTHER). However, the quirk is useless except in NTB applications, so we will only run it when the class is PCI_CLASS_BRIDGE_OTHER. Switch to using DECLARE_PCI_FIXUP_CLASS_FINAL and only match PCI_CLASS_BRIDGE_OTHER. Reported-by: Stephen Bates <sbates@raithlin.com> Fixes: ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB") Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: split SWITCHTEC_QUIRK() introduction to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Doug Meyer <dmeyer@gigaio.com> Cc: Kurt Schwemmer <kurt.schwemmer@microsemi.com>
2018-10-11PCI: Add macro for Switchtec quirk declarationsLogan Gunthorpe
Add SWITCHTEC_QUIRK() to reduce redundancy in declaring devices that use quirk_switchtec_ntb_dma_alias(). By itself, this is no functional change, but a subsequent patch updates SWITCHTEC_QUIRK() to fix ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB"). Fixes: ad281ecf1c7d ("PCI: Add DMA alias quirk for Microsemi Switchtec NTB") Signed-off-by: Logan Gunthorpe <logang@deltatee.com> [bhelgaas: split to separate patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-10-11PCI: Add Device IDs for Intel GPU "spurious interrupt" quirkBin Meng
Add Device IDs to the Intel GPU "spurious interrupt" quirk table. For these devices, unplugging the VGA cable and plugging it in again causes spurious interrupts from the IGD. Linux eventually disables the interrupt, but of course that disables any other devices sharing the interrupt. The theory is that this is a VGA BIOS defect: it should have disabled the IGD interrupt but failed to do so. See f67fd55fa96f ("PCI: Add quirk for still enabled interrupts on Intel Sandy Bridge GPUs") and 7c82126a94e6 ("PCI: Add new ID for Intel GPU "spurious interrupt" quirk") for some history. [bhelgaas: See link below for discussion about how to fix this more generically instead of adding device IDs for every new Intel GPU. I hope this is the last patch to add device IDs.] Link: https://lore.kernel.org/linux-pci/1537974841-29928-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Bin Meng <bmeng.cn@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v3.4+
2018-10-11TC: Set DMA masks for devicesMaciej W. Rozycki
Fix a TURBOchannel support regression with commit 205e1b7f51e4 ("dma-mapping: warn when there is no coherent_dma_mask") that caused coherent DMA allocations to produce a warning such as: defxx: v1.11 2014/07/01 Lawrence V. Stefani and others tc1: DEFTA at MMIO addr = 0x1e900000, IRQ = 20, Hardware addr = 08-00-2b-a3-a3-29 ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1 at ./include/linux/dma-mapping.h:516 dfx_dev_register+0x670/0x678 Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 4.19.0-rc6 #2 Stack : ffffffff8009ffc0 fffffffffffffec0 0000000000000000 ffffffff80647650 0000000000000000 0000000000000000 ffffffff806f5f80 ffffffffffffffff 0000000000000000 0000000000000000 0000000000000001 ffffffff8065d4e8 98000000031b6300 ffffffff80563478 ffffffff805685b0 ffffffffffffffff 0000000000000000 ffffffff805d6720 0000000000000204 ffffffff80388df8 0000000000000000 0000000000000009 ffffffff8053efd0 ffffffff806657d0 0000000000000000 ffffffff803177f8 0000000000000000 ffffffff806d0000 9800000003078000 980000000307b9e0 000000001e900000 ffffffff80067940 0000000000000000 ffffffff805d6720 0000000000000204 ffffffff80388df8 ffffffff805176c0 ffffffff8004dc78 0000000000000000 ffffffff80067940 ... Call Trace: [<ffffffff8004dc78>] show_stack+0xa0/0x130 [<ffffffff80067940>] __warn+0x128/0x170 ---[ end trace b1d1e094f67f3bb2 ]--- This is because the TURBOchannel bus driver fails to set the coherent DMA mask for devices enumerated. Set the regular and coherent DMA masks for TURBOchannel devices then, observing that the bus protocol supports a 34-bit (16GiB) DMA address space, by interpreting the value presented in the address cycle across the 32 `ad' lines as a 32-bit word rather than byte address[1]. The architectural size of the TURBOchannel DMA address space exceeds the maximum amount of RAM any actual TURBOchannel system in existence may have, hence both masks are the same. This removes the warning shown above. References: [1] "TURBOchannel Hardware Specification", EK-369AA-OD-007B, Digital Equipment Corporation, January 1993, Section "DMA", pp. 1-15 -- 1-17 Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20835/ Fixes: 205e1b7f51e4 ("dma-mapping: warn when there is no coherent_dma_mask") Cc: stable@vger.kernel.org # 4.16+ Cc: Ralf Baechle <ralf@linux-mips.org>
2018-10-11MAINTAINERS: add Jarkko as maintainer for trusted keysMimi Zohar
Trusted keys are variable length random numbers generated by the TPM, which are used as symmetric keys. The trusted key is never exported to userspace in the clear. Adding Jarrko, the TPM maintainer. Signed-off-by: Mimi Zohar <zohar@linux.ibm.com>
2018-10-11dm: rename DM_TYPE_MQ_REQUEST_BASED to DM_TYPE_REQUEST_BASEDMike Snitzer
Now that request-based DM is only using blk-mq, there is no need to differentiate between legacy "rq" and new "mq". We're back to a single request-based DM -- and there was much rejoicing! Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2018-10-11dm: remove legacy request-based IO pathJens Axboe
dm supports both, and since we're killing off the legacy path in general, get rid of it in dm. Signed-off-by: Jens Axboe <axboe@kernel.dk> Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2018-10-11s390/vmalloc: fix VMALLOC_START calculationMikhail Zaslonko
With the introduction of the module area on top of the vmalloc area, the calculation of VMALLOC_START in setup_memory_end() function hasn't been adjusted. As a result we got vmalloc area 2 Gb (MODULES_LEN) smaller than it should be and the preceding vmemmap area got extra memory instead. The patch fixes this calculation error although there were no visible negative effects. Apart from that, change 'tmp' variable to 'vmemmap' in memory_end calculation for better readability. Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Mikhail Zaslonko <zaslonko@linux.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2018-10-11ASoC: max98373: Sort DHT Rot Pnt Volume in reverse orderRyan Lee
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11ASoC: max98373: Sort max98373_bde_gain_tlv in reverse orderRyan Lee
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11ASoC: max98373: Sort BDE Limiter Thresh Volume in reverse orderRyan Lee
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11ASoC: max98373: Sort Digital Volume in reverse orderRyan Lee
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi/spi-pxa2xx: add PXA2xx SSP SPI ControllerLubomir Rintel
This is the SPI controller found on Marvel MMP2 and perhaps more platforms. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: pxa2xx: Add devicetree supportLubomir Rintel
The MMP2 platform, that uses device tree, has this controller. Let's add devicetree alongside platform & PCI. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: pxa2xx: Use an enum for typeLubomir Rintel
That seems to be the correct type. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: spi-geni-qcom: Add SPI driver support for GENI based QUPGirish Mahadevan
This driver supports GENI based SPI Controller in the Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable module supporting a wide range of serial interfaces including SPI. This driver supports SPI operations using FIFO mode of transfer. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Dilip Kota <dkota@codeaurora.org> Signed-off-by: Alok Chauhan <alokc@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: soc: qcom: GENI SE SPI controller device tree bindingDilip Kota
Move GENI SE SPI controller device-tree bindings from devicetree/bindings/soc/qcom/qcom,geni-se.txt to devicetree/bindings/spi/qcom,spi-geni-qcom.txt. Signed-off-by: Dilip Kota <dkota@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alok Chauhan <alokc@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11dt-bindings: soc: qcom: Remove SPI controller maximum frequency bindingDilip Kota
SPI controller driver should maintain the maximum frequency of the controller instead of relying on device tree bindings. Because maximum frequency is specific property of SPI controller. Signed-off-by: Dilip Kota <dkota@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alok Chauhan <alokc@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: rockchip: simplify spi enable logicEmil Renner Berthing
Let the dma/non-dma code paths handle the spi enable flag themselves. This removes some logic to determine if the flag should be turned on before or after dma and also don't leave the spi enabled if the dma path fails. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: rockchip: directly use direction constantsEmil Renner Berthing
The dma direction for the tx and rx dma channels never change, so just use the constants directly rather than storing them in device data. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: rockchip: mark use_dma as boolEmil Renner Berthing
The driver data has a u32 field use_dma which is only ever used as a boolean, so change its type to reflect that. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: rockchip: remove unneeded dma_capsEmil Renner Berthing
We no longer need the dma_caps since the dma driver already clamps the burst length to the hardware limit, so don't request and store dma_caps in device data. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: rockchip: adjust dma watermark and burstlenHuibin Hong
Signal tx dma when spi fifo is less than half full, and limit tx bursts to half the fifo length. Clamp rx burst length to 1 to avoid alignment issues. Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11perf vendor events intel: Fix wrong filter_band* values for uncore eventsJiri Olsa
Michael reported that he could not stat following event: $ perf stat -e unc_p_freq_ge_1200mhz_cycles -a -- ls event syntax error: '..e_1200mhz_cycles' \___ value too big for format, maximum is 255 Run 'perf list' for a list of valid events The event is unwrapped into: uncore_pcu/event=0xb,filter_band0=1200/ where filter_band0 format says it's one byte only: # cat uncore_pcu/format/filter_band0 config1:0-7 while JSON files specifies bigger number: "Filter": "filter_band0=1200", all the filter_band* formats show 1 byte width: # cat uncore_pcu/format/filter_band1 config1:8-15 # cat uncore_pcu/format/filter_band2 config1:16-23 # cat uncore_pcu/format/filter_band3 config1:24-31 The reason of the issue is that filter_band* values are supposed to be in 100Mhz units.. it's stated in the JSON help for the events, like: filter_band3=XXX, with XXX in 100Mhz units This patch divides the filter_band* values by 100, plus there's couple of changes that actually change the number completely, like: - "Filter": "edge=1,filter_band2=4000", + "Filter": "edge=1,filter_band2=30", Reported-by: Michael Petlan <mpetlan@redhat.com> Signed-off-by: Jiri Olsa <jolsa@kernel.org> Acked-by: Andi Kleen <ak@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20181010080339.GB15790@krava Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2018-10-11spi: rockchip: initialize dma_slave_config properlyHuibin Hong
The rxconf and txconf structs are allocated on the stack, so make sure we zero them before filling out the relevant fields. Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: Introduce new driver for Qualcomm QuadSPI controllerGirish Mahadevan
New driver for Qualcomm QuadSPI(QSPI) controller that is used to communicate with slaves such as flash memory devices. The QSPI controller can operate in 2 or 4 wire mode but only supports SPI Mode 0. The controller can also operate in Single or Dual data rate modes. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Ryan Case <ryandcase@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: Qualcomm Quad SPI(QSPI) documentationGirish Mahadevan
Bindings for Qualcomm Quad SPI used on SoCs such as sdm845. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Ryan Case <ryandcase@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11dw: spi: add support for Amazon's Alpine spi controllerTalel Shenhar
Add support for a new devicetree compatible string called 'amazon,alpine-apb-ssi', which is necessary for the Amazon Alpine spi controller. 'amazon,alpine-dw-apb-ssi' is used in the dw spi driver if specified in the devicetree. Otherwise, fall back to driver default behavior, i.e. original dw IP hw driver behavior. Signed-off-by: Talel Shenhar <talel@amazon.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11spi: dw: add compatible for Amazon's Alpine spi controllerTalel Shenhar
This compatible adds the ability for dw spi controller driver to work with the dw spi controller found on Alpine chips. The dw spi controller has an auto-deselect of Chip-Select, in case there is no data inside the Tx FIFO. While working on platforms with Alpine chips, auto-deselect mode causes an issue for some spi devices that can't handle the Chip-Select deselect in the middle of a transaction. It is a normal behavior for a Tx FIFO to be empty in the middle of a transaction, due to busy cpu. In the Alpine chip family an option to change the default behavior was added to the original dw spi controller to prevent this issue of de-asserting Chip-Select once TX FIFO is empty. The change was to allow SW manual control of the Chip-Select. With this change, as long as the Slave Enable Register is asserted, the Chip-Select will be asserted. As a result, it is necessary to deselect the Slave Select Register once the transaction is done. This feature is enabled via a new device compatible string called 'amazon,alpine-dw-apb-ssi'. Once the driver identifies the new compatible string, it enables the hw fixup logic, by writing to a dedicated register found in the IP reserved area and will start manual deselecting the Slave Select Register when the transfer ends. Signed-off-by: Talel Shenhar <talel@amazon.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-11Merge tag 'qcom-geni-immutable-for-mark-brown' of ↵Mark Brown
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into spi-4.20 Immutable branch for QCOM Geni patches
2018-10-11mac80211: Extend SAE authentication in infra BSS STA modeJouni Malinen
Previous implementation of SAE authentication in infrastructure BSS was somewhat restricting and not exactly clean way of handling the two auth() operations. This ended up removing and re-adding the STA entry for the AP in the middle of authentication and also messing up authentication state tracking through the sequence of four Authentication frames. Furthermore, this did not work if the AP ended up sending out SAE Confirm (auth trans #2) immediately after SAE Commit (auth trans #1) before the station had time to transmit its SAE Confirm. Clean up authentication state handling for the SAE case to allow two rounds of auth() calls without dropping all state between those operations. Track peer Confirmed status and mark authentication completed only once both ends have confirmed. ieee80211_mgd_auth() check for EBUSY cases is now handling only the pending association (ifmgd->assoc_data) while all pending authentication (ifmgd->auth_data) cases are allowed to proceed to allow user space to start a new connection attempt from scratch even if the previously requested authentication is still waiting completion. This is needed to avoid making SAE error cases with retries take excessive amount of time with no means for the user space to stop that (apart from setting the netdev down). As an extra bonus, the end of ieee80211_rx_mgmt_auth() can be cleaned up to avoid the extra copy of the cfg80211_rx_mlme_mgmt() call for ongoing SAE authentication since the new ieee80211_mark_sta_auth() helper function can handle both completion of authentication and updates to the STA entry under the same condition and there is no need to return from the function between those operations. Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2018-10-11mac80211: Move ieee80211_mgd_auth() EBUSY check to be before allocationJouni Malinen
This makes it easier to conditionally replace full allocation of auth_data to use reallocation for the case of continuing SAE authentication. Furthermore, there was not really any point in having this check done so late in the function after having already completed number of steps that cannot be used anyway in the error case. Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2018-10-11mac80211: Helper function for marking STA authenticatedJouni Malinen
Authentication exchange can be completed in both TX and RX paths for SAE, so move this common functionality into a helper function to avoid having to implement practically the same operations in two places when extending SAE implementation in the following commits. Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2018-10-11mac80211: rc80211_minstrel: remove variance / stddev calculationFelix Fietkau
When there are few packets (e.g. for sampling attempts), the exponentially weighted variance is usually vastly overestimated, making the resulting data essentially useless. As far as I know, there has not been any practical use for this, so let's not waste any cycles on it. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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