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2019-06-19arm64: dts: qcom: msm8996: Enable SMMUsBjorn Andersson
Enable SMMUs on 8996 now that the WRZ workaround in the arm-smmu driver has landed. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-06-18arm64: dts: qcom: msm8996: Correct apr-domain propertyBjorn Andersson
The domain specifier was changed from using "reg" to "qcom,apr-domain", update the dts accordingly. Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-18arm64: dts: qcom: Add Dragonboard 845cBjorn Andersson
This adds an initial dts for the Dragonboard 845. Supported functionality includes Debug UART, UFS, USB-C (peripheral), USB-A (host), microSD-card and Bluetooth. Initializing the SMMU is clearing the mapping used for the splash screen framebuffer, which causes the board to reboot. This can be worked around using: fastboot oem select-display-panel none Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Vinod Koul <vkoul@kernel.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-18dt-bindings: arm: fsl: Add missing schemas for i.MX1/31/35Rob Herring
The SoC/board bindings for i.MX1/31/35 are undocumented. Add the missing bindings to the schema. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: arm: fsl: Add back missing i.MX7ULP bindingRob Herring
In the conversion to DT schema, the addition of the i.MX7ULP binding got dropped. Add it to the binding schema. Fixes: a1a38e1f4d1d ("dt-bindings: arm: Convert FSL board/soc bindings to json-schema") Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: arm: Move Emtrion i.MX6 board bindings to schemaRob Herring
The Emtrion board bindings landed when the i.MX board/SoC bindings were being converted to DT schema. Add them to the schema and remove the separate file. Cc: Jan Tuerk <jan.tuerk@emtrion.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkitAngus Ainslie (Purism)
This is for the development kit board for the Librem 5. The current level of support yields a working console and is able to boot userspace from the network or eMMC. Additional subsystems that are active : - Both USB ports - SD card socket - WiFi usdhc - WWAN modem - GNSS - GPIO keys - LEDs - gyro - magnetometer - touchscreen - pwm - backlight - haptic motor Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: arm: fsl: Add the imx8mq boardsAngus Ainslie (Purism)
Add an entry for imx8mq based boards Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: Add an entry for Purism SPCAngus Ainslie (Purism)
Add an entry for Purism, SPC Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: fsl: ls1028a: Add qDMA nodePeng Ma
Add the qDMA device tree nodes for LS1028A devices Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: fsl-qdma: Add LS1028A qDMA bindingsPeng Ma
Add LS1028A qDMA controller bindings to fsl-qdma bindings. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: renesas: r8a774a1: Add dynamic power coefficientBiju Das
Describe the dynamic power coefficient of A57 and A53 CPUs. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: r8a774a1: Create thermal zone to support IPABiju Das
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on work by Dien Pham <dien.pham.ry@renesas.com> for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhzBiju Das
Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on dhrystone. Based on work done by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC. The average dhrystone result for 5 iterations is as below: r8a774a1 SoC (CA57x2 + CA53x4) CPU max-freq dhrystone --------------------------------- CA57 1500 MHz 11428571 lps/s CA53 1200 MHz 5000000 lps/s From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated as follows: r8a774a1 SoC CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024 CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560 Since each CPUs have different max frequencies, the final CPU capacities of A53 scaled by the above difference is as below $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 448 448 448 448 Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: r8a774a1: Add CPU topology on r8a774a1 SoCBiju Das
This patch adds the "cpu-map" into r8a774a1 composed of multi-cluster. This definition is used to parse the cpu topology. Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: hihope-common: Add LEDs supportFabrizio Castro
This patch adds LEDs support to the HiHope RZ/G2[MN] Main Board common device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: renesas: hihope-common: Enable USB3.0Biju Das
This patch enables USB3.0 host/peripheral device node for the HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-18arm64: dts: marvell: add missing #interrupt-cells propertyRussell King
The GPIO interrupt controllers are missing their required specified in DT. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-06-18ARM: dts: imx7d-zii-rpu2: Drop unused pinmux entriesAndrey Smirnov
Neither pinctrl_i2c1_gpio nor pinctrl_i2c2_gpio are used anywhere in the file, drop them. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx7d-zii-rpu2: Fix incorrrect 'stdout-path'Andrey Smirnov
RPU2 uses UART2 as a serial console and UART1 is not used at all. Fix incorrrectly specified 'stdout-path' to reflect that. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: Add support for 96Boards Meerkat96 boardManivannan Sadhasivam
Add devicetree support for 96Boards Meerkat96 board from Novtech. This board is one of the Consumer Edition boards of the 96Boards family based on i.MX7D SoC. Following are the currently supported features of the board: * uSD * WiFi/BT * USB More information about this board can be found in 96Boards product page: https://www.96boards.org/product/imx7-96/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18dt-bindings: arm: Document 96Boards Meerkat96 devicetree bindingManivannan Sadhasivam
Document 96Boards Meerkat96 devicetree binding based on i.MX7D SoC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6ul: Add PXP nodeSébastien Szymanski
Add PXP node for i.MX6UL/L SoC. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6sll: Enable SNVS poweroff according to board designAnson Huang
The SNVS poweroff depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up to external PMIC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx7s: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6sll: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6ul: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6sx: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18ARM: dts: imx6qdl: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: imx8mm: Enable SNVS power key according to board designAnson Huang
The SNVS power key depends on board design, by default it should be disabled in SoC DT and ONLY be enabled on board DT if it is wired up. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: imx8mq-evk: Enable SNVS power keyAnson Huang
Enable SNVS power key for i.MX8MQ EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18arm64: dts: ls1028a: add crypto nodeHoria Geantă
LS1028A has a SEC v5.0 compatible security engine. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-17arm64: dts: qcom: qcs404-evb: Enable PCIeBjorn Andersson
Enable the PCIe PHY and controller found on the QCS404 EVB. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17arm64: dts: qcom: qcs404: Add PCIe related nodesBjorn Andersson
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, define these to for the platform. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodesMarc Gonzalez
Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes. Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17arm64: dts: qcom: msm8998: Add ANOC1 SMMU nodeMarc Gonzalez
The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB. (*) Aggregate Network-on-Chip #1 Based on the following DTS downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-17arm64: dts: ti: am654-base-board: Disable SERDES and PCIeKishon Vijay Abraham I
AM654 base board does not have any PCIe slots. Disable all the SERDES and PCIe instances. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Endpoint DT nodeKishon Vijay Abraham I
Add PCIe Endpoint DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Root Complex DT nodeKishon Vijay Abraham I
Add PCIe Root Complex DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add SERDES DT nodeKishon Vijay Abraham I
Add DT node for SERDES0 and SERDES1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDESKishon Vijay Abraham I
Add mux-controller DT node as a child node of scm_conf. This is required for muxing SERDES between USB, PCIe and ICSS2 SGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_itsKishon Vijay Abraham I
GIC_ITS used in AM654 platform has the same configuration as that of GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its" property to get PCI MSI working. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect nodeRoger Quadros
Add the MSCM RAM address space to the ranges property of the cbass_main interconnect node so that the addresses can be translated properly. This fixes the probe failure in the sram driver for the MSMC RAM node. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodesSuman Anna
Add the address spaces for the R5F cores in MCU domain to the ranges property of the cbass_mcu interconnect node so that the addresses within the R5F nodes can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65-mcu: Add the MCU RAM nodeSuman Anna
Add the on-chip SRAM present within the MCU domain as a mmio-sram node. The K3 AM65x SoCs have 512 KB of such memory. Any specific memory range within this RAM needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodesSuman Anna
Add the address space for the MCU SRAM memory to the ranges property of the cbass_mcu interconnect node so that the addresses within the mcu_sram nodes and its children can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am654-base-board: Add gpio_keys nodeKeerthy
There are 2 push buttons: SW5 and SW6 that are basically connected to WKUP_GPIO0_24 and WKUP_GPIO0_27 respectively. Add the respective nodes and the pinctrl data to set the mode to GPIO and Input. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am6-main: Add gpio nodesKeerthy
Add gpio0/1 nodes under main domain. They have 96 and 90 gpios respectively and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am6-wakeup: Add gpio nodeKeerthy
Add gpio0 node under wakeup domain. This has 56 gpios and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am654: Add interrupt controllers in wakeup domainLokesh Vutla
Wakeup domain in AM654 SoC has an interrupt router connected to gpio in wakeup domain. Add DT node for this interrupt router. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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