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2020-01-08ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPPMartin Blumenstingl
The clock setup on Meson8 cannot achieve a Mali frequency of exactly 182.15MHz. The vendor driver uses "FCLK_DIV7 / 1" for this frequency, which translates to 2550MHz / 7 / 1 = 364285714Hz. Update the GPU operating point to that specific frequency to not confuse myself when comparing the frequency from the .dts with the actual clock rate on the system. Fixes: c3ea80b6138cae ("ARM: dts: meson8b: add the Mali-450 MP2 GPU") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2020-01-08ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPPMartin Blumenstingl
The clock setup on Meson8 cannot achieve a Mali frequency of exactly 182.15MHz. The vendor driver uses "FCLK_DIV7 / 2" for this frequency, which translates to 2550MHz / 7 / 2 = 182142857Hz. Update the GPU operating point to that specific frequency to not confuse myself when comparing the frequency from the .dts with the actual clock rate on the system. Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2020-01-08ARM: dts: meson8b: fix the clock controller compatible stringMartin Blumenstingl
The Meson8b clock controller is an evolution of the Meson8 clock controller. The clock controller on Meson8b contains two identical mali clock trees for glitch-free rate switching. Use the correct compatible string to make use of the glitch free mux. Fixes: b6db3936f2833c ("ARM: dts: meson: switch the clock controller to the HHI register area") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2020-01-08Merge tag 'aspeed-5.5-devicetree-fixes' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/fixes ASPEED device tree fixes for 5.5 Fixes for some badly applied patches that went in to 5.5. There is also a fix for an incorrect i2c address. * tag 'aspeed-5.5-devicetree-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: dts: aspeed: rainier: Fix fan fault and presence ARM: dts: aspeed: rainier: Remove duplicate i2c busses ARM: dts: aspeed: tacoma: Remove duplicate flash nodes ARM: dts: aspeed: tacoma: Remove duplicate i2c busses ARM: dts: aspeed: tacoma: Fix fsi master node ARM: dts: aspeed-g6: Fix FSI master location Link: https://lore.kernel.org/r/CACPK8XcjazgORXNZBU1ECMukXG4HA8D9VeDxiSPifDk_iB7_dw@mail.gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-08ARM: omap2plus: select RESET_CONTROLLERArnd Bergmann
With the new omap_prm driver added unconditionally, omap2 builds fail when the reset controller subsystem is disabled: drivers/soc/ti/omap_prm.o: In function `omap_prm_probe': omap_prm.c:(.text+0x2d4): undefined reference to `devm_reset_controller_register' Link: https://lore.kernel.org/r/20191216132132.3330811-1-arnd@arndb.de Fixes: 3e99cb214f03 ("soc: ti: add initial PRM driver with reset control support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-08ARM: davinci: select CONFIG_RESET_CONTROLLERArnd Bergmann
Selecting RESET_CONTROLLER is actually required, otherwise we can get a link failure in the clock driver: drivers/clk/davinci/psc.o: In function `__davinci_psc_register_clocks': psc.c:(.text+0x9a0): undefined reference to `devm_reset_controller_register' drivers/clk/davinci/psc-da850.o: In function `da850_psc0_init': psc-da850.c:(.text+0x24): undefined reference to `reset_controller_add_lookup' Link: https://lore.kernel.org/r/20191210195202.622734-1-arnd@arndb.de Fixes: f962396ce292 ("ARM: davinci: support multiplatform build for ARM v5") Cc: <stable@vger.kernel.org> # v5.4 Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-08Merge tag 'tags/bcm2835-dt-next-2020-01-07' into devicetree/nextFlorian Fainelli
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-08ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/startQuanyang Wang
When kernel booting, it will create a cpuid map between the logical cpus and physical cpus. In a normal boot, the cpuid map is as below: Physical Logical 0 ==> 0 1 ==> 1 But in kdump, there is a condition that the crash happens at the physical cpu1, and the crash kernel will run at the physical cpu1 too, so the cpuid map in crash kernel is as below: Physical Logical 1 ==> 0 0 ==> 1 The functions zynq_slcr_cpu_stop/start is to stop/start the physical cpus, the parameter cpu should be the physical cpuid. So use cpu_logical_map to translate the logical cpuid to physical cpuid. Or else the logical cpu0(physical cpu1) will stop itself and the processor will hang. Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-08ARM: tegra: Use clk_m CPU on Tegra124 LP1 resumeStephen Warren
Configure the clock controller to set an alternate clock for the CPU when it receives an IRQ during LP1 (system suspend). Specifically, use clk_m (the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will be the LP1 wake event. This reduces the amount of time taken to resume from LP1. NVIDIA's downstream kernel executes this code on both Tegra30 and Tegra124, so it appears OK to make this change unconditionally. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08ARM: tegra: Modify reshift divider during LP1Stephen Warren
The reshift hardware module implements the RAM re-repair process. This module uses PLLP as an input clock during LP1 resume. The input divider for this clock is typically set for PLLP's normal rate. During LP1 resume, PLLP is bypassed and so runs at the crystal rate, which is much slower. Consequently, decrease the divider so that the reshift module runs at a reasonable rate during LP1 resume. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08ARM: tegra: Enable PLLP bypass during Tegra124 LP1Stephen Warren
For a little over a year, U-Boot has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail[1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. PLLP is one of those clocks. This clock is shut down during LP1 in order to save power. Enable bypass (which I believe routes osc_div_clk, essentially the crystal clock, to the PLL output) so that this clock signal toggles even though the PLL is not active. This is required so that LP1 power mode (system suspend) operates correctly. The bypass configuration must then be undone when resuming from LP1, so that all peripheral clocks run at the expected rate. Without this, many peripherals won't work correctly; for example, the UART baud rate would be incorrect. NVIDIA's downstream kernel code only does this if not compiled for Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's downstream code makes this change conditional upon the active CPU cluster. The upstream kernel currently doesn't support cluster switching, so this patch doesn't test the active CPU cluster ID. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08ARM: dts: armada-388-clearfog: add eepromBaruch Siach
SolidRun Clearfog Pro rev 2.1 and Clearfog Base rev 1.3 added EEPROM. Add DT node for EEPROM description in the .dtsi shared by Clearfog Pro and Base. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08ARM: dts: armada-38x-solidrun-microsom: add eepromBaruch Siach
SolidRun Armada 38x SOM rev 2.1 added EEPROM. Add DT node for EEPROM description. Cc: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08ARM: armada-38x-solidrun-microsom: move i2c0 to SOM DTBaruch Siach
Move the i2c0 controller properties to the SOM .dtsi. This is preparation for adding an i2c device at the SOM level. Cc: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08ARM: dts: mvebu: add support for SolidRun Clearfog GTRBaruch Siach
SolidRun Clearfog GTR L8 and S4 SBCs are based on Armada 385. They features 8 (L8) or 4 (S4) switched Ethernet ports, 1 1Gb Ethernet port, 1 directly connected SFP port, 1 SFP port behind the switch (not currently described in DT), 3 mini-PCIe slots, eMMC, SPI flash, USB3 port. https://developer.solid-run.com/products/clearfog-gtr-a385/ Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08ARM: dts: aspeed: rainier: Fix fan fault and presenceBrandon Wyman
The PCA9552 used for fan fault and presence information is at address 61h, not 60h. Fixes: 2efc118ce3c3 ("ARM: dts: aspeed: rainier: Add i2c devices") Signed-off-by: Brandon Wyman <bjwyman@gmail.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: rainier: Remove duplicate i2c bussesJoel Stanley
This is a revert of "ARM: dts: aspeed: rainier: Add i2c devices", which was already applied to the tree. Fixes: 9c44db7096e0 ("ARM: dts: aspeed: rainier: Add i2c devices") Reviewed-by: Jim Wright <wrightj@linux.vnet.ibm.com> Tested-by: Jim Wright <wrightj@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Remove duplicate flash nodesJoel Stanley
This is a revert of "ARM: dts: aspeed: tacoma: Enable FMC and SPI devices" which was already applied as part of "ARM: dts: aspeed: Add Tacoma machine". Fixes: 8737481e381c ("ARM: dts: aspeed: tacoma: Enable FMC and SPI devices") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Remove duplicate i2c bussesJoel Stanley
This is a revert of "ARM: dts: aspeed: tacoma: Enable I2C busses", which was already applied as part of "ARM: dts: aspeed: Add Tacoma machine". Fixes: 606bcdde6724 ("ARM: dts: aspeed: tacoma: Enable I2C busses") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed: tacoma: Fix fsi master nodeJoel Stanley
This was broken when applying "ARM: dts: aspeed: tacoma: Add host FSI description". Fixes: a981c93300ef ("ARM: dts: aspeed: tacoma: Add host FSI description") Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-08ARM: dts: aspeed-g6: Fix FSI master locationJoel Stanley
The FIS nodes were placed incorrectly in the device tree. Fixes: 0fe4e304782c ("ARM: dts: aspeed-g6: Describe FSI masters") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-01-07ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tigerMatthias Kaehlcke
The flash write protect pin is currently named 'FW_WP_AP', which is how the signal is called in the schematics. The Chrome OS ABI requires the pin to be named 'AP_FLASH_WP_L', which is also how it is called on all other veyron devices. Rename the pin to match the ABI. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200106135142.1.I3f99ac8399a564c88ff48ae6290cc691b47c16ae@changeid Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-07ARM: dts: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07ARM: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07ARM: exynos: Correct the help text for platform Kconfig optionKrzysztof Kozlowski
ARCH_EXYNOS option is used for entire ARMv7 Exynos family, including also Exynos3 SoCs. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07Merge tag 'omap-for-v5.6/ti-sysc-drop-pdata-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Drop more legacy platform data for omaps for v5.6 merge window We can now probe devices with ti-sysc interconnect driver and dts data, and can continue dropping the related platform data and custom ti,hwmods dts property for various devices. And related to that, we finally can remove the legacy sdma support in favor of using the dmaengine driver only. I was planning to send the sdma changes separately, but that would have produced a pile of pointless merge conflicts, so I decided it's best to resolve it locally. After all, the sdma series also ends up removing the related platform data. Note that this series is based on omap-for-v5.6/ti-sysc-dt-signed branch as it depends for dts data being in place. * tag 'omap-for-v5.6/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (56 commits) ARM: OMAP2+: Drop legacy platform data for sdma ARM: OMAP2+: Drop legacy init for sdma dmaengine: ti: omap-dma: Use cpu notifier to block idle for omap2 dmaengine: ti: omap-dma: Allocate channels directly dmaengine: ti: omap-dma: Pass sdma auxdata to driver and use it dmaengine: ti: omap-dma: Configure global priority register directly ARM: OMAP5: hwmod-data: remove OMAP5 IOMMU hwmod data ARM: OMAP4: hwmod-data: remove OMAP4 IOMMU hwmod data ARM: OMAP2+: Drop legacy platform data for omap4 fdif ARM: OMAP2+: Drop legacy platform data for omap4 slimbus ARM: OMAP2+: Drop legacy platform data for omap5 kbd ARM: OMAP2+: Drop legacy platform data for omap4 kbd ARM: OMAP2+: Drop legacy platform data for dra7 smartreflex ARM: OMAP2+: Drop legacy platform data for omap4 smartreflex ARM: OMAP2+: Drop legacy platform data for omap4 hsi ARM: OMAP2+: Drop legacy platform data for am4 vpfe ARM: OMAP2+: Drop legacy platform data for dra7 ocp2scp ARM: OMAP2+: Drop legacy platform data for omap5 ocp2scp ARM: OMAP2+: Drop legacy platform data for omap4 ocp2scp ARM: OMAP2+: Drop legacy platform data for am4 ocp2scp ... Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-4 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge branch 'omap/soc' into arm/dtOlof Johansson
Bringing in to resolve soc -> add/add conflicts locally * omap/soc: ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot ARM: OMAP2+: omap-iommu.c conversion to ti-sysc ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 ARM: OMAP4+: remove pdata quirks for omap4+ iommus ARM: OMAP2+: pdata-quirks: add PRM data for reset support ARM: OMAP2+: am43xx: Add lcdc clockdomain Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/ti-sysc-dt-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt dts changes for omaps for ti-sysc driver for v5.6 merge window Devicetree changes for omaps to configure more devices to probe with ti-sysc interconnect target module: - Configure am4 qspi - Configure aes, des and sham accelerators for am3, 4 and dra7 - Configure iommus for omap4, 5 and dra7 - Add a generic compatible for sdma, and configure omap2 and 3 sdma * tag 'omap-for-v5.6/ti-sysc-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (24 commits) ARM: dts: omap5: convert IOMMUs to use ti-sysc ARM: dts: omap4: convert IOMMUs to use ti-sysc ARM: dts: dra74x: convert IOMMUs to use ti-sysc ARM: dts: dra7: convert IOMMUs to use ti-sysc ARM: dts: Configure interconnect target module for dra7 des ARM: dts: Configure interconnect target module for am4 des ARM: dts: Configure interconnect target module for dra7 aes ARM: dts: Configure interconnect target module for am4 aes ARM: dts: Configure interconnect target module for am3 aes ARM: dts: Configure interconnect target module for dra7 sham ARM: dts: Configure interconnect target module for am4 sham ARM: dts: Configure interconnect target module for am3 sham ARM: dts: Configure interconnect target module for am4 qspi ARM: dts: Configure interconnect target module for omap3 sdma ARM: dts: Configure interconnect target module for omap2 sdma ARM: dts: Add generic compatible for omap sdma instances bus: ti-sysc: Fix iterating over clocks ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap bus: ti-sysc: Fix missing reset delay handling ARM: dts: am437x-gp/epos-evm: fix panel compatible ... Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/dt-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.6 merge window Devicetree changes for omaps for v5.6 to configure more devices and update boards to use generic lcd panels: - Configure HDMI for dra76-evm and am57xx-idk - Correct node name for am3517 mdio - Convert am335x-evm, am335x-evmsk, and am335x-icev2 to use generic panels * tag 'omap-for-v5.6/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ARM: dts: am335x-evmsk: Use drm simple-panel instead of tilcdc-panel ARM: dts: am335x-evm: Use drm simple-panel instead of tilcdc-panel ARM: dts: omap3: name mdio node properly ARM: dts: am57xx-idk-common: add HDMI to the common dtsi ARM: dts: dra76-evm: add HDMI output Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com-2 Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.6/soc-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc SoC changes for omaps for v5.6 merge window SoC related changes for omaps that mostly relate to making iommus to start probing with ti-sysc interconnect target module driver: - Add missing lcdc clockdomain for am43xx - Pass auxdata for reset control driver - Remove old pdata quirks for iommus - Add workaround for dra7 dsp mstandby errata - Convert iommu platform code to probe with ti-sysc - Use sperate iommu auxdata for ipu1 * tag 'omap-for-v5.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot ARM: OMAP2+: omap-iommu.c conversion to ti-sysc ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 ARM: OMAP4+: remove pdata quirks for omap4+ iommus ARM: OMAP2+: pdata-quirks: add PRM data for reset support ARM: OMAP2+: am43xx: Add lcdc clockdomain Link: https://lore.kernel.org/r/pull-1578420398-290837@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07Merge tag 'omap-for-v5.5/fixes-rc5' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Fixes for omaps for v5.5-rc cycle Here are few fixes for v5.5-rc cycle: - Two corner case fixes related to ti-sysc driver clock issues - Fixes for am57xx dts for pcie gpios - Beagle-x15 regulator dts fix - Fix for wkup_m3_ipc driver race * tag 'omap-for-v5.5/fixes-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: soc: ti: wkup_m3_ipc: Fix race condition with rproc_boot ARM: dts: beagle-x15-common: Model 5V0 regulator ARM: dts: am571x-idk: Fix gpios property to have the correct gpio number ARM: dts: am57xx-beagle-x15/am57xx-idk: Remove "gpios" for endpoint dt nodes bus: ti-sysc: Fix iterating over clocks ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap Link: https://lore.kernel.org/r/pull-1578418121-413328@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-07ARM: dts: bcm2711: Enable HWRNG supportStephen Brennan
This enables hardware random number generator support for the BCM2711 on the Raspberry Pi 4 board. Signed-off-by: Stephen Brennan <stephen@brennan.io> Acked-by: Stefan Wahren <wahrenst@gmx.net> [nsaenzjulienne@suse.de: remove unnecessary status="okay"] Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
2020-01-07ARM: dts: bcm2835: Move rng definition to common locationStephen Brennan
BCM2711 inherits from BCM283X, but has an incompatible HWRNG. Move this node to bcm2835-common.dtsi, so that BCM2711 can define its own. Signed-off-by: Stephen Brennan <stephen@brennan.io> Acked-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
2020-01-07arm: Implement copy_thread_tlsAmanieu d'Antras
This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-4-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
2020-01-06ARM: dts: sunxi: Use macros for references to CCU clocksChen-Yu Tsai
A few clocks from the CCU were exported later, and references to them in the device tree were using raw numbers. Now that the DT binding header changes are in as well, switch to the macros for more clarity. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxesAndre Przywara
The Allwinner R40 SoC contains four SPI controllers, using the newer sun6i design (but at the legacy addresses). The controller seems to be fully compatible to the A64 one, so no driver changes are necessary. The first three controllers can be used on two sets of pins, but SPI3 is only routed to one set on Port A. Only the pin groups for SPI0 on PortC and SPI1 on PortI are added here, because those seem to be the only one exposed on the Bananapi boards. Tested by connecting a SPI flash to a Bananapi M2 Berry SPI0 and SPI1 header pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06Merge branch 'mmp/hsic' into arm/dtOlof Johansson
* mmp/hsic: ARM: dts: mmp3: Fix typos
2020-01-06ARM: dts: mmp3: Fix typosOlof Johansson
Fixes build failures due to syntax errors. Fixes: 3240d5b872f2 ("ARM: dts: mmp3: Add HSIC controllers") Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge branch 'mmp/hsic' into arm/dtOlof Johansson
* mmp/hsic: ARM: dts: mmp3-dell-ariel: Enable the HSIC ARM: dts: mmp3: Add HSIC controllers dt-bindings: phy: Add binding for marvell,mmp3-hsic-phy clk: mmp2: Add HSIC clocks dt-bindings: marvell,mmp2: Add clock ids for the HSIC clocks + Linux 5.5-rc2
2020-01-06ARM: dts: mmp3-dell-ariel: Enable the HSICLubomir Rintel
There's a SMSC USB2640 (USB hub & SD controller) connected to it, but the SD card slot footprint is unpopulated. Also connected to the hub is a SMSC LAN7500 gigabit ethernet adapter. Link: https://lore.kernel.org/r/20191220065314.237624-6-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06ARM: dts: mmp3: Add HSIC controllersLubomir Rintel
There are two on MMP3, along with the PHYs. The PHYs are made compatible with the NOP transceiver, since there's no driver for the time being and they're likely configured by the firmware. Link: https://lore.kernel.org/r/20191220065314.237624-5-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge tag 'renesas-arm-dt-for-v5.6-tag1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.6 - Touch screen support for the iwg20d board, - ARM global timer support on Cortex-A9 MPCore SoCs, - Miscellaneous fixes for issues detected by "make dtbs_check". * tag 'renesas-arm-dt-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: dts: sh73a0: Add missing clock-frequency for fixed clocks ARM: dts: r8a7778: Add missing clock-frequency for fixed clocks ARM: dts: rcar-gen2: Add missing mmio-sram bus properties ARM: dts: rcar-gen2: Fix PCI high address in interrupt-map-mask ARM: dts: renesas: Group tuples in pci ranges and dma-ranges properties ARM: dts: renesas: Group tuples in interrupt properties ARM: dts: renesas: Group tuples in regulator-gpio states properties ARM: dts: r8a7779: Add device node for ARM global timer ARM: dts: sh73a0: Add device node for ARM global timer ARM: dts: sh73a0: Rename twd clock to periph clock ARM: dts: iwg20d-q7-common: Add LCD support Link: https://lore.kernel.org/r/20200106104857.8361-3-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge tag 'renesas-arm-defconfig-for-v5.6-tag1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig Renesas ARM defconfig updates for v5.6 - Enable support for the display panel on the iwg20d board. * tag 'renesas-arm-defconfig-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: defconfig: Enable support for panels from EDT ARM: shmobile: defconfig: Restore debugfs support Link: https://lore.kernel.org/r/20200106104857.8361-2-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06ARM: defconfig: gemini: Update defconfigLinus Walleij
This updates the gemini defconfig with Kconfig shuffling and some of the features activated in new upstream drivers and newly supported devices: - Move some symbols around due to Kconfig alterations, this affects CONFIG_PREEMPT, CONFIG_PCI, CONFIG_CMA, CONFIG_BINFMT_MISC, CONFIG_PARTITION_ADVANCED. - Add RedBoot partition parsing, as all the Gemini devices use some RedBoot derivative and store their flash partition tables in this format. - Enable bridge and VLAN filtering: a majority of the Gemini devices have some kind of DSA chip for ethernet bridging/routing. - Enable CONFIG_NET_DSA_REALTEK_SMI as this DSA router chip is found in the Gemini-based products. This makes explicit selection of CONFIG_REALTEK_PHY unnecessary so that goes away. - Enable CONFIG_TUN since Gemini userspace often make use of the TUN interface for network services. - Enable MARVELL_PHY as Marvell PHY connectors are often found in Gemini systems. - Enable basic 802.11 libraries as many Gemini systems have wireless PCI cards. Link: https://lore.kernel.org/r/20200101143520.14218-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge tag 'ux500-armsoc-v5.6-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into arm/dt Support the Samsung GT-I8190/Golden phone: - Proper include file for the AB8505 PMIC variant. - Add a DTS file for the GT-I8190/Golden - Extend the IMU, touch screen, WiFi and Bluetooth as separate patches. * tag 'ux500-armsoc-v5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: dts: ux500: samsung-golden: Add Bluetooth ARM: dts: ux500: samsung-golden: Add WiFi ARM: dts: ux500: samsung-golden: Add touch screen ARM: dts: ux500: samsung-golden: Add IMU (accelerometer + gyroscope) ARM: dts: ux500: Add device tree for Samsung Galaxy S III mini (GT-I8190) dt-bindings: arm: ux500: Document samsung,golden compatible ARM: dts: ux500: Add device tree include for AB8505 ARM: dts: ux500: Remove unused ste-href-ab8505.dtsi Link: https://lore.kernel.org/r/CACRpkdaN2Lv_rBEYNiyAarA81yea6Eky8w_htqZqdRng8S-DcA@mail.gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06ARM: dts: mmp3: Fix the TWSI rangesLubomir Rintel
The register blocks don't occupy 4K. In fact, some blocks are packed close to others and assuming they're 4K causes overlaps: pxa2xx-i2c d4033800.i2c: can't request region for resource [mem 0xd4033800-0xd40347ff] Link: https://lore.kernel.org/r/20191220071443.247183-1-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06ARM: mmp: do not divide the clock rateLubomir Rintel
This was done because the clock driver returned the wrong rate, which is fixed in "clk: mmp2: Fix the order of timer mux parents" patch. Link: https://lore.kernel.org/r/20191218190454.420358-2-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06ARM: dts: sun8i: r40: Add device node for CSI0Chen-Yu Tsai
The CSI0 and CSI1 blocks are the same as found on the A20. However only CSI0 is supported upstream right now. Add a device node for CSI0 using the A20 compatible as a fallback, and the standard pinctrl options. Also add the MBUS interconnect. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun7i: Add CSI1 controller and pinmux optionsChen-Yu Tsai
The CSI controller driver now supports the second CSI controller, CSI1. Add a device node for it. Pinmuxing options for the MCLK output, the standard 8-bit interface, and a secondary 24-bit interface are included. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-06ARM: dts: sun4i: Add CSI1 controller and pinmux optionsChen-Yu Tsai
The CSI controller driver now supports the second CSI controller, CSI1. Add a device node for it. Pinmuxing options for the MCLK output, the standard 8-bit interface, and a secondary 24-bit interface are included. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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