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2019-12-09Merge tag 'samsung-dt-5.5-2' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.5, part 2 1. Cleanup by adjusting DTS to bindings, 2. Add touch-sensitive buttons to Midas (Galaxy S III family phones), 3. Add GPU/Mali to Exynos542x and Odroid XU3/XU4 family. * tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4 ARM: dts: exynos: Add support for the touch-sensitive buttons on Midas family ARM: dts: exynos: Rename children of SysRAM node to "sram" Link: https://lore.kernel.org/r/20191119142026.7190-1-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746Benjamin Gaignard
On stm32f7 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429Benjamin Gaignard
On stm32f4 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on ↵Christophe Roullier
stm32mp15 When there is no activity on ethernet phy link, the ETH_GTX_CLK is cut. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15Christophe Roullier
ETH_MDIO slew-rate should be set to "0" instead of "2". Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: ux500: Add devicetree for HREF520Linus Walleij
This reference design is very similar to the others just that it has a different display mounted on the user interface board, and some GPIOs where shuffled around. As this is the first board that uses DB8520 we create the DB8520-specific DTSI file here. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-3-linus.walleij@linaro.org
2019-12-09ARM: dts: ux500: Split TVK DTSI files in twoLinus Walleij
The TVK1281618 was made in R1, R2 and R3 variants. The most commonly used variants are R2 and R3 so split out these to their own files. The R3 version has a totally different display than R1 and R2 and a different set of sensors. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-2-linus.walleij@linaro.org
2019-12-09ARM: dts: ux500: Break out DB8500 DTSILinus Walleij
The DB8500 exists in an enhanced variant named DB8520 for some machines. To clearly distinguish between the different machines, create an explicit db8500.dtsi and move the operating points (only known difference so far) to that file, so we can add an explicit db8520.dtsi after this. Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191126124738.77690-1-linus.walleij@linaro.org Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Drop pulls on I2C busesLinus Walleij
The I2C block in the Ux500 uses internal pull-ups on the SoC, in fact it has to: in HS mode, the I2C block will need to autonomously take control over the pull-up line to do its job. This can be clearly seen from the SoC manual which states that the silicon has a line named "en_cspu_hs" which enables current source pull-up for high speed mode. Another hint is that the vendor code tree never enabled the pull up on these lines, despite being deployed on boards that lack external pull-up resistors. Tested on the Ux500 reference designs without any problems. Cc: Stephan Gerhold <stephan@gerhold.net> Reported-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191126123116.56244-1-linus.walleij@linaro.org Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Use "arm,pl031" compatible for PL031Stephan Gerhold
The Ux500 device tree uses "arm,rtc-pl031" as compatible for PL031. All other boards in Linux describe it using "arm,pl031" instead. This works because the compatible is not actually used in Linux: AMBA devices get probed based on "arm,primecell" and their peripheral ID. Nevertheless, some other projects (e.g. U-Boot) rely on the compatible to probe the device with the correct driver. Those will look for "arm,pl031" instead of "arm,rtc-pl031", preventing the RTC from being probed. Change it to "arm,pl031" to match all other boards. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124205110.48031-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add "simple-bus" compatible to soc nodeStephan Gerhold
The "soc" node in the Ux500 device tree does not need any special handling - it is just a simple I/O bus that can be accessed without additional configuration. Therefore we can additionally describe it as compatible with "simple-bus". This can be used by platforms to probe devices under the soc node without special handling for our custom "stericsson,db8500" compatible (e.g. in U-Boot). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124195728.32226-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Remove ux500_ prefix from ux500_serial* labelsStephan Gerhold
ux500_serial{0,1,2} are the only labels with ux500_ prefix in ste-dbx5x0.dtsi, the other labels (gpio0, msp, ...) do not use any prefix. Remove it for consistency. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-4-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Move serial aliases to ste-dbx5x0.dtsiStephan Gerhold
Now that we have aliases for I2C and SPI in ste-dbx5x0.dtsi, it does not make much sense to keep only the aliases for UART separately in each board device tree. Considering that all boards set the same aliases for the serial ports there is no reason to keep them separated either. Move them to ste-dbx5x0.dtsi and remove the aliases from the board-specific device tree parts. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-3-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add aliases for I2C and SPI busesStephan Gerhold
Now that we disable the I2C/SPI buses by default, is is even more important to assign aliases to the I2C/SPI device nodes. Otherwise, enabling/disabling one of them will potentially change all device IDs, e.g. i2c2 will be named i2c-0 if it is the only enabled I2C bus. Add aliases for the I2C and SPI buses to avoid this. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-2-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Disable I2C/SPI buses by defaultStephan Gerhold
At the moment, all 5 I2C and 6 SPI buses are probed and exposed to user-space by default - even if they are not muxed to any pins on the board. This means that user-space sees an I2C/SPI bus that cannot be actually used properly. In some cases this was used to put the corresponding pins into a low power sleep mode - but even then the pins first need to be configured by the board-specific device tree part. Avoid exposing unconfigured devices to user-space by disabling the I2C/SPI buses by default. Enable them in the board device trees when needed. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: nomadik-pinctrl: Add &gpio_in_nopullStephan Gerhold
ste-nomadik-pinctrl.dtsi already defines in_nopull and gpio_in_pu/pd, but there is no node to configure a pin as GPIO without pull up/down. Add a new &gpio_in_nopull node for this. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125122256.53482-5-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add pin configs for UART1 CTS/RTS pinsStephan Gerhold
UART1 can optionally be used with additional CTS/RTS pins. The pinctrl driver has an extra "u1ctsrts_a_1" pin group for them. Add a new pin configuration to configure them correctly if needed. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125122256.53482-4-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add alternative SDI pin configsStephan Gerhold
SDI0/SDI1 can be used in configurations where some of the pins (e.g. direction control) are not used. The pinctrl driver has separate pin groups for them. Add new pin configurations for: - mc0_a_2: like mc0_a_1, but without CMDDIR/DAT0DIR/DAT2DIR - mc1_a_2: like mc1_a_1, but without FBCLK Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125122256.53482-3-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Rename generic pin configs according to pin groupStephan Gerhold
Some components (e.g. SDI, I2C) can be used with different pin assignments. Before we can add the alternative configurations, we need to rename the current configurations to more generic names. Each pin configuration usually configures one specific pin group. Therefore we rename the configurations to use the pin group as name. Make up for the slightly longer names by removing the "_mode" suffix. Rename all existing uses to use the new labels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125122256.53482-2-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Move generic pin configs out of ste-href-family-pinctrl.dtsiStephan Gerhold
All existing Ux500 boards make use of ste-href-family-pinctrl.dtsi, which contains shared pin configurations for UART, I2C and SDI. Most of these can be also used for devices not based on HREF. Move the generic pin configs into a new device tree include "ste-dbx5x0-pinctrl.dtsi". There is no functional change (yet), as a next step we will rename the pin configs to use more generic names. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125122256.53482-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: snowball: Remove unused PRCMU cpufreq nodeStephan Gerhold
Commit a435adbec264 ("ARM: dts: augment Ux500 to use DT cpufreq") switched the Ux500 device tree to use the generic DT cpufreq driver and removed the PRCMU cpufreq node. The snowball DTS still references it, without effect, since cpufreq is now enabled by default. Remove the unused node. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191117222732.283673-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: declare GPADC IIO ADC channelsLinus Walleij
This adds the IIO channels for the GPADC after converting it to using the standard IIO ADC bindings and moving the driver over to the IIO subsystem. We also add IIO hwmon standard driver node to support reading channels in a standard manner. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: stm32: remove syscfg clock on stm32mp15 ethernetChristophe Roullier
Syscfg is now activated automatically when syscfg registers are used. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: vexpress: Set-up shared OPP table instead of individual for each CPUSudeep Holla
Currently we add individual copy of same OPP table for each CPU within the cluster. This is redundant and doesn't reflect the reality. We can't use core cpumask to set policy->cpus in ve_spc_cpufreq_init() anymore as it gets called via cpuhp_cpufreq_online()->cpufreq_online() ->cpufreq_driver->init() and the cpumask gets updated upon CPU hotplug operations. It also may cause issues when the vexpress_spc_cpufreq driver is built as a module. Since ve_spc_clk_init is built-in device initcall, we should be able to use the same topology_core_cpumask to set the opp sharing cpumask via dev_pm_opp_set_sharing_cpus and use the same later in the driver via dev_pm_opp_get_sharing_cpus. Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-12-09ARM: dts: stm32: remove "@" and "_" from stm32f7 pinmux groupsBenjamin Gaignard
Replace all "@" and "_" by "-" in pinmux groups for stm32f7 family. This avoid errors when using yaml to check the bindings. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: remove "@" and "_" from stm32f4 pinmux groupsBenjamin Gaignard
Replace all "@" and "_" by "-" in pinmux groups for stm32f4 family. This avoid errors when using yaml to check the bindings. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: iwg20d-q7-common: Add LCD supportFabrizio Castro
The iwg20d comes with a 7" capacitive touch screen, therefore add support for it. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/1573660292-10629-11-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-09ARM: dts: stm32: Adapt STM32MP157C ED1 board to STM32 DT diversityAlexandre Torgue
This commit adds security (cryp1) IP to stm32mp157c ED1 board by including stm32mp15xc.dtsi file. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Adapt STM32MP157 DK boards to stm32 DT diversityAlexandre Torgue
To handle STM32MP15 SOCs diversity, some updates have to been done. This commit mainly adapt dk1 board to include the correct package and the correct SOC version. A new file has been created to factorize common parts. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Manage security diversity for STM32M15x SOCsAlexandre Torgue
This commit creates a new file to manage security diversity on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot. -Y = C means cryp IP + secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Introduce new STM32MP15 SOCs: STM32MP151 and STM32MP153Alexandre Torgue
STM32MP151 and STM32MP153 were not explicitly supported through stm32mp157c.dts. This commit adds dedicated files to support all STM32MP15 SOCs family. The differences between those SOCs are: -STM32MP151 [1]: common file. -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU. -STM32MP157 [3]: STM32MP153 + DSI + GPU. [1] https://www.st.com/resource/en/reference_manual/dm00366349.pdf [2] https://www.st.com/resource/en/reference_manual/dm00366355.pdf [3] https://www.st.com/resource/en/reference_manual/dm00327659.pdf Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Update stm32mp157 pinctrl filesAlexandre Torgue
In order to cover the STM32MP15 SOCs family this commit updates pinctrl file names (group definition and packages files). This family includes: STM32MP151, STM32MP153 and STM32MP157. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Adapt stm32mp157 pinctrl to manage STM32MP15xx SOCs familyAlexandre Torgue
This commit modifies stm32mp157 pinctrl files to better manage STM32MP15xx SOCs diversity. Pin controller and gpio controller are moved to common SOC dtsi file. Only pin groups remain in the main pinctrl dtsi file. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: remove unused rng interrupt on stm32f429Benjamin Gaignard
Interrupt has never be used in rng driver so remove it from DT. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add ADC support to stm32mp157c-ed1Fabrice Gasnier
Add ADC support to stm32mp157c-ed1 board. Following ADC signals are dedicated for analog and routed to connectors: - ADC1/2 in0 (ANA0) - ADC1/2 in1 (ANA1) - ADC1 in6 (PF12) Configure ADC1 with these signals. But keep it disabled by default, so PF12 can be used as gpio by default. Add VDD and VDDA supplies to ADC on stm32mp157c-ed1 board. This allows to get full ADC analog performances in case VDDA is below 2.7V (not the case by default). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add ADC pins used for stm32mp157c-ed1Fabrice Gasnier
Define adc1_in6 pin used on stm32mp157c eval board. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add sdmmc3 node for STM32MP1 boardsYann Gautier
On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral can be used through the GPIO extension connector. The sdmmc3 node is then added in the boards DT files, and the required pins are also added. The node status is disabled as there is no device connected by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-12-09ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 boardYann Gautier
On STM32MP157C-ED1, the eMMC is connected on instance 2 of SDMMC peripheral. The sdmmc2 node is then added in the board DT file, as well as the pins nodes in the pinctrl file. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoCYann Gautier
The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral. The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157Yann Gautier
Relax sdmmc1 pins slew-rate to minimize peak currents. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add timers counter support on stm32mp157cFabrice Gasnier
Add counter support on stm32mp157c that provides quadrature encoder on timers 1, 2, 3, 4, 5 and 8. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add support for PWM on stm32mp157a-dk1Fabrice Gasnier
Add PWM support on stm32mp157a-dk1 board. There are several timers channels made available on GPIO expansion and arduino connectors: - Add PWM and trigger support (these timers can also be used as trigger for ADC). It's easier then to configure them all. But keep them disabled by default, so the pins are kept in their initial state to lower power consumption. This way they can also be used as GPIO. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add pwm sleep pins to stm32mp157c-ev1Fabrice Gasnier
Add pinctrl sleep state for PWM on stm32mp157c-ev1 board. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add pwm pin muxing for stm32mp157a-dk1Fabrice Gasnier
Add all PWM pinctrl definitions that can be used on stm32mp157a-dk1 board. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: add pwm sleep pin muxing for stm32mp157c-ev1Fabrice Gasnier
Add PWM pinctrl definitions used in low-power (sleep) mode on stm32mp157c-ev1. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: e60k02: fix power buttonAndreas Kemnade
The power button was only producing irqs, but no key events, Forced power down with long key press works, so probably only a short spike arrives at the SoC. Further investigation shows that LDORTC2 is off after boot of the vendor kernel. LDORTC2 is shared with a GPIO at the pmic which probably transfers the button press to the SoC. That regulator off at boot, so "regulator-boot-on" is definitively wrong. So remove that. Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Fixes: c100ea86e6ab ("ARM: dts: add Netronix E60K02 board common file") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYsVladimir Oltean
On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 have interrupt lines connected to the shared IRQ2_B LS1021A pin. Switching to interrupts offloads the PHY library from the task of polling the MDIO status and AN registers (1, 4, 5) every second. Unfortunately, the BCM5464R quad PHY connected to the switch does not appear to have an interrupt line routed to the SoC. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09ARM: dts: ls1021a: add node describing external interrupt linesRasmus Villemoes
This adds a node describing the six external interrupt lines IRQ0-IRQ5 with configurable polarity. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09ARM: dts: imx25: describe maximum speed of internal usbhost port1 phyMichael Grzeschik
The internal usbphy of usbhost port1 is only full-speed capable. We set this limitation in the dtsi. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-09ARM: dts: imx25: consolidate properties of usbhost1 in dtsi fileMichael Grzeschik
The usb port represented by &usbhost1 uses an USB phy internal to the SoC. We add the phy_type to the base dtsi so the board dts only have to overwrite it if they use a different configuration. While at it we also pin the usbhost port to host mode. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-16 18:56:43 +0000