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Panfrost driver provides a devfreq driver for the Mali GPU and allows to
scale GPU core frequency. Enable support for devfreq thermal integration
to enable cooling of GPU thermal zone by reducing GPU core frequency.
This fixes following warning during boot on Exynos5422-based Odroid XU4:
panfrost 11800000.gpu: [drm:panfrost_devfreq_init] Failed to register cooling device
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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NFS is widely used in debugging and Continuous Integration systems, so
enable the newest versions of protocol: v4.1 and v4.2.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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NFS is widely used in debugging and Continuous Integration systems, so
enable the newest versions of protocol: v4.1 and v4.2.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The Denali NAND controller IP has separate reset control for the
controller core and registers.
Add the reset-names, and one more phandle accordingly. This is the
approved DT-binding.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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The function name suggests that this is a boolean checking whether the
architecture asks for an update of the VDSO data, but it works the other
way round. To spare further confusion invert the logic.
Fixes: 44f57d788e7d ("timekeeping: Provide a generic update_vsyscall() implementation")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20200114185946.656652824@linutronix.de
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson:
"I've been sitting on these longer than I meant, so the patch count is
a bit higher than ideal for this part of the release. There's also
some reverts of double-applied patches that brings the diffstat up a
bit.
With that said, the biggest changes are:
- Revert of duplicate i2c device addition on two Aspeed (BMC)
Devicetrees.
- Move of two device nodes that got applied to the wrong part of the
tree on ASpeed G6.
- Regulator fix for Beaglebone X15 (adding 12/5V supplies)
- Use interrupts for keys on Amlogic SM1 to avoid missed polls
In addition to that, there is a collection of smaller DT fixes:
- Power supply assignment fixes for i.MX6
- Fix of interrupt line for magnetometer on i.MX8 Librem5 devkit
- Build fixlets (selects) for davinci/omap2+
- More interrupt number fixes for Stratix10, Amlogic SM1, etc.
- ... and more similar fixes across different platforms
And some non-DT stuff:
- optee fix to register multiple shared pages properly
- Clock calculation fixes for MMP3
- Clock fixes for OMAP as well"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits)
MAINTAINERS: Add myself as the co-maintainer for Actions Semi platforms
ARM: dts: imx7: Fix Toradex Colibri iMX7S 256MB NAND flash support
ARM: dts: imx6sll-evk: Remove incorrect power supply assignment
ARM: dts: imx6sl-evk: Remove incorrect power supply assignment
ARM: dts: imx6sx-sdb: Remove incorrect power supply assignment
ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment
ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL
ARM: omap2plus: select RESET_CONTROLLER
ARM: davinci: select CONFIG_RESET_CONTROLLER
ARM: dts: aspeed: rainier: Fix fan fault and presence
ARM: dts: aspeed: rainier: Remove duplicate i2c busses
ARM: dts: aspeed: tacoma: Remove duplicate flash nodes
ARM: dts: aspeed: tacoma: Remove duplicate i2c busses
ARM: dts: aspeed: tacoma: Fix fsi master node
ARM: dts: aspeed-g6: Fix FSI master location
ARM: dts: mmp3: Fix the TWSI ranges
clk: mmp2: Fix the order of timer mux parents
ARM: mmp: do not divide the clock rate
arm64: dts: rockchip: Fix IR on Beelink A1
optee: Fix multi page dynamic shm pool alloc
...
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
More dts changes for omaps for v5.6 merge window
Add basic support for first generation Amazon omap3-echo. This got
applied rather late as we discussed how to deal with SoC variants
with some accelerators unaccessible, and eventually ended up setting
up few more SoC specific dtsi files. Eventually we'll need to also
detect the disabled accelerators on driver init, but more patching
is needed for that.
* tag 'omap-for-v5.6/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Add omap3-echo
ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725
Link: https://lore.kernel.org/r/pull-1579200367-372444@atomide.com-4
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc
SMC related changes for omaps for v5.6 merge window
A series of changes to use optee SMC calls if optee is initialized by
the bootloader. Based on the discussions on LAKML in mailing list thread
"arm_smccc_smc as generic smc interface?" we don't want to add more quirk
handling to arm_smccc_smc() and want to handle it locally instead.
* tag 'omap-for-v5.6/soc-smc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available
ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init()
ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization
Link: https://lore.kernel.org/r/pull-1579200367-372444@atomide.com-2
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.6
- add DDR clock controller
- GPU OPP updates
* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPP
ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPP
ARM: dts: meson8b: fix the clock controller compatible string
ARM: dts: meson8b: add the DDR clock controller
ARM: dts: meson8: add the DDR clock controller
ARM: dts: meson: provide the XTAL clock using a fixed-clock
dt-bindings: clock: meson8b: add the clock inputs
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
Link: https://lore.kernel.org/r/7hwo9udi7m.fsf@baylibre.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM dts updates for v5.6
* Add SAW L2 nodes to boot secondary cpus on IPQ40xx
* Fix remaining IRQ_TYPE_NONE on APQ8084
* Update tsens node to new style
* Add modem remoteproc node to MSM8974
* Move ADSP SMD edge into ADSP remoteproc node for MSM8974
* Add and enable wireless communication subsystem on MSM8974 and Fairphone 2
* Add MSM8974 interconnect provider nodes
* Add MSM8974 OCMEM node
* tag 'qcom-dts-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx
ARM: dts: qcom: apq8084: Remove all instances of IRQ_TYPE_NONE
ARM: dts: qcom: apq8084: Change tsens definition to new style
ARM: dts: msm8974: Move ADSP smd edge to ADSP PIL
ARM: dts: msm8974: Add modem remoteproc node
ARM: dts: msm8974-FP2: Introduce the wcnss remoteproc node
ARM: dts: msm8974: Introduce the wcnss remoteproc node
ARM: dts: qcom: msm8974: add interconnect nodes
ARM: dts: qcom: msm8974: add ocmem node
Link: https://lore.kernel.org/r/20200113204448.GE3325@yoga
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/defconfig
Qualcomm ARM defconfig updates for v5.6
* Enable anx78xx HDMI bridge driver
* Enable MSM8974 interconnect provider driver
* tag 'qcom-defconfig-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: qcom_defconfig: add anx78xx HDMI bridge support
ARM: qcom_defconfig: add msm8974 interconnect support
Link: https://lore.kernel.org/r/20200113204313.GC3325@yoga
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc
AT91 SoC for 5.5
- Document new SoC: sam9x60
- rework sam9x60 Kconfig option
* tag 'at91-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: Documentation: add sam9x60 product and datasheet
ARM: at91: pm: use of_device_id array to find the proper shdwc node
ARM: at91: pm: use SAM9X60 PMC's compatible
ARM: debug-ll: select DEBUG_AT91_RM9200_DBGU for sam9x60
drivers: soc: atmel: select POWER_RESET_AT91_SAMA5D2_SHDWC for sam9x60
power: reset: Kconfig: select POWER_RESET_AT91_RESET for sam9x60
drivers: soc: atmel: move sam9x60 under its own config flag
ARM: at91: pm: move SAM9X60's PM under its own SoC config flag
ARM: at91: Kconfig: add config flag for SAM9X60 SoC
ARM: at91: Kconfig: add sam9x60 pll config flag
Link: https://lore.kernel.org/r/20200113161612.GA1358903@piout.net
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/defconfig
AT91 defconfig for 5.6
- Add sam9x60 to at91_dt_defconfig
* tag 'at91-5.6-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: configs: at91: enable config flags for sam9x60 SoC
ARM: configs: at91: use savedefconfig
Link: https://lore.kernel.org/r/20200113161033.GA1358651@piout.net
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for 5.6
- Fix sama5d3 peripheral clock rate range
- New boards: Overkiz Smartikz and Kizbox Mini, Microchip SAMA5D27
wlsom1-ek
- sama5d2 sdmcc fixes
* tag 'at91-5.6-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama5d3: define clock rate range for tcb1
ARM: dts: at91: sama5d3: fix maximum peripheral clock rates
ARM: dts: at91: nattis 2: remove unnecessary include
ARM: dts: at91: add smartkiz support and a common kizboxmini dtsi file
dt-bindings: arm: at91: Document Kizboxmini and Smartkiz boards binding
ARM: dts: at91: rearrange kizbox dts using aliases nodes
ARM: dts: at91: sama5d27_som1_ek: add the microchip,sdcal-inverted on sdmmc0
ARM: dts: at91: Reenable UART TX pull-ups
ARM: dts: at91: sama5d2: set the sdmmc gclk frequency
ARM: dts: at91: sama5d27_som1_ek: add i2c filters properties
ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ek
dt-bindings: ARM: at91: Document SAMA5D27 WLSOM1 and Evaluation Kit
ARM: dts: at91: sama5d2: mark secumod as a GPIO controller
ARM: dts: at91: sama5d2: disable pwm0 by default
Link: https://lore.kernel.org/r/20200113155423.GA1357189@piout.net
Signed-off-by: Olof Johansson <olof@lixom.net>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
This is our usual set of DT patches for the Allwinner SoCs.
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
* tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (52 commits)
arm64: dts: allwinner: a64: enable DVFS
arm64: dts: allwinner: a64: add dtsi with CPU operating points
arm64: dts: allwinner: a64: add cooling maps and thermal tripping points
arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodes
arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocks
ARM: dts: sunxi: Use macros for references to CCU clocks
arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 board
ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes
arm64: dts: allwinner: a64: pinebook: Fix lid wakeup
ARM: dts: sun8i: r40: Add device node for CSI0
ARM: dts: sun7i: Add CSI1 controller and pinmux options
ARM: dts: sun4i: Add CSI1 controller and pinmux options
ARM: dts: sunxi: Add missing LVDS resets and clocks
ARM: dts: sun8i: r40: Use tcon top clock index macros
ARM: dts: sun8i: R40: Add PMU node
ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K
arm64: dts: allwinner: h6: Add thermal sensor and thermal zones
ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 board
arm64: dts: allwinner: a64: Add MIPI DSI pipeline
arm64: dts: allwinner: a64: Add thermal sensors and thermal zones
...
Link: https://lore.kernel.org/r/20200113095555.GA29848@wens.csie.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig update for 5.6:
- Enable i.MX8MP clock driver in arm64 defconfig.
- Enable Crypto CAAM driver support as module in arm64 defconfig.
- Enable ILI210X touch driver, USB CDC ACM function, NFS_V4 support and
TFP410 DVI bridge driver support in arm32 imx_v6_v7_defconfig.
* tag 'imx-defconfig-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: Enable CONFIG_CLK_IMX8MP by default
arm64: defconfig: Enable CRYPTO_DEV_FSL_CAAM
ARM: imx_v6_v7_defconfig: Select the TFP410 driver
ARM: imx_v6_v7_defconfig: Enable NFS_V4_1 and NFS_V4_2 support
ARM: configs: imx_v6_v7_defconfig: enable USB ACM
ARM: imx_v6_v7_defconfig: Enable TOUCHSCREEN_ILI210X
Link: https://lore.kernel.org/r/20200113034006.17430-6-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree update for 5.6:
- New board support: i.MX6SL based Tolino Shine 3 eBook reader,
i.MX7ULP Embedded Artists COM Board, i.MX6Q/DL based Gateworks
Ventana Boards.
- A couple of series from Andrey Smirnov to enhance i.MX6 RDU2 and
VF610 ZII boards.
- Add revision in board compatible string for imx6sx-sdb-reva and
imx7d-sdb-reva board.
- A fixup on imx6sl-tolino-shine3 board to remove incorrect power
supply assignment.
- Set initial buck regulator modes explicitly for phycore-imx6 board,
so that a wrong initial mode set by bootloader does not interfere.
- Add Add LCD support for imx7d-pico board.
- A couple of patches from Michael Grzeschik to enhance USB Host
support on i.MX25.
- A couple of patches from Michael Trimarchi to remove duplicate
Ethernet PHY reset properties on imx6qdl-icore and switch to
phy-handle.
- A couple of changes to add extirq node support on LS1021A SoC and
make use of it on the LS1021A-TSN board.
- A few random device additions and improvements on various boards.
* tag 'imx-dt-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
ARM: dts: imx: Add GW5912 board support
ARM: dts: imx: Add GW5913 board support
ARM: dts: imx: Add GW5910 board support
ARM: dts: imx: Add GW5907 board support
ARM: dts: imx6ul-14x14-evk: Pass the "broken-cd" property
ARM: dts: imx6sl-tolino-shine3: Remove incorrect power supply assignment
ARM: dts: imx7d-pico: Add LCD support
ARM: dts: imx6qdl-icore: Add fec phy-handle
ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods
ARM: dts: imx7: Unify temp-grade and speed-grade nodes
ARM: dts: imx6: phycore-som: add pmic onkey device
ARM: dts: imx51-babbage: Fix the DVI output description
ARM: dts: imx6qdl-apalis: mux HDMI CEC pin
ARM: dts: imx6sll: add PXP module
ARM: dts: colibri-imx6ull: correct wrong pinmuxing and add comments
ARM: dts: vf610-zii-scu4-aib: Add node for switch watchdog
ARM: dts: vf610-zii-scu4-aib: Use generic names for DT nodes
ARM: dts: vf610-zii-dev-rev-b: Drop redundant I2C properties
ARM: dts: phycore-imx6: set buck regulator modes explicitly
ARM: dts: imx6: rdu2: Limit USBH1 to Full Speed
...
Link: https://lore.kernel.org/r/20200113034006.17430-4-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc
i.MX SoC changes for 5.6:
- Add support for reading serial number from OCOTP on i.MX7ULP.
- A patch from Anson to enable ARM_ERRATA_814220 for i.MX6UL & i.MX7D,
and a fixup patch from Arnd to select the option only for ARMv7-A.
* tag 'imx-soc-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A
ARM: imx: Enable ARM_ERRATA_814220 for i.MX6UL and i.MX7D
ARM: imx: Add i.MX7ULP SoC serial number support
ARM: imx: Fix boot crash if ocotp is not found
ARM: imx_v6_v7_defconfig: Explicitly restore CONFIG_DEBUG_FS
ARM: dts: imx6ul-evk: Fix peripheral regulator
arm64: dts: ls1028a: fix reboot node
arm64: dts: ls1028a: fix typo in TMU calibration data
ARM: imx: Correct ocotp id for serial number support of i.MX6ULL/ULZ SoCs
ARM: dts: e60k02: fix power button
ARM: dts: imx6ul: imx6ul-14x14-evk.dtsi: Fix SPI NOR probing
Link: https://lore.kernel.org/r/20200113034006.17430-2-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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mvebu dt for 5.6 (part 1)
- Add support for SolidRun Clearfog GTR (Armada 385 based board)
- Move i2c0 to the SoliRrun Microsom dtsi (Armada 38x based)
- Add EEPROM node on SoliRrun Microsom (rev 2.1)
- Add EEPROM node on SoliRrun ClearFog Pro
* tag 'mvebu-dt-5.6-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-388-clearfog: add eeprom
ARM: dts: armada-38x-solidrun-microsom: add eeprom
ARM: armada-38x-solidrun-microsom: move i2c0 to SOM DT
ARM: dts: mvebu: add support for SolidRun Clearfog GTR
Link: https://lore.kernel.org/r/874kx13nvh.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.6-rc1
This adds memory timings for the PAZ100 and does some minor cleanup for
the external memory controller device tree node on Tegra124.
* tag 'tegra-for-5.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra20: paz00: Add memory timings
ARM: tegra: Rename EMC on Tegra124
ARM: tegra: Let the EMC hardware use the EMC clock
Link: https://lore.kernel.org/r/20200111003553.2411874-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc
ARM: tegra: Core changes for v5.6-rc1
Contains a couple of fixes for RAM repair on Tegra124.
* tag 'tegra-for-5.6-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
ARM: tegra: Modify reshift divider during LP1
ARM: tegra: Enable PLLP bypass during Tegra124 LP1
Link: https://lore.kernel.org/r/20200111003553.2411874-5-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add device tree files for SAM9X60 SoC and SAM9X60-EK board.
Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/1579085987-13976-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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This appears to be some kind of copy and paste error, and is actually
dead code.
Pre: f = 0 ⇒ (f >> 32) = 0
f = (f >> 32) + le32_to_cpu(digest[0]);
Post: 0 ≤ f < 2³²
put_unaligned_le32(f, dst);
Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0
f = (f >> 32) + le32_to_cpu(digest[1]);
Post: 0 ≤ f < 2³²
put_unaligned_le32(f, dst + 4);
Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0
f = (f >> 32) + le32_to_cpu(digest[2]);
Post: 0 ≤ f < 2³²
put_unaligned_le32(f, dst + 8);
Pre: 0 ≤ f < 2³² ⇒ (f >> 32) = 0
f = (f >> 32) + le32_to_cpu(digest[3]);
Post: 0 ≤ f < 2³²
put_unaligned_le32(f, dst + 12);
Therefore this sequence is redundant. And Andy's code appears to handle
misalignment acceptably.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Merge crypto tree to pick up hisilicon patch.
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This enables bcm2711's PCIe bus, which is hardwired to a VIA
Technologies XHCI USB 3.0 controller.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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With the introduction of the Raspberry Pi 4 we were forced to explicitly
configure CMA's location, since arm64 defaults it into the ZONE_DMA32
memory area, which is not good enough to perform DMA operations on that
device. To bypass this limitation a dedicated CMA DT node was created,
explicitly indicating the acceptable memory range and size.
That said, compatibility between boards is a must on the Raspberry Pi
ecosystem so this creates a common CMA DT node so as for DT overlays to
be able to update CMA's properties regardless of the board being used.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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The DaVinci MUSB glue contains an optional GPIO line to
control VBUS power, convert this to use a GPIO descriptor
and augment the EVM board file to provide this descriptor.
I can't get this driver to compile properly and it depends
on broken but when I didn get it to compile brokenly, it
did at least not complain about THIS code being broken so
I don't think I broke the driver any more than what it
already is.
I did away with the ifdefs that do not work with
multiplatform anyway so the day someone decides to
resurrect the code, the path to get it working should be
easier as well since DaVinci is now multiplatform.
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[b-liu@ti.com: fixed one instance still ref to global variable vbus_state]
Signed-off-by: Bin Liu <b-liu@ti.com>
Link: https://lore.kernel.org/r/20200115132547.364-25-b-liu@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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con_init in tty/vt.c will now set conswitchp to dummy_con if it's unset.
Drop it from arch setup code.
Signed-off-by: Arvind Sankar <nivedita@alum.mit.edu>
Link: https://lore.kernel.org/r/20191218214506.49252-6-nivedita@alum.mit.edu
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Setting BUILD_VDSO32 is required to expose the legacy 32bit interfaces in
the generic VDSO code which are going to be hidden behind an #ifdef
BUILD_VDSO32.
The 32bit fallbacks are necessary to remove the existing
VDSO_HAS_32BIT_FALLBACK hackery.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/87tv4zq9dc.fsf@nanos.tec.linutronix.de
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This wires up the pidfd_getfd syscall for all architectures.
Signed-off-by: Sargun Dhillon <sargun@sargun.me>
Acked-by: Christian Brauner <christian.brauner@ubuntu.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200107175927.4558-4-sargun@sargun.me
Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com>
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This is the first generation Amazon Echo from 2016.
Audio support is not yet implemented.
Signed-off-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DM3730 is considered as omap36xx.dtsi, while the rest has:
DM3730 | DM3725 | AM3715 | AM3703
IVA X | X | |
SGX X | | X |
Where X is "supported"
Signed-off-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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During suspend CPU context may be lost in both non-secure and secure CPU
states. The kernel can handle saving and restoring the non-secure context
but must call into the secure side to allow it to save any context it may
lose. Add these calls here.
Note that on systems with OP-TEE available the suspend call is issued to
OP-TEE using the ARM SMCCC, but the resume call is always issued to the
ROM. This is because on waking from suspend the ROM is restored as the
secure monitor. It is this resume call that instructs the ROM to restore
OP-TEE, all subsequent calls will be handled by OP-TEE and should use the
ARM SMCCC.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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On High-Security(HS) OMAP2+ class devices a couple actions must be
performed from the ARM TrustZone during boot. These traditionally can be
performed by calling into the secure ROM code resident in this secure
world using legacy SMC calls. Optionally OP-TEE can replace this secure
world functionality by replacing the ROM after boot. ARM recommends a
standard calling convention is used for this interaction (SMC Calling
Convention). We check for the presence of OP-TEE and use this type of
call to perform the needed actions, falling back to the legacy OMAP ROM
call if OP-TEE is not available.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This check and associated flag can be used to signal the presence
of OP-TEE on the platform. This can be used to determine which
SMC calls to make to perform secure operations.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This can be used for detecting secure features or making early device
init sequence changes based on device security type.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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BeagleBone Black series is equipped with 512MB RAM
whereas only 256MB is included from am335x-bone-common.dtsi
This leads to an issue with unusual setups when devicetree
is loaded by GRUB2 directly.
Signed-off-by: Matwey V. Kornilov <matwey@sai.msu.ru>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The codec driver needs correct regulators in order to probe.
Both VCC_3.3V and VCC_1.8V is always on fixed regulators on the board.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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The codec driver needs correct regulators in order to probe.
Both VCC_3V3 and VCC_1V8 is always on fixed regulators on the board.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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We need the USB fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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An experimental test with the command below gives this error:
rk3188-bqedison2qc.dt.yaml: dwmmc@10218000: wifi@1:
'reg' is a required property
So fix this by adding a reg property to the brcmf sub node.
Also add #address-cells and #size-cells to prevent more warnings.
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200110134420.11280-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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All platforms have now been switched to the new clocksource driver.
Remove the old code and various no longer needed bits and pieces.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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We now have a proper clocksource driver for davinci. Switch the dm365
platform to using it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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In order to probe this ethernet interface from the device tree
all physical MMIO regions must be passed as resources. Begin
this rewrite by first passing the port base address as a
resource for all platforms using this driver, remap it in
the driver and avoid using any reference of the statically
mapped virtual address in the driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The platform data is needed to compile the driver as standalone,
so move it to a global location along with similar files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The ixp46x ptp driver has a somewhat unusual setup, where the ptp
driver and the ethernet driver are in different directories but
access the same registers that are defined a platform specific
header file.
Moving everything into drivers/net/ makes it look more like most
other ptp drivers and allows compile-testing this driver on
other targets.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The ixp4xx_hss driver needs the platform data definition and the
system clock rate to be compiled. Move both into a new platform_data
header file.
This is a prerequisite for compile testing, but turning on compile
testing requires further patches to isolate the SoC headers.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The Gateworks GW5912 is an IMX6 SoC based single board computer with:
- IMX6Q or IMX6DL
- 32bit DDR3 DRAM
- GbE RJ45 front-panel
- 4x miniPCIe socket with PCI Gen2, USB2
- 1x miniPCIe socket with PCI Gen2, USB2, mSATA
- 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
- 10V to 60V DC input barrel jack
- 3axis accelerometer (lis2de12)
- GPS (ublox ZOE-M8Q)
- bi-color front-panel LED
- 256MB NAND boot device
- nanoSIM/microSD socket (with UHS-I support)
- user pushbutton
- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
- CAN Bus transceiver (mcp2562)
- RS232 transceiver (1x UART with flow-control or 2x UART (build option)
- off-board SPI connector (1x chip-select)
Signed-off-by: Robert Jones <rjones@gateworks.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The Gateworks GW5913 is an IMX6 SoC based single board computer with:
- IMX6Q or IMX6DL
- 32bit DDR3 DRAM
- FEC GbE RJ45 front-panel
- 1x miniPCIe socket with PCI Gen2, USB2
- 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
- 6V to 60V DC input connector
- GPS (ublox ZOE-M8Q)
- bi-color front-panel LED
- 256MB NAND boot device
- nanoSIM socket
- user pushbutton
- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
Signed-off-by: Robert Jones <rjones@gateworks.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The Gateworks GW5910 is an IMX6 SoC based single board computer with:
- IMX6Q or IMX6DL
- 32bit DDR3 DRAM
- FEC GbE RJ45 front-panel
- 1x miniPCIe socket with PCI Gen2, USB2
- 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
- 5V to 60V DC input barrel jack
- 3axis accelerometer (lis2de12)
- GPS (ublox ZOE-M8Q)
- bi-color front-panel LED
- 256MB NAND boot device
- microSD socket (with UHS-I support)
- user pushbutton
- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
- Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
- WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
- RS232 transceiver (1x UART with flow-control or 2x UART (build option)
- off-board SPI connector (1x chip-select)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Robert Jones <rjones@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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