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2020-03-13ARM: tegra: Add clock-cells property to PMCSowjanya Komatineni
Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock. These clocks were erroneously provided by the clock and reset controller and are now provided by the PMC instead because that's where the primary controls are. This patch adds #clock-cells property with 1 clock specifier to the Tegra PMC node in device tree. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: Remove USB 2-0 port from Jetson TK1 padctlNagarjuna Kristam
On Jetson TK1 USB 2-0 port is controlled by phy-tegra-usb driver rather than padctl driver. Remove the entry for the same. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: cpuidle: Remove unnecessary memory barrierDmitry Osipenko
There is no good justification for smp_rmb() after returning from LP2 because there are no memory operations that require SMP synchronization. Thus remove the confusing barrier. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: cpuidle: Make abort_flag atomicDmitry Osipenko
Replace memory accessors with atomic API just to make code consistent with the abort_barrier. The new variant may be even more correct now since atomic_read() will prevent compiler from generating wrong things like carrying abort_flag value in a register instead of re-fetching it from memory. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2Dmitry Osipenko
It is possible that something may go wrong with the secondary CPU, in that case it is much nicer to get a dump of the flow-controller state before hanging machine. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: Make outer_disable() open-codedDmitry Osipenko
The outer_disable() of Tegra's suspend code is open-coded now since that helper produces spurious warning message about secondary CPUs being online when CPU enters into LP2 from cpuidle. The secondaries are actually halted by the cpuidle driver on entering into LP2 idle-state, but the online status is not touched by the cpuidle. This fixes a storm of warnings once LP2 idling state is enabled on Tegra30. The outer_disable() helper has sanity checks for interrupts and secondary CPUs being disabled and we are pretty confident about the interrupts state during of CPU idling / system suspend. The rail-off status check is added in this patch as equivalent for the "num_online_cpus() > 1". Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: Rename some of the newly exposed PM functionsDmitry Osipenko
Rename some of the recently exposed PM functions, prefixing them with "tegra_pm_" in order to make the naming of the PM functions consistent. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: Expose PM functions required for new cpuidle driverDmitry Osipenko
The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/ directory and it will require all these exposed Tegra PM-core functions. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: fixup missing include rename] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: bcm2835-rpi-zero-w: Add missing pinctrl nameNick Hudson
Define the sdhci pinctrl state as "default" so it gets applied correctly and to match all other RPis. Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W") Signed-off-by: Nick Hudson <skrll@netbsd.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-03-12ARM: 8962/1: kexec: drop invalid assembly argumentStefan Agner
The tst menomic has only a single #<const> argument in Thumb mode. There is an ARM variant which allows to write #<const> as #<byte>, #<rot> which probably is where the current syntax comes from. It seems that binutils does not care about the additional parameter. Clang however complains in Thumb2 mode: arch/arm/kernel/relocate_kernel.S:28:12: error: too many operands for instruction tst r3,#1,0 ^ Drop the unnecessary parameter. This fixes building this file in Thumb2 mode with the Clang integrated assembler. Link: https://github.com/ClangBuiltLinux/linux/issues/770 Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-03-12ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfigDmitry Osipenko
The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: multi_v7_defconfig: Enable Tegra cpuidle driverDmitry Osipenko
The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and it is now a proper platform driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: tegra: Propagate error from tegra_idle_lp2_last()Dmitry Osipenko
Technically cpu_suspend() may fail and it's never good to lose information about failure. For example things like cpuidle core could correctly sample idling time in the case of failure. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: tegra: Change tegra_set_cpu_in_lp2() type to voidDmitry Osipenko
The Tegra30 CPUIDLE driver has intention to check whether primary CPU was the last CPU that entered LP2 (CC6) idle-state, but that functionality never got utilized because driver never supported the CC6 state for the case where any secondary CPU is online. The new cpuidle driver will properly support CC6 on Tegra30, including the case where secondary CPUs are online, and that knowledge about what CPUs entered into CC6 won't be needed at all because new driver will use different approach by making use of the coupled idle-state and explicitly parking secondary CPUs before entering into CC6. Thus this patch is just a minor cleanup change. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: tegra: Remove pen-locking from cpuidle-tegra20Dmitry Osipenko
Pen-locking is meant to block CPU0 if CPU1 wakes up during of entering into LP2 because of some interrupt firing up, preventing unnecessary LP2 enter that will be resumed immediately. Apparently this case doesn't happen often in practice, I checked how often it takes place and found that after ~20 hours of browsing web, managing email, watching videos and idling (15+ hours) there is only a dozen of early LP2 entering abortions and they all happened while device was idling. Thus let's remove the pen-locking and make LP2 entering uninterruptible, simplifying code quite a lot. This will also become very handy for the upcoming unified cpuidle driver, allowing to have a common LP2 code-path across of different hardware generations. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: tegra: Add tegra_pm_park_secondary_cpu()Dmitry Osipenko
This function resembles tegra_cpu_die() of the hotplug code, but this variant is more suitable to be used for CPU PM because it's made specifically to be used by cpu_suspend(). In short this function puts secondary CPU offline, it will be used by the new CPUIDLE driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: tegra: Compile sleep-tegra20/30.S unconditionallyDmitry Osipenko
The sleep-tegra*.S provides functionality required for suspend/resume and CPU hotplugging. The new unified CPUIDLE driver will support multiple hardware generations starting from Terga20 and ending with Tegra124, the driver will utilize functions that are provided by the assembly and thus it is cleaner to compile that code without any build-dependencies in order to avoid churning with #ifdef's. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12ARM: dts: sun8i: a83t: Add device node for rotation coreJernej Skrabec
Allwinner A83T contains rotation core. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-12ARM: dts: sunxi: Fix DE2 clocks register rangeJernej Skrabec
As it can be seen from DE2 manual, clock range is 0x10000. Fix it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Fixes: 73f122c82775 ("ARM: dts: sun8i: a83t: Add display pipeline") Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline") Fixes: 21b299209330 ("ARM: sun8i: v3s: add device nodes for DE2 display pipeline") Fixes: d8c6f1f0295c ("ARM: sun8i: h3/h5: add DE2 CCU device node for H3") [wens@csie.org: added fixes tags] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: a33: add the new SS compatibleCorentin Labbe
Add the new A33 SS compatible to the crypto node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Move SPI device nodes based on address orderChen-Yu Tsai
When the SPI device nodes were added, they were added in the wrong location in the device tree file. The device nodes should be sorted by register address. Move the devices node to their correct positions within the file. Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes") Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3Chen-Yu Tsai
When the SPI device nodes were added, SPI2 and SPI3 had incorrect register base addresses. Fix the base address for both of them. Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes") Reported-by: JuanEsf <juanesf91@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: sun8i: r40: Move AHCI device node based on address orderChen-Yu Tsai
When the AHCI device node was added, it was added in the wrong location in the device tree file. The device nodes should be sorted by register address. Move the device node to before EHCI1, where it belongs. Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node") Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-03-11ARM: dts: exynos: Fix polarity of the LCD SPI bus on UniversalC210 boardMarek Szyprowski
Recent changes in the SPI core and the SPI-GPIO driver revealed that the GPIO lines for the LD9040 LCD controller on the UniversalC210 board are defined incorrectly. Fix the polarity for those lines to match the old behavior and hardware requirements to fix LCD panel operation with recent kernels. Cc: <stable@vger.kernel.org> # 5.0.x Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-03-11ARM: dts: add bus to rockchip amba nodenamesJohan Jonker
A test with the command below gives for example this error: arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml: amba: $nodename:0: 'amba' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' AMBA is a open standard for the connection and management of functional blocks in a SoC. It's compatible with 'simple-bus', so fix this error by adding 'bus' to all Rockchip 'amba' nodes. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ schemas/simple-bus.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200302153047.17101-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11ARM: dts: rockchip: remove #dma-cells from dma client nodes for rv1108Johan Jonker
When we combine spi-rockchip.yaml and spi-controller.yaml and add 'additionalProperties: false' it gives for example this error: arch/arm/boot/dts/rv1108-evb.dt.yaml: spi@10270000: '#dma-cells' does not match any of the regexes: '^.*@[0-9a-f]+$', '^slave$' '#dma-cells' are not used for dma clients, so remove them all. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/spi-rockchip.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200309134020.14935-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11ARM: dts: rockchip: fix rockchip,default-sample-phase property namesJohan Jonker
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine rockchip-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives for example this error: arch/arm/boot/dts/rk3036-evb.dt.yaml: mmc@1021c000: 'default-sample-phase' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'default-sample-phase' is not a valid property name for mmc nodes. Fix this error by renaming it to 'rockchip,default-sample-phase'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307134841.13803-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11ARM: dts: rockchip: fix vqmmc-supply property name for rk3188-bqedison2qcJohan Jonker
A test with the command below does not detect all errors in combination with 'additionalProperties: false' and allOf: - $ref: "synopsys-dw-mshc-common.yaml#" allOf: - $ref: "mmc-controller.yaml#" 'additionalProperties' applies to all properties that are not accounted-for by 'properties' or 'patternProperties' in the immediate schema. First when we combine rockchip-dw-mshc.yaml, synopsys-dw-mshc-common.yaml and mmc-controller.yaml it gives this error: arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml: mmc@10218000: 'vmmcq-supply' does not match any of the regexes: '^.*@[0-9]+$', '^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)| uhs-(sdr(12|25|50|104)|ddr50))$', 'pinctrl-[0-9]+' 'vmmcq-supply' is not a valid property name for mmc nodes. Fix this error by renaming it to 'vqmmc-supply'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200307134841.13803-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-11ARM: dts: imx25-pinfunc: add config for kpp rows 4 to 7Martin Kaiser
i.MX25's Keypad Port (KPP) can be used with a key pad matrix of up to 8 x 8 keys. Add pin configurations for rows 4 to 7. The new defines have been tested on an out-of-tree board. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx: align name for crypto node and child nodesHoria Geantă
crypto node should use the "crypto" generic naming, and not a specific one ("sahara", "dcp", "caam"). Child nodes of the crypto node for caam crypto engine should use the "jr" name (without an index), as indicated in the DT binding. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx6: phycore-som: fix arm and soc minimum voltageMarco Felsch
The current set minimum voltage of 730000µV seems to be wrong. I don't know the document which specifies that but the imx6qdl datasheets says that the minimum voltage should be 0.925V for VDD_ARM (LDO bypassed, lowest opp) and 1.15V for VDD_SOC (LDO bypassed, lowest opp). Fixes: ddec5d1c0047 ("ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM") Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx6qdl-gw5910: add CC1352 UARTTim Harvey
The GW5910-C revision adds a TI CC1352 connected to IMX UART4 Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: iwg22d-sodimm: Enable touchscreenMarian-Cristian Rotariu
In one of the iWave-G22D development board variants, called Generic SODIMM Development Platform, we have an LCD with touchscreen. The resistive touch controller, STMPE811 is on the development board and is connected through the i2c5 of the RZ-G1E. Additionally, this controller should generate an interrupt to the CPU and it is connected through GPIO4,4 to the GIC. Touch was tested with one of our iW-RainboW-G22D-SODIMM RZ/G1E development platforms. More details on the iWave website: https://www.iwavesystems.com/rz-g1e-sodimm-development-kit.html Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1583336650-25848-1-git-send-email-marian-cristian.rotariu.rb@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-11ARM: dts: iwg22d-sodimm: Enable LCD panelMarian-Cristian Rotariu
On the Generic SODIMM Development Platform there is an RGB LCD panel directly connected to the DU output. It uses the TPU0 as backlight, one GPIO pull-up configuration for power enable, R[2:7], G[2:7], B[2:7], VSYNC, HSYNC, DU0_DISP and, DU0_CLK as inputs. There is no encoder between the DU and the panel, therefore the default connector driver is used. The two variants of the iW-G22D should be mutually exclusive, therefore this patch also disables the RGB LCD display when the HDMI extension board is used. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1583239490-8837-1-git-send-email-marian-cristian.rotariu.rb@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-11ARM: dts: imx6qdl-sr-som-ti: indicate powering off wifi is safeRussell King
We need to indicate that powering off the TI WiFi is safe, to avoid: wl18xx_driver wl18xx.2.auto: Unbalanced pm_runtime_enable! wl1271_sdio mmc0:0001:2: wl12xx_sdio_power_on: failed to get_sync(-13) which prevents the WiFi being functional. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx6: phycore-som: add da9062 gpio supportMarco Felsch
The pmic is a mfd device and supports gpios. Those gpios are not routed to the SoM baseboard pin header but they are connected to the i.MX6. We need the GPIO's to configure the pmic to select between the suspend/resume arm and soc voltages Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspendMarco Felsch
By default the phycore-som has support for two watchdog devices: 1st the internal imx6 watchdog and 2nd the DA9062 PMIC watchdog. According [1] the PMIC watchdog is used as boot watchdog. It is common to use this watchdog during "system up" time too. Furthermore the PMIC watchdog can be used to address ERR007117 since the phycore-som can be equipped with NAND or eMMC storage. The PMIC watchdog can be enabled/disabled by the PMIC itself if the PMIC enters POWERDOWN mode or by the host. The PMIC powerdown mode can't be used due to the PCB design. So the watchdog is still enabled during a suspend which causes a system reset. We need to tell the driver to disable the watchdog during a system suspend and to reenable it upon a resume to fix this. [1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi#n73 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx: Make iomuxc node name genericAnson Huang
Node name should be generic, use "pinctrl" instead of "iomuxc" for all i.MX6/7 SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: imx: Drop unnecessary src_base checkAnson Huang
src_base is already checked during src driver initialization, no need to check its availability again when using it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: imx: Remove unnecessary blank linesAnson Huang
Remove unnecessary blank lines for cleanup. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11ARM: dts: imx7s: add snvs clock to pwrkeyAndré Draszik
On i.MX7, the SNVS requires a clock. This is similar to the clock bound to the SNVS RTC node, but if the SNVS RTC driver isn't enabled, then SNVS doesn't work, and as such the pwrkey driver doesn't work (i.e. hangs the kernel, as the clock isn't enabled). Also see commit ec2a844ef7c1 ("ARM: dts: imx7s: add snvs rtc clock") for a similar fix. Signed-off-by: André Draszik <git@andred.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11Merge v5.6-rc5 into drm-nextDave Airlie
Requested my mripard for some misc patches that need this as a base. Signed-off-by: Dave Airlie <airlied@redhat.com>
2020-03-10ARM: bcm: Drop unneeded select of PCI_DOMAINS_GENERIC, HAVE_SMP, TIMER_OFGeert Uytterhoeven
Support for Broadcom SoCs depends on ARCH_MULTI_V6_V7, and thus on ARCH_MULTIPLATFORM, which selects PCI_DOMAINS_GENERIC and TIMER_OF. Support for the various Broadcom IPROC architected SoCs depends on ARCH_MULTI_V7, which selects HAVE_SMP. Hence there is no need for the Broadcom-specific symbols to select any of them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-03-10ARM: dts: imx6sx-softing-vining-2000: Enable PCI supportFabio Estevam
Add PCI support. Since this board has an active high PCI reset line, pass the 'reset-gpio-active-high' property. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10ARM: multi_v7_defconfig: enable drm imx supportChristian Gmeiner
It will be useful to have it enabled for KernelCI boot and runtime testing. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-09ARM: dts: at91: sama5d2: add i2c gpio pinctrlKamel Bouhara
Add the i2c gpio pinctrls to support the i2c bus recovery Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> [codrin.ciubotariu@microchip.com: removed gpio pull-ups] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200225155012.22764-4-codrin.ciubotariu@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-03-09ARM: dts: at91: sama5d4: add i2c gpio pinctrlKamel Bouhara
Add the i2c gpio pinctrls so the i2c bus recovery option can be enabled Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> [codrin.ciubotariu@microchip.com: removed gpio pull-ups] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200225155012.22764-3-codrin.ciubotariu@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-03-09ARM: dts: at91: sama5d3: add i2c gpio pinctrlKamel Bouhara
Add the i2c gpio pinctrls to support the i2c bus recovery Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> [codrin.ciubotariu@microchip.com: removed gpio pull-ups] Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200225155012.22764-2-codrin.ciubotariu@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-03-09ARM: dts: at91: sama5d4: use correct rtc compatibleAlexandre Belloni
Use the sama5d4 specific compatible string for the RTC. Link: https://lore.kernel.org/r/20191229204421.337612-9-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-03-09ARM: dts: at91: sama5d2: use correct rtc compatibleAlexandre Belloni
Use the sama5d2 specific compatible string for the RTC. Link: https://lore.kernel.org/r/20191229204421.337612-8-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
generated by cgit (git 2.34.1) at 2025-09-18 14:42:35 +0000