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2020-01-13x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlockedSean Christopherson
WARN if the IA32_FEAT_CTL MSR is somehow left unlocked now that CPU initialization unconditionally locks the MSR. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20191221044513.21680-6-sean.j.christopherson@intel.com
2020-01-13x86/intel: Initialize IA32_FEAT_CTL MSR at bootSean Christopherson
Opportunistically initialize IA32_FEAT_CTL to enable VMX when the MSR is left unlocked by BIOS. Configuring feature control at boot time paves the way for similar enabling of other features, e.g. Software Guard Extensions (SGX). Temporarily leave equivalent KVM code in place in order to avoid introducing a regression on Centaur and Zhaoxin CPUs, e.g. removing KVM's code would leave the MSR unlocked on those CPUs and would break existing functionality if people are loading kvm_intel on Centaur and/or Zhaoxin. Defer enablement of the boot-time configuration on Centaur and Zhaoxin to future patches to aid bisection. Note, Local Machine Check Exceptions (LMCE) are also supported by the kernel and enabled via feature control, but the kernel currently uses LMCE if and only if the feature is explicitly enabled by BIOS. Keep the current behavior to avoid introducing bugs, future patches can opt in to opportunistic enabling if it's deemed desirable to do so. Always lock IA32_FEAT_CTL if it exists, even if the CPU doesn't support VMX, so that other existing and future kernel code that queries the MSR can assume it's locked. Start from a clean slate when constructing the value to write to IA32_FEAT_CTL, i.e. ignore whatever value BIOS left in the MSR so as not to enable random features or fault on the WRMSR. Suggested-by: Borislav Petkov <bp@suse.de> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20191221044513.21680-5-sean.j.christopherson@intel.com
2020-01-13x86/msr-index: Clean up bit defines for IA32_FEATURE_CONTROL MSRSean Christopherson
As pointed out by Boris, the defines for bits in IA32_FEATURE_CONTROL are quite a mouthful, especially the VMX bits which must differentiate between enabling VMX inside and outside SMX (TXT) operation. Rename the MSR and its bit defines to abbreviate FEATURE_CONTROL as FEAT_CTL to make them a little friendlier on the eyes. Arguably, the MSR itself should keep the full IA32_FEATURE_CONTROL name to match Intel's SDM, but a future patch will add a dedicated Kconfig, file and functions for the MSR. Using the full name for those assets is rather unwieldy, so bite the bullet and use IA32_FEAT_CTL so that its nomenclature is consistent throughout the kernel. Opportunistically, fix a few other annoyances with the defines: - Relocate the bit defines so that they immediately follow the MSR define, e.g. aren't mistaken as belonging to MISC_FEATURE_CONTROL. - Add whitespace around the block of feature control defines to make it clear they're all related. - Use BIT() instead of manually encoding the bit shift. - Use "VMX" instead of "VMXON" to match the SDM. - Append "_ENABLED" to the LMCE (Local Machine Check Exception) bit to be consistent with the kernel's verbiage used for all other feature control bits. Note, the SDM refers to the LMCE bit as LMCE_ON, likely to differentiate it from IA32_MCG_EXT_CTL.LMCE_EN. Ignore the (literal) one-off usage of _ON, the SDM is simply "wrong". Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20191221044513.21680-2-sean.j.christopherson@intel.com
2020-01-13x86/resctrl: Do not reconfigure exiting tasksXiaochen Shen
When writing a pid to file "tasks", a callback function move_myself() is queued to this task to be called when the task returns from kernel mode or exits. The purpose of move_myself() is to activate the newly assigned closid and/or rmid associated with this task. This activation is done by calling resctrl_sched_in() from move_myself(), the same function that is called when switching to this task. If this work is successfully queued but then the task enters PF_EXITING status (e.g., receiving signal SIGKILL, SIGTERM) prior to the execution of the callback move_myself(), move_myself() still calls resctrl_sched_in() since the task status is not currently considered. When a task is exiting, the data structure of the task itself will be freed soon. Calling resctrl_sched_in() to write the register that controls the task's resources is unnecessary and it implies extra performance overhead. Add check on task status in move_myself() and return immediately if the task is PF_EXITING. [ bp: Massage. ] Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lkml.kernel.org/r/1578500026-21152-1-git-send-email-xiaochen.shen@intel.com
2020-01-13ARM: davinci: dm644x-evm: Add Fixed regulators needed for tlv320aic33Peter Ujfalusi
The codec driver needs correct regulators in order to probe. Both VCC_3.3V and VCC_1.8V is always on fixed regulators on the board. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-13ARM: davinci: dm365-evm: Add Fixed regulators needed for tlv320aic3101Peter Ujfalusi
The codec driver needs correct regulators in order to probe. Both VCC_3V3 and VCC_1V8 is always on fixed regulators on the board. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-13arm64: kernel: Correct annotation of end of el0_syncMark Brown
Commit 582f95835a8fc812c ("arm64: entry: convert el0_sync to C") caused the ENDPROC() annotating the end of el0_sync to be placed after the code for el0_sync_compat. This replaced the previous annotation where it was located after all the cases that are now converted to C, including after the currently unannotated el0_irq_compat and el0_error_compat. Move the annotation to the end of the function and add separate annotations for the _compat ones. Fixes: 582f95835a8fc812c (arm64: entry: convert el0_sync to C) Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
2020-01-13Merge 5.5-rc6 into tty-nextGreg Kroah-Hartman
We need the serial/tty fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-13Merge 5.5-rc6 into usb-nextGreg Kroah-Hartman
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-13ARM: dts: rockchip: add reg property to brcmf sub node for rk3188-bqedison2qcJohan Jonker
An experimental test with the command below gives this error: rk3188-bqedison2qc.dt.yaml: dwmmc@10218000: wifi@1: 'reg' is a required property So fix this by adding a reg property to the brcmf sub node. Also add #address-cells and #size-cells to prevent more warnings. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110134420.11280-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13arm64: dts: rockchip: hook up the px30-evb dsi displayHeiko Stuebner
Create the necessary display nodes to activate the Xingpeng XPP055C272 dsi display that can be found on the px30-evb. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20191209145301.5307-2-heiko@sntech.de
2020-01-13Merge back power capping changes for v5.6.Rafael J. Wysocki
2020-01-13arm64: dts: mt8183: add reset-cells in infracfgyong.liang
Include mt8183-reset.h and add reset-cells in infracfg in dtsi file Signed-off-by: yong.liang <yong.liang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-01-13arm64: dts: rockchip: Enable sdio0 and uart0 on rk3399-roc-pc-mezzanineMarkus Reichl
The mezzanine board carries an E key type M.2 slot. This is connected to USB, SDIO and UART0. Enable sdio and uart0 for use with wlan and/or bt M.2 cards. Signed-off-by: Markus Reichl <m.reichl@fivetechno.de> Link: https://lore.kernel.org/r/20200109154211.1530-1-m.reichl@fivetechno.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13arm64: dts: rockchip: add reg property to brcmf sub-nodesJohan Jonker
An experimental test with the command below gives this error: rk3399-firefly.dt.yaml: dwmmc@fe310000: wifi@1: 'reg' is a required property rk3399-orangepi.dt.yaml: dwmmc@fe310000: wifi@1: 'reg' is a required property rk3399-khadas-edge.dt.yaml: dwmmc@fe310000: wifi@1: 'reg' is a required property rk3399-khadas-edge-captain.dt.yaml: dwmmc@fe310000: wifi@1: 'reg' is a required property rk3399-khadas-edge-v.dt.yaml: dwmmc@fe310000: wifi@1: 'reg' is a required property So fix this by adding a reg property to the brcmf sub node. Also add #address-cells and #size-cells to prevent more warnings. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110142128.13522-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13arm64: dts: rockchip: fix dwmmc clock name for rk3308Johan Jonker
An experimental test with the command below gives this error: rk3308-evb.dt.yaml: dwmmc@ff480000: clock-names:2: 'ciu-drive' was expected 'ciu-drv' is not a valid dwmmc clock name, so fix this by changing it to 'ciu-drive'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110161200.22755-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13arm64: dts: rockchip: fix dwmmc clock name for px30Johan Jonker
An experimental test with the command below gives this error: px30-evb.dt.yaml: dwmmc@ff390000: clock-names:2: 'ciu-drive' was expected 'ciu-drv' is not a valid dwmmc clock name, so fix this by changing it to 'ciu-drive'. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200110161200.22755-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-01-13x86/mce: Fix use of uninitialized MCE message stringJan H. Schönherr
The function mce_severity() is not required to update its msg argument. In fact, mce_severity_amd() does not, which makes mce_no_way_out() return uninitialized data, which may be used later for printing. Assuming that implementations of mce_severity() either always or never update the msg argument (which is currently the case), it is sufficient to initialize the temporary variable in mce_no_way_out(). While at it, avoid printing a useless "Unknown". Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200103150722.20313-4-jschoenh@amazon.de
2020-01-13x86/mce: Fix mce=nobootlogJan H. Schönherr
Since commit 8b38937b7ab5 ("x86/mce: Do not enter deferred errors into the generic pool twice") the mce=nobootlog option has become mostly ineffective (after being only slightly ineffective before), as the code is taking actions on MCEs left over from boot when they have a usable address. Move the check for MCP_DONTLOG a bit outward to make it effective again. Also, since commit 011d82611172 ("RAS: Add a Corrected Errors Collector") the two branches of the remaining "if" at the bottom of machine_check_poll() do same. Unify them. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200103150722.20313-3-jschoenh@amazon.de
2020-01-13x86/mce: Take action on UCNA/Deferred errors againJan H. Schönherr
Commit fa92c5869426 ("x86, mce: Support memory error recovery for both UCNA and Deferred error in machine_check_poll") added handling of UCNA and Deferred errors by adding them to the ring for SRAO errors. Later, commit fd4cf79fcc4b ("x86/mce: Remove the MCE ring for Action Optional errors") switched storage from the SRAO ring to the unified pool that is still in use today. In order to only act on the intended errors, a filter for MCE_AO_SEVERITY is used -- effectively removing handling of UCNA/Deferred errors again. Extend the severity filter to include UCNA/Deferred errors again. Also, generalize the naming of the notifier from SRAO to UC to capture the extended scope. Note, that this change may cause a message like the following to appear, as the same address may be reported as SRAO and as UCNA: Memory failure: 0x5fe3284: already hardware poisoned Technically, this is a return to previous behavior. Signed-off-by: Jan H. Schönherr <jschoenh@amazon.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/20200103150722.20313-2-jschoenh@amazon.de
2020-01-13arm64: dts: allwinner: a64: enable DVFSVasily Khoruzhick
Add CPU regulator and operating points for all the A64-based boards that are currently supported to enable DVFS. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add dtsi with CPU operating pointsVasily Khoruzhick
Add operating points for A64. These are taken from FEX file from BSP for A64. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add cooling maps and thermal tripping pointsVasily Khoruzhick
Add cooling maps and thermal tripping points to prevent CPU overheating when running at the highest frequency. Tripping points are taken from A33 dts since A64 user manual doesn't mention when we should start throttling. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-13arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodesVasily Khoruzhick
Add CPU clock to the CPU nodes since it is a prerequisite for enabling DVFS. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> [wens@csie.org: Replace CLK_CPUX macro with raw number] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-01-13ARM: davinci: remove legacy timer supportBartosz Golaszewski
All platforms have now been switched to the new clocksource driver. Remove the old code and various no longer needed bits and pieces. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-13ARM: davinci: dm365: switch to using the clocksource driverBartosz Golaszewski
We now have a proper clocksource driver for davinci. Switch the dm365 platform to using it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-01-12Merge tag 'riscv/for-v5.5-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: "Two fixes for RISC-V: - Clear FP registers during boot when FP support is present, rather than when they aren't present - Move the header files associated with the SiFive L2 cache controller to drivers/soc (where the code was recently moved)" * tag 'riscv/for-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fixup obvious bug for fp-regs reset riscv: move sifive_l2_cache.h to include/soc
2020-01-12ARM/net: ixp4xx: Pass ethernet physical base as resourceLinus Walleij
In order to probe this ethernet interface from the device tree all physical MMIO regions must be passed as resources. Begin this rewrite by first passing the port base address as a resource for all platforms using this driver, remap it in the driver and avoid using any reference of the statically mapped virtual address in the driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12ixp4xx_eth: move platform_data definitionArnd Bergmann
The platform data is needed to compile the driver as standalone, so move it to a global location along with similar files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12ptp: ixp46x: move adjacent to ethernet driverArnd Bergmann
The ixp46x ptp driver has a somewhat unusual setup, where the ptp driver and the ethernet driver are in different directories but access the same registers that are defined a platform specific header file. Moving everything into drivers/net/ makes it look more like most other ptp drivers and allows compile-testing this driver on other targets. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12wan: ixp4xx_hss: prepare compile testingArnd Bergmann
The ixp4xx_hss driver needs the platform data definition and the system clock rate to be compiled. Move both into a new platform_data header file. This is a prerequisite for compile testing, but turning on compile testing requires further patches to isolate the SoC headers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-01-12riscv: Fixup obvious bug for fp-regs resetGuo Ren
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine ISA Register misa. Every bit:1 indicate a feature, so we should beqz reset_done when there is no F/D bit in csr_misa register. Signed-off-by: Guo Ren <ren_guo@c-sky.com> [paul.walmsley@sifive.com: fix typo in commit message] Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2020-01-12riscv: move sifive_l2_cache.h to include/socYash Shah
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2020-01-12m68k: defconfig: Update defconfigs for v5.5-rc3Geert Uytterhoeven
- Enable modular build of new crypto algorithms: - CONFIG_CRYPTO_BLAKE2S=m, - CONFIG_CRYPTO_CURVE25519=m, - CONFIG_CRYPTO_LIB_BLAKE2S=m, - CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m, - CONFIG_CRYPTO_LIB_CURVE25519=m. - Remove CONFIG_CRYPTO_XXHASH=m (auto-selected by CONFIG_BTRFS_FS since commit 3951e7f050ac6a38 ("btrfs: add xxhash64 to checksumming algorithms"), - Move CONFIG_EARLY_PRINTK. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-12m68k: Wire up clone3() syscallKars de Jong
Wire up the clone3() syscall for m68k. The special entry point is done in assembler as was done for clone() as well. This is needed because all registers need to be saved. The C wrapper then calls the generic sys_clone3() with the correct arguments. Tested on A1200 using the simple test program from: https://lore.kernel.org/lkml/20190716130631.tohj4ub54md25dys@brauner.io/ Signed-off-by: Kars de Jong <jongk@linux-m68k.org> Link: https://lore.kernel.org/r/20191124195225.31230-1-jongk@linux-m68k.org Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-12sparc: Add .exit.data section.David S. Miller
This fixes build errors of all sorts. Also, emit .exit.text unconditionally. Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-12ARM: dts: imx: Add GW5912 board supportRobert Jones
The Gateworks GW5912 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - GbE RJ45 front-panel - 4x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, mSATA - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine - 10V to 60V DC input barrel jack - 3axis accelerometer (lis2de12) - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - nanoSIM/microSD socket (with UHS-I support) - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - CAN Bus transceiver (mcp2562) - RS232 transceiver (1x UART with flow-control or 2x UART (build option) - off-board SPI connector (1x chip-select) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5913 board supportRobert Jones
The Gateworks GW5913 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE RJ45 front-panel - 1x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM - 6V to 60V DC input connector - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - nanoSIM socket - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5910 board supportTim Harvey
The Gateworks GW5910 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE RJ45 front-panel - 1x miniPCIe socket with PCI Gen2, USB2 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM - 5V to 60V DC input barrel jack - 3axis accelerometer (lis2de12) - GPS (ublox ZOE-M8Q) - bi-color front-panel LED - 256MB NAND boot device - microSD socket (with UHS-I support) - user pushbutton - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6) - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6) - RS232 transceiver (1x UART with flow-control or 2x UART (build option) - off-board SPI connector (1x chip-select) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Robert Jones <rjones@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12ARM: dts: imx: Add GW5907 board supportRobert Jones
The Gateworks GW5907 is an IMX6 SoC based single board computer with: - IMX6Q or IMX6DL - 32bit DDR3 DRAM - FEC GbE Phy - bi-color front-panel LED - 256MB NAND boot device - Gateworks System Controller (hwmon, pushbutton controller, EEPROM) - Digital IO expander (pca9555) - Joystick 12bit adc (ads1015) Signed-off-by: Robert Jones <rjones@gateworks.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12arm64: defconfig: Enable CONFIG_CLK_IMX8MP by defaultAnson Huang
Select CONFIG_CLK_IMX8MP by default to support i.MX8MP clock driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-11Merge tag 'clone3-tls-v5.5-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux Pull thread fixes from Christian Brauner: "This contains a series of patches to fix CLONE_SETTLS when used with clone3(). The clone3() syscall passes the tls argument through struct clone_args instead of a register. This means, all architectures that do not implement copy_thread_tls() but still support CLONE_SETTLS via copy_thread() expecting the tls to be located in a register argument based on clone() are currently unfortunately broken. Their tls value will be garbage. The patch series fixes this on all architectures that currently define __ARCH_WANT_SYS_CLONE3. It also adds a compile-time check to ensure that any architecture that enables clone3() in the future is forced to also implement copy_thread_tls(). My ultimate goal is to get rid of the copy_thread()/copy_thread_tls() split and just have copy_thread_tls() at some point in the not too distant future (Maybe even renaming copy_thread_tls() back to simply copy_thread() once the old function is ripped from all arches). This is dependent now on all arches supporting clone3(). While all relevant arches do that now there are still four missing: ia64, m68k, sh and sparc. They have the system call reserved, but not implemented. Once they all implement clone3() we can get rid of ARCH_WANT_SYS_CLONE3 and HAVE_COPY_THREAD_TLS. This series also includes a minor fix for the arm64 uapi headers which caused __NR_clone3 to be missing from the exported user headers. Unfortunately the series came in a little late especially given that it touches a range of architectures. Due to the holidays not all arch maintainers responded in time probably due to their backlog. Will and Arnd have thankfully acked the arm specific changes. Given that the changes are straightforward and rather minimal combined with the fact the that clone3() with CLONE_SETTLS is broken I decided to send them post rc3 nonetheless" * tag 'clone3-tls-v5.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux: um: Implement copy_thread_tls clone3: ensure copy_thread_tls is implemented xtensa: Implement copy_thread_tls riscv: Implement copy_thread_tls parisc: Implement copy_thread_tls arm: Implement copy_thread_tls arm64: Implement copy_thread_tls arm64: Move __ARCH_WANT_SYS_CLONE3 definition to uapi headers
2020-01-11Merge tag 'samsung-dt-5.6' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.6 1. Couple ARM and wcore bus regulators on Exynos542x so higher frequencies could be used with dynamic voltage and frequency scaling. Enable this higher frequencies. 2. Correct the polarity of USB3503 hub GPIOs. 3. Adjust the bus frequencies (scaled with devfreq framework) on Exynos5422 Odroid boards to match values possible to obtain from root PLLs. 4. Add display to Tiny4412 board. 5. Cleanups and minor improvements. * tag 'samsung-dt-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Enable FIMD node and add proper panel node to Tiny4412 ARM: dts: samsung: Rename Samsung and Exynos to lowercase ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids ARM: dts: exynos: Move Exynos5420 bus related OPPs to the Odroid boards DTS ARM: dts: exynos: Correct USB3503 GPIOs polarity ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800 ARM: dts: exynos: Add initial data for coupled regulators for Exynos5422/5800 ARM: dts: exynos: Remove syscon compatible from chipid node on Exynos5 Link: https://lore.kernel.org/r/20200110172334.4767-3-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-11x86/nmi: Remove irq_work from the long duration NMI handlerChangbin Du
First, printk() is NMI-context safe now since the safe printk() has been implemented and it already has an irq_work to make NMI-context safe. Second, this NMI irq_work actually does not work if a NMI handler causes panic by watchdog timeout. It has no chance to run in such case, while the safe printk() will flush its per-cpu buffers before panicking. While at it, repurpose the irq_work callback into a function which concentrates the NMI duration checking and makes the code easier to follow. [ bp: Massage. ] Signed-off-by: Changbin Du <changbin.du@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20200111125427.15662-1-changbin.du@gmail.com
2020-01-10Merge tag 'samsung-soc-5.6' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc Samsung mach/soc changes for v5.6 Cleanups (Samsung and Exynos names, Kconfig help text correction). * tag 'samsung-soc-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: samsung: Rename Samsung and Exynos to lowercase ARM: exynos: Correct the help text for platform Kconfig option Link: https://lore.kernel.org/r/20200110172334.4767-4-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'v5.6-rockchip-dts64-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New boards are the Radxa Rock Pi N10 using the VMARC SOM and Dalang carrier board, separate versions for the two rockpro64 hardware revisions which switched a pin between revisions. The rockpro64 also got bluetooth support now. The px30 got a lot of attention with dsi, gpu and thermal support. Similarly the rk3399-roc-pc board also got attention with mtd flash, sdr104 mode, hdmi sound, gpu and a lot of other smaller improvements. Other than that there is a new gpu-cooling device for rk3399 a cpu idle-state for rk3328 and more small improvements across a number of boards. * tag 'v5.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (37 commits) arm64: dts: rockchip: Enable mp8859 regulator on rk3399-roc-pc arm64: dts: rockchip: rk3399-hugsun-x99: remove supports-sd and supports-emmc options arm64: dts: rockchip: rk3399-firefly: remove num-slots from &sdio0 node arm64: dts: rockchip: Add PX30 LVDS arm64: dts: rockchip: add dsi controller for px30 arm64: dts: rockchip: Add PX30 DSI DPHY arm64: dts: rockchip: Add RK3328 idle state arm64: dts: rockchip: remove identical &uart0 node from rk3368-lion-haikou arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support ARM: dts: rockchip: Add Radxa Dalang Carrier board arm64: dts: rockchip: Add VMARC RK3399Pro SOM initial support dt-bindings: arm: rockchip: Add Rock Pi N10 binding arm64: dts: rockchip: hook up bluetooth at uart0 on rockpro64 arm64: dts: rockchip: enable wifi module at sdio0 on rockpro64 arm64: dts: rockchip: split rk3399-rockpro64 for v2 and v2.1 boards arm64: dts: rockchip: enable the gpu on px30-evb arm64: dts: rockchip: add the gpu for px30 dt-bindings: gpu: mali-bifrost: Add Rockchip PX30 arm64: dts: rockchip: Add GPU cooling device for RK3399 arm64: dts: rockchip: Add regulators for PCIe for Radxa Rock Pi 4 board ... Link: https://lore.kernel.org/r/5115625.yBEeHQkg2z@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'v5.6-rockchip-dts32-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and additional operating points for rk3288-tinker. * tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'amlogic-defconfig' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/defconfig arm64: defconfig updates for v5.6 - enable FUSB302 as module * tag 'amlogic-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: defconfig: enable FUSB302 as module Link: https://lore.kernel.org/r/7hftgoeaad.fsf@baylibre.com Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10ARM: multi_v7_defconfig: enable STM32 PWR regulatorAmelie Delaunay
This enables the driver for STM32 PWR regulators found on stm32mp1. Link: https://lore.kernel.org/r/20200109125531.13610-1-alexandre.torgue@st.com Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-10Merge tag 'stm32-dt-for-v5.6-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v5.6, round 1 Highlights: ---------- MPU part: -Add PWM support on DK2 board. -Add counter support to STM32 timers. -Add support of SDMMC 2&3 instances based on "arm,pl18x". SDMMC2 is connected to eMMC on ED1 board. SDMMC3 is connected to the GPIO extension connector on EV1 & DKx boards. -Add ADC support on ED1 board. -Update devicetree files split to better fit to STM32MP15 SOC & boards diversity. -Fix issues seen during YAML validation. -Enable Ethernet (MAC) TX clock gating during low-power mode. -Enable USB OTG HS support on DKx boards. -Enable USB Host EHCI on DKx boards. MCU part: -Fix issues seen during YAML validation. * tag 'stm32-dt-for-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (37 commits) ARM: dts: stm32: Add power-supply for RGB panel on stm32429i-eval ARM: dts: stm32: Add power-supply for DSI panel on stm32f469-disco ARM: dts: stm32: change nvmem node name on stm32mp1 ARM: dts: stm32: change nvmem node name on stm32f429 ARM: dts: stm32: update mlahb node according to the bindings on stm32mp15 ARM: dts: stm32: fix dma controller node name on stm32mp157c ARM: dts: stm32: fix dma controller node name on stm32f743 ARM: dts: stm32: fix dma controller node name on stm32f746 ARM: dts: stm32: add phy-names to usbotg_hs on stm32mp157c-ev1 ARM: dts: stm32: enable USB OTG HS on stm32mp15 DKx boards ARM: dts: stm32: enable USB Host (USBH) EHCI controller on stm32mp15 DKx ARM: dts: stm32: enable USBPHYC on stm32mp15 DKx boards ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746 ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429 ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on stm32mp15 ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15 ARM: dts: stm32: remove syscfg clock on stm32mp15 ethernet ARM: dts: stm32: remove "@" and "_" from stm32f7 pinmux groups ARM: dts: stm32: remove "@" and "_" from stm32f4 pinmux groups ARM: dts: stm32: Adapt STM32MP157C ED1 board to STM32 DT diversity ... Link: https://lore.kernel.org/r/39df1dee-3c9f-cd35-bc55-a71223e07100@st.com Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit (git 2.34.1) at 2025-09-15 02:41:46 +0000