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2020-05-17arm64: dts: marvell: armada-37xx: Move PCIe comphy handle propertyMarek Behún
Move the comphy handle property of the PCIe node from board specific device tree files (EspressoBin and Turris Mox) to the generic armada-37xx.dtsi. This is correct since this is the only possible PCIe PHY configuration on Armada 37xx, so when PCIe is enabled on any board, this handle is correct. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio functionMarek Behún
We found out that we are unable to control the PERST# signal via the default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe register space called PERSTN_GPIO_EN (D0088004[3]), but changing the value of this register does not change the pin output when measuring with voltmeter. We do not know if this is a bug in the SOC, or if it works only when PCIe controller is in a certain state. Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before training link") says that when this pin changes pinctrl mode from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief moment. So currently the situation is that on A3700 boards the PERST# signal is asserted in U-Boot (because the code in U-Boot issues reset via this pin via GPIO mode), and then in Linux by the obscure and undocumented mechanism described by the above mentioned commit. We want to issue PERST# signal in a known way, therefore this patch changes the pcie_reset_pin function from "pcie" to "gpio" and adds the reset-gpios property to the PCIe node in device tree files of EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already has this property and uDPU does not have a PCIe port). Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Remi Pommarel <repk@triplefau.lt> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17arm64: dts: update SolidRun Armada 8040 phy interface typesRussell King
Update the SolidRun Armada 8040 platforms phy interface types from the old 10gbase-kr to the newer and more correct 10gbase-r. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17arm64: dts: imx8mp: add "fsl,imx6sx-fec" compatible stringFugang Duan
Add "fsl,imx6sx-fec" compatible string for fec node, then i.MX8MP EVK ethernet function can work now. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-17mips/mm: Add page soft dirty trackingGuoyun Sun
User space checkpoint and restart tool (CRIU) needs the page's change to be soft tracked. This allows to do a pre checkpoint and then dump only touched pages. Signed-off-by: Guoyun Sun <sunguoyun@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-17MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bitsWANG Xuerui
These are exposed to userland alternatively via the new CPUCFG instruction on Loongson-3A R4 and above. Add definitions for readback on older cores. Signed-off-by: WANG Xuerui <git@xen0n.name> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-17MIPS: Loongson64: define offsets and known revisions for some CPUCFG featuresWANG Xuerui
Add the constants for easier and maintainable composition of CPUCFG values. Signed-off-by: WANG Xuerui <git@xen0n.name> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-17MIPS: Loongson64: fix typos in loongson_regs.hWANG Xuerui
Fix some symbol names to align with Loongson's User Manual wording. Also correct the comment in csr_readq() suggesting the wrong instruction in use. Fixes: 6a6f9b7dafd50efc ("MIPS: Loongson: Add CFUCFG&CSR support") Signed-off-by: WANG Xuerui <git@xen0n.name> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-17MIPS: Remove not used 8250-platform.cTiezhu Yang
When CONFIG_HAVE_STD_PC_SERIAL_PORT is set, there exists build errors of 8250-platform.c due to linux/module.h is not included. CONFIG_HAVE_STD_PC_SERIAL_PORT is not used in arch/mips for many years, 8250-platform.c is also not built and used, so it is not necessary to fix the build errors, just remove the not used file 8250-platform.c and the related code in Kconfig and Makefile. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-17MIPS: Loongson: Build ATI Radeon GPU driver as moduleTiezhu Yang
When ATI Radeon GPU driver has been compiled directly into the kernel instead of as a module, we should make sure the firmware for the model (check available ones in /lib/firmware/radeon) is built-in to the kernel as well, otherwise there exists the following fatal error during GPU init, change CONFIG_DRM_RADEON=y to CONFIG_DRM_RADEON=m to fix it. [ 1.900997] [drm] Loading RS780 Microcode [ 1.905077] radeon 0000:01:05.0: Direct firmware load for radeon/RS780_pfp.bin failed with error -2 [ 1.914140] r600_cp: Failed to load firmware "radeon/RS780_pfp.bin" [ 1.920405] [drm:r600_init] *ERROR* Failed to load firmware! [ 1.926069] radeon 0000:01:05.0: Fatal error during GPU init [ 1.931729] [drm] radeon: finishing device. Fixes: 024e6a8b5bb1 ("MIPS: Loongson: Add a Loongson-3 default config file") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-16Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "A new testcase for guest debugging (gdbstub) that exposed a bunch of bugs, mostly for AMD processors. And a few other x86 fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: Fix off-by-one error in kvm_vcpu_ioctl_x86_setup_mce KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c KVM: SVM: Disable AVIC before setting V_IRQ KVM: Introduce kvm_make_all_cpus_request_except() KVM: VMX: pass correct DR6 for GD userspace exit KVM: x86, SVM: isolate vcpu->arch.dr6 from vmcb->save.dr6 KVM: SVM: keep DR6 synchronized with vcpu->arch.dr6 KVM: nSVM: trap #DB and #BP to userspace if guest debugging is on KVM: selftests: Add KVM_SET_GUEST_DEBUG test KVM: X86: Fix single-step with KVM_SET_GUEST_DEBUG KVM: X86: Set RTM for DB_VECTOR too for KVM_EXIT_DEBUG KVM: x86: fix DR6 delivery for various cases of #DB injection KVM: X86: Declare KVM_CAP_SET_GUEST_DEBUG properly
2020-05-16Merge tag 'powerpc-5.7-4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - A fix for unrecoverable SLB faults in the interrupt exit path, introduced by the recent rewrite of interrupt exit in C. - Four fixes for our KUAP (Kernel Userspace Access Prevention) support on 64-bit. These are all fairly minor with the exception of the change to evaluate the get/put_user() arguments before we enable user access, which reduces the amount of code we run with user access enabled. - A fix for our secure boot IMA rules, if enforcement of module signatures is enabled at runtime rather than build time. - A fix to our 32-bit VDSO clock_getres() which wasn't falling back to the syscall for unknown clocks. - A build fix for CONFIG_PPC_KUAP_DEBUG on 32-bit BookS, and another for 40x. Thanks to: Christophe Leroy, Hugh Dickins, Nicholas Piggin, Aurelien Jarno, Mimi Zohar, Nayna Jain. * tag 'powerpc-5.7-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/40x: Make more space for system call exception powerpc/vdso32: Fallback on getres syscall when clock is unknown powerpc/32s: Fix build failure with CONFIG_PPC_KUAP_DEBUG powerpc/ima: Fix secure boot rules in ima arch policy powerpc/64s/kuap: Restore AMR in fast_interrupt_return powerpc/64s/kuap: Restore AMR in system reset exception powerpc/64/kuap: Move kuap checks out of MSR[RI]=0 regions of exit code powerpc/64s: Fix unrecoverable SLB crashes due to preemption check powerpc/uaccess: Evaluate macro arguments once, before user access is allowed
2020-05-16Merge tag 'csky-for-linus-5.7-rc6' of git://github.com/c-sky/csky-linuxLinus Torvalds
Pull csky updates from Guo Ren: - fix for copy_from/to_user (a hard-to-find bug, thx Viro) - fix for calltrace panic without FRAME_POINT - two fixes for perf - two build fixes - four fixes for non-fatal bugs (msa, rm dis_irq, cleanup psr, gdbmacros.txt) * tag 'csky-for-linus-5.7-rc6' of git://github.com/c-sky/csky-linux: csky: Fixup raw_copy_from_user() csky: Fixup gdbmacros.txt with name sp in thread_struct csky: Fixup remove unnecessary save/restore PSR code csky: Fixup remove duplicate irq_disable csky: Fixup calltrace panic csky: Fixup perf callchain unwind csky: Fixup msa highest 3 bits mask csky: Fixup perf probe -x hungup csky: Fixup compile error for abiv1 entry.S csky/ftrace: Fixup error when disable CONFIG_DYNAMIC_FTRACE
2020-05-16Merge tag 'arm-soc-fixes-5.7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC/dt fixes from Arnd Bergmann: "This round of fixes is almost exclusively device tree changes, with trivial defconfig fixes and one compiler warning fix added in. A number of patches are to fix dtc warnings, in particular on Amlogic, i.MX and Rockchips. Other notable changes include: Renesas: - Fix a wrong clock configuration on R-Mobile A1 - Fix IOMMU support on R-Car V3H Allwinner - Multiple audio fixes Qualcomm - Use a safe CPU voltage on MSM8996 - Fixes to match a late audio driver change Rockchip: - Some fixes for the newly added Pinebook Pro NXP i.MX: - Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board - Fix imx6dl-yapp4-ursa board Ethernet connection OMAP: - A regression fix for non-existing can device on am534x-idk - Fix flakey wlan on droid4 where some devices would not connect at all because of internal pull being used with an external pull - Fix occasional missed wake-up events on droid4 modem uart" * tag 'arm-soc-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits) ARM: dts: iwg20d-q7-dbcm-ca: Remove unneeded properties in hdmi@39 ARM: dts: renesas: Make hdmi encoder nodes compliant with DT bindings arm64: dts: renesas: Make hdmi encoder nodes compliant with DT bindings arm64: defconfig: add MEDIA_PLATFORM_SUPPORT arm64: defconfig: ARCH_R8A7795: follow changed config symbol name arm64: defconfig: add DRM_DISPLAY_CONNECTOR arm64: defconfig: DRM_DUMB_VGA_DAC: follow changed config symbol name ARM: oxnas: make ox820_boot_secondary static ARM: dts: r8a7740: Add missing extal2 to CPG node ARM: dts: omap4-droid4: Fix occasional lost wakeirq for uart1 ARM: dts: omap4-droid4: Fix flakey wlan by disabling internal pull for gpio arm64: dts: allwinner: a64: Remove unused SPDIF sound card arm64: dts: allwinner: a64: pinetab: Fix cpvdd supply name arm64: dts: meson-g12: remove spurious blank line arm64: dts: meson-g12b-khadas-vim3: add missing frddr_a status property arm64: dts: meson-g12-common: fix dwc2 clock names arm64: dts: meson-g12b-ugoos-am6: fix usb vbus-supply arm64: dts: freescale: imx8mp: update input_val for AUDIOMIX_BIT_STREAM ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes ARM: dts: rockchip: fix pinctrl sub nodename for spi in rk322x.dtsi ...
2020-05-16arm: dts: mt2701: Add usb2 device nodesMin Guo
Add musb nodes and usb2 phy nodes for MT2701 Signed-off-by: Min Guo <min.guo@mediatek.com> Link: https://lore.kernel.org/r/20191211015446.11477-3-min.guo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm: dts: mt7623: add Mali-450 device nodeRyder Lee
Add a node for Mali-450. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mt8173: Add capacity-dmips-mhz attributesUlrich Hecht
Dhrystone benchmark on Acer Chromebook R13 CB5-312T: A72: 15698587 dps @ 1807 MHz A53: 7598784 dps @ 1703 MHz Signed-off-by: Ulrich Hecht <uli-qwV78thtvt0@public.gmane.org> Link: https://lore.kernel.org/r/1563529816-3992-1-git-send-email-uli@fpond.eu Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mt2712: use non-empty ranges for usb-phyChunfeng Yun
Use non-empty ranges for usb-phy to make the layout of its registers clearer; Replace deprecated compatible by generic Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mt8173: fix mdp aliases property nameHsin-Yi Wang
Fix warning: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20200414030815.192104-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mediatek: Switch to SPDX license identifier for MT6797 SoCManivannan Sadhasivam
Switch to SPDX license identifier for MT6797 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200222162444.11590-5-manivannan.sadhasivam@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mediatek: Enable I2C support for 96Boards X20 Development boardManivannan Sadhasivam
There are 7 I2C ports used on this board. Hence, enable all of them. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200222162444.11590-4-manivannan.sadhasivam@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm64: dts: mediatek: Add I2C support for MT6797 SoCManivannan Sadhasivam
Add I2C support for Mediatek MT6797 SoC. There are a total of 8 I2C controllers in this SoC (2 being shared) and they are same as the controllers present in MT6577 SoC. Hence, the driver support is added with DT fallback method. As per the datasheet, there are controllers with _imm prefix like i2c2_imm and i2c3_imm. These appears to be in different memory regions but sharing the same pins with i2c2 and i2c3 respectively. Since there is no clear evidence of what they really are, I've adapted the numbering/naming scheme from the downstream code by Mediatek. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200222162444.11590-3-manivannan.sadhasivam@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16KVM: arm64: Make KVM_CAP_MAX_VCPUS compatible with the selected GIC versionMarc Zyngier
KVM_CAP_MAX_VCPUS always return the maximum possible number of VCPUs, irrespective of the selected interrupt controller. This is pretty misleading for userspace that selects a GICv2 on a GICv3 system that supports v2 compat: It always gets a maximum of 512 VCPUs, even if the effective limit is 8. The 9th VCPU will fail to be created, which is unexpected as far as userspace is concerned. Fortunately, we already have the right information stashed in the kvm structure, and we can return it as requested. Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com> Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Link: https://lore.kernel.org/r/20200427141507.284985-1-maz@kernel.org
2020-05-16KVM: arm64: Support enabling dirty log gradually in small chunksKeqian Zhu
There is already support of enabling dirty log gradually in small chunks for x86 in commit 3c9bd4006bfc ("KVM: x86: enable dirty log gradually in small chunks"). This adds support for arm64. x86 still writes protect all huge pages when DIRTY_LOG_INITIALLY_ALL_SET is enabled. However, for arm64, both huge pages and normal pages can be write protected gradually by userspace. Under the Huawei Kunpeng 920 2.6GHz platform, I did some tests on 128G Linux VMs with different page size. The memory pressure is 127G in each case. The time taken of memory_global_dirty_log_start in QEMU is listed below: Page Size Before After Optimization 4K 650ms 1.8ms 2M 4ms 1.8ms 1G 2ms 1.8ms Besides the time reduction, the biggest improvement is that we will minimize the performance side effect (because of dissolving huge pages and marking memslots dirty) on guest after enabling dirty log. Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200413122023.52583-1-zhukeqian1@huawei.com
2020-05-16KVM: arm64: Unify handling THP backed host memorySuzuki K Poulose
We support mapping host memory backed by PMD transparent hugepages at stage2 as huge pages. However the checks are now spread across two different places. Let us unify the handling of the THPs to keep the code cleaner (and future proof for PUD THP support). This patch moves transparent_hugepage_adjust() closer to the caller to avoid a forward declaration for fault_supports_stage2_huge_mappings(). Also, since we already handle the case where the host VA and the guest PA may not be aligned, the explicit VM_BUG_ON() is not required. Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200507123546.1875-3-yuzenghui@huawei.com
2020-05-16KVM: arm64: Clean up the checking for huge mappingSuzuki K Poulose
If we are checking whether the stage2 can map PAGE_SIZE, we don't have to do the boundary checks as both the host VMA and the guest memslots are page aligned. Bail the case easily. While we're at it, fixup a typo in the comment below. Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200507123546.1875-2-yuzenghui@huawei.com
2020-05-16KVM: arm/arm64: Release kvm->mmu_lock in loop to prevent starvationJiang Yi
Do cond_resched_lock() in stage2_flush_memslot() like what is done in unmap_stage2_range() and other places holding mmu_lock while processing a possibly large range of memory. Signed-off-by: Jiang Yi <giangyi@amazon.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20200415084229.29992-1-giangyi@amazon.com
2020-05-16KVM: arm64: Sidestep stage2_unmap_vm() on vcpu reset when S2FWB is supportedZenghui Yu
stage2_unmap_vm() was introduced to unmap user RAM region in the stage2 page table to make the caches coherent. E.g., a guest reboot with stage1 MMU disabled will access memory using non-cacheable attributes. If the RAM and caches are not coherent at this stage, some evicted dirty cache line may go and corrupt guest data in RAM. Since ARMv8.4, S2FWB feature is mandatory and KVM will take advantage of it to configure the stage2 page table and the attributes of memory access. So we ensure that guests always access memory using cacheable attributes and thus, the caches always be coherent. So on CPUs that support S2FWB, we can safely reset the vcpu without a heavy stage2 unmapping. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200415072835.1164-1-yuzenghui@huawei.com
2020-05-16KVM: Fix spelling in code commentsFuad Tabba
Fix spelling and typos (e.g., repeated words) in comments. Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200401140310.29701-1-tabba@google.com
2020-05-16KVM: arm64: Use cpus_have_final_cap for has_vhe()Marc Zyngier
By the time we start using the has_vhe() helper, we have long discovered whether we are running VHE or not. It thus makes sense to use cpus_have_final_cap() instead of cpus_have_const_cap(), which leads to a small text size reduction. Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: David Brazdil <dbrazdil@google.com> Link: https://lore.kernel.org/r/20200513103828.74580-1-maz@kernel.org
2020-05-16KVM: arm64: Simplify __kvm_timer_set_cntvoff implementationMarc Zyngier
Now that this function isn't constrained by the 32bit PCS, let's simplify it by taking a single 64bit offset instead of two 32bit parameters. Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-05-16KVM: arm64: Clean up kvm makefilesFuad Tabba
Consolidate references to the CONFIG_KVM configuration item to encompass entire folders rather than per line. Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20200505154520.194120-5-tabba@google.com
2020-05-16KVM: arm64: Change CONFIG_KVM to a menuconfig entryWill Deacon
Changing CONFIG_KVM to be a 'menuconfig' entry in Kconfig mean that we can straightforwardly enumerate optional features, such as the virtual PMU device as dependent options. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200505154520.194120-4-tabba@google.com
2020-05-16KVM: arm64: Update help textWill Deacon
arm64 KVM supports 16k pages since 02e0b7600f83 ("arm64: kvm: Add support for 16K pages"), so update the Kconfig help text accordingly. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200505154520.194120-3-tabba@google.com
2020-05-16KVM: arm64: Kill off CONFIG_KVM_ARM_HOSTWill Deacon
CONFIG_KVM_ARM_HOST is just a proxy for CONFIG_KVM, so remove it in favour of the latter. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Fuad Tabba <tabba@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200505154520.194120-2-tabba@google.com
2020-05-16KVM: arm64: Move virt/kvm/arm to arch/arm64Marc Zyngier
Now that the 32bit KVM/arm host is a distant memory, let's move the whole of the KVM/arm64 code into the arm64 tree. As they said in the song: Welcome Home (Sanitarium). Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20200513104034.74741-1-maz@kernel.org
2020-05-16x86/fpu/xstate: Restore supervisor states for signal returnYu-cheng Yu
The signal return fast path directly restores user states from the user buffer. Once that succeeds, restore supervisor states (but only when they are not yet restored). For the slow path, save supervisor states to preserve them across context switches, and restore after the user states are restored. The previous version has the overhead of an XSAVES in both the fast and the slow paths. It is addressed as the following: - In the fast path, only do an XRSTORS. - In the slow path, do a supervisor-state-only XSAVES, and relocate the buffer contents. Some thoughts in the implementation: - In the slow path, can any supervisor state become stale between save/restore? Answer: set_thread_flag(TIF_NEED_FPU_LOAD) protects the xstate buffer. - In the slow path, can any code reference a stale supervisor state register between save/restore? Answer: In the current lazy-restore scheme, any reference to xstate registers needs fpregs_lock()/fpregs_unlock() and __fpregs_load_activate(). - Are there other options? One other option is eagerly restoring all supervisor states. Currently, CET user-mode states and ENQCMD's PASID do not need to be eagerly restored. The upcoming CET kernel-mode states (24 bytes) need to be eagerly restored. To me, eagerly restoring all supervisor states adds more overhead then benefit at this point. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lkml.kernel.org/r/20200512145444.15483-11-yu-cheng.yu@intel.com
2020-05-16x86/fpu/xstate: Preserve supervisor states for the slow path in ↵Yu-cheng Yu
__fpu__restore_sig() The signal return code is responsible for taking an XSAVE buffer present in user memory and loading it into the hardware registers. This operation only affects user XSAVE state and never affects supervisor state. The fast path through this code simply points XRSTOR directly at the user buffer. However, since user memory is not guaranteed to be always mapped, this XRSTOR can fail. If it fails, the signal return code falls back to a slow path which can tolerate page faults. That slow path copies the xfeatures one by one out of the user buffer into the task's fpu state area. However, by being in a context where it can handle page faults, the code can also schedule. The lazy-fpu-load code would think it has an up-to-date fpstate and would fail to save the supervisor state when scheduling the task out. When scheduling back in, it would likely restore stale supervisor state. To fix that, preserve supervisor state before the slow path. Modify copy_user_to_fpregs_zeroing() so that if it fails, fpregs are not zeroed, and there is no need for fpregs_deactivate() and supervisor states are preserved. Move set_thread_flag(TIF_NEED_FPU_LOAD) to the slow path. Without doing this, the fast path also needs supervisor states to be saved first. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200512145444.15483-10-yu-cheng.yu@intel.com
2020-05-16x86/fpu: Introduce copy_supervisor_to_kernel()Yu-cheng Yu
The XSAVES instruction takes a mask and saves only the features specified in that mask. The kernel normally specifies that all features be saved. XSAVES also unconditionally uses the "compacted format" which means that all specified features are saved next to each other in memory. If a feature is removed from the mask, all the features after it will "move up" into earlier locations in the buffer. Introduce copy_supervisor_to_kernel(), which saves only supervisor states and then moves those states into the standard location where they are normally found. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200512145444.15483-9-yu-cheng.yu@intel.com
2020-05-16x86/nmi: Remove edac.h include leftoverBorislav Petkov
... which db47d5f85646 ("x86/nmi, EDAC: Get rid of DRAM error reporting thru PCI SERR NMI") forgot to remove. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200515182246.3553-1-bp@alien8.de
2020-05-15ARM: socfpga: Drop unneeded select of PCI_DOMAINS_GENERICGeert Uytterhoeven
Support for Altera SOCFPGA systems depends on ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM. As the latter selects PCI_DOMAINS_GENERIC, there is no need for ARCH_SOCFPGA to select PCI_DOMAINS_GENERIC. Link: https://lore.kernel.org/r/20200505150722.1575-16-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: prima2: Drop unneeded select of HAVE_SMPGeert Uytterhoeven
Support for CSR SiRF SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for ARCH_ATLAS7 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-14-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Barry Song <baohua@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: mvebu: Drop unneeded select of HAVE_SMPGeert Uytterhoeven
Support for Marvell Armada 375, 380, 385, and 39x SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_ARMADA_375, MACH_ARMADA_38X, and MACH_ARMADA_39X to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-12-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: mmp: Drop unneeded select of COMMON_CLKGeert Uytterhoeven
Support for Marvell MMP ARMv5 platforms depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects COMMON_CLK, there is no need for MACH_MMP_DT to select COMMON_CLK. Link: https://lore.kernel.org/r/20200505150722.1575-11-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: davinci: Drop unneeded select of TIMER_OFGeert Uytterhoeven
Support for TI DaVinci SoCs depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects TIMER_OF, there is no need for MACH_DA8XX_DT to select TIMER_OF. Link: https://lore.kernel.org/r/20200505150722.1575-9-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: clps711x: Drop unneeded select of multi-platform selected optionsGeert Uytterhoeven
Support for Cirrus Logic EP721x/EP731x-based SoCs depends on ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM. As the latter selects AUTO_ZRELADDR, TIMER_OF, COMMON_CLK, GENERIC_CLOCKEVENTS, and USE_OF, there is no need for ARCH_CLPS711X to select any of them. Link: https://lore.kernel.org/r/20200505150722.1575-8-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Alexander Shiyan <shc_work@mail.ru> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: berlin: Drop unneeded select of HAVE_SMPGeert Uytterhoeven
Support for Marvell Berlin SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_BERLIN_BG2 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-7-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: aspeed: Drop unneeded select of HAVE_SMPGeert Uytterhoeven
Support for the 6th generation Aspeed SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_ASPEED_G6 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-6-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: asm9260: Drop unneeded select of GENERIC_CLOCKEVENTSGeert Uytterhoeven
Support for the Alphascale ASM9260 platform depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects GENERIC_CLOCKEVENTS, there is no need for MACH_ASM9260 to select GENERIC_CLOCKEVENTS. Link: https://lore.kernel.org/r/20200505150722.1575-5-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Oleksij Rempel <linux@rempel-privat.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-15ARM: alpine: Drop unneeded select of HAVE_SMPGeert Uytterhoeven
Support for Annapurna Labs Alpine platforms depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for ARCH_ALPINE to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-4-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Tsahee Zidenberg <tsahee@annapurnalabs.com> Cc: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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