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2025-01-20Merge tag 'kvm-memslots-6.14' of https://github.com/kvm-x86/linux into HEADPaolo Bonzini
KVM kvm_set_memory_region() cleanups and hardening for 6.14: - Add proper lockdep assertions when setting memory regions. - Add a dedicated API for setting KVM-internal memory regions. - Explicitly disallow all flags for KVM-internal memory regions.
2025-01-20Grab mm lock before grabbing pt lockMaksym Planeta
Function xen_pin_page calls xen_pte_lock, which in turn grab page table lock (ptlock). When locking, xen_pte_lock expect mm->page_table_lock to be held before grabbing ptlock, but this does not happen when pinning is caused by xen_mm_pin_all. This commit addresses lockdep warning below, which shows up when suspending a Xen VM. [ 3680.658422] Freezing user space processes [ 3680.660156] Freezing user space processes completed (elapsed 0.001 seconds) [ 3680.660182] OOM killer disabled. [ 3680.660192] Freezing remaining freezable tasks [ 3680.661485] Freezing remaining freezable tasks completed (elapsed 0.001 seconds) [ 3680.685254] [ 3680.685265] ================================== [ 3680.685269] WARNING: Nested lock was not taken [ 3680.685274] 6.12.0+ #16 Tainted: G W [ 3680.685279] ---------------------------------- [ 3680.685283] migration/0/19 is trying to lock: [ 3680.685288] ffff88800bac33c0 (ptlock_ptr(ptdesc)#2){+.+.}-{3:3}, at: xen_pin_page+0x175/0x1d0 [ 3680.685303] [ 3680.685303] but this task is not holding: [ 3680.685308] init_mm.page_table_lock [ 3680.685311] [ 3680.685311] stack backtrace: [ 3680.685316] CPU: 0 UID: 0 PID: 19 Comm: migration/0 Tainted: G W 6.12.0+ #16 [ 3680.685324] Tainted: [W]=WARN [ 3680.685328] Stopper: multi_cpu_stop+0x0/0x120 <- __stop_cpus.constprop.0+0x8c/0xd0 [ 3680.685339] Call Trace: [ 3680.685344] <TASK> [ 3680.685347] dump_stack_lvl+0x77/0xb0 [ 3680.685356] __lock_acquire+0x917/0x2310 [ 3680.685364] lock_acquire+0xce/0x2c0 [ 3680.685369] ? xen_pin_page+0x175/0x1d0 [ 3680.685373] _raw_spin_lock_nest_lock+0x2f/0x70 [ 3680.685381] ? xen_pin_page+0x175/0x1d0 [ 3680.685386] xen_pin_page+0x175/0x1d0 [ 3680.685390] ? __pfx_xen_pin_page+0x10/0x10 [ 3680.685394] __xen_pgd_walk+0x233/0x2c0 [ 3680.685401] ? stop_one_cpu+0x91/0x100 [ 3680.685405] __xen_pgd_pin+0x5d/0x250 [ 3680.685410] xen_mm_pin_all+0x70/0xa0 [ 3680.685415] xen_pv_pre_suspend+0xf/0x280 [ 3680.685420] xen_suspend+0x57/0x1a0 [ 3680.685428] multi_cpu_stop+0x6b/0x120 [ 3680.685432] ? update_cpumasks_hier+0x7c/0xa60 [ 3680.685439] ? __pfx_multi_cpu_stop+0x10/0x10 [ 3680.685443] cpu_stopper_thread+0x8c/0x140 [ 3680.685448] ? smpboot_thread_fn+0x20/0x1f0 [ 3680.685454] ? __pfx_smpboot_thread_fn+0x10/0x10 [ 3680.685458] smpboot_thread_fn+0xed/0x1f0 [ 3680.685462] kthread+0xde/0x110 [ 3680.685467] ? __pfx_kthread+0x10/0x10 [ 3680.685471] ret_from_fork+0x2f/0x50 [ 3680.685478] ? __pfx_kthread+0x10/0x10 [ 3680.685482] ret_from_fork_asm+0x1a/0x30 [ 3680.685489] </TASK> [ 3680.685491] [ 3680.685491] other info that might help us debug this: [ 3680.685497] 1 lock held by migration/0/19: [ 3680.685500] #0: ffffffff8284df38 (pgd_lock){+.+.}-{3:3}, at: xen_mm_pin_all+0x14/0xa0 [ 3680.685512] [ 3680.685512] stack backtrace: [ 3680.685518] CPU: 0 UID: 0 PID: 19 Comm: migration/0 Tainted: G W 6.12.0+ #16 [ 3680.685528] Tainted: [W]=WARN [ 3680.685531] Stopper: multi_cpu_stop+0x0/0x120 <- __stop_cpus.constprop.0+0x8c/0xd0 [ 3680.685538] Call Trace: [ 3680.685541] <TASK> [ 3680.685544] dump_stack_lvl+0x77/0xb0 [ 3680.685549] __lock_acquire+0x93c/0x2310 [ 3680.685554] lock_acquire+0xce/0x2c0 [ 3680.685558] ? xen_pin_page+0x175/0x1d0 [ 3680.685562] _raw_spin_lock_nest_lock+0x2f/0x70 [ 3680.685568] ? xen_pin_page+0x175/0x1d0 [ 3680.685572] xen_pin_page+0x175/0x1d0 [ 3680.685578] ? __pfx_xen_pin_page+0x10/0x10 [ 3680.685582] __xen_pgd_walk+0x233/0x2c0 [ 3680.685588] ? stop_one_cpu+0x91/0x100 [ 3680.685592] __xen_pgd_pin+0x5d/0x250 [ 3680.685596] xen_mm_pin_all+0x70/0xa0 [ 3680.685600] xen_pv_pre_suspend+0xf/0x280 [ 3680.685607] xen_suspend+0x57/0x1a0 [ 3680.685611] multi_cpu_stop+0x6b/0x120 [ 3680.685615] ? update_cpumasks_hier+0x7c/0xa60 [ 3680.685620] ? __pfx_multi_cpu_stop+0x10/0x10 [ 3680.685625] cpu_stopper_thread+0x8c/0x140 [ 3680.685629] ? smpboot_thread_fn+0x20/0x1f0 [ 3680.685634] ? __pfx_smpboot_thread_fn+0x10/0x10 [ 3680.685638] smpboot_thread_fn+0xed/0x1f0 [ 3680.685642] kthread+0xde/0x110 [ 3680.685645] ? __pfx_kthread+0x10/0x10 [ 3680.685649] ret_from_fork+0x2f/0x50 [ 3680.685654] ? __pfx_kthread+0x10/0x10 [ 3680.685657] ret_from_fork_asm+0x1a/0x30 [ 3680.685662] </TASK> [ 3680.685267] xen:grant_table: Grant tables using version 1 layout [ 3680.685921] OOM killer enabled. [ 3680.685934] Restarting tasks ... done. Signed-off-by: Maksym Planeta <maksym@exostellar.io> Reviewed-by: Juergen Gross <jgross@suse.com> Message-ID: <20241204103516.3309112-1-maksym@exostellar.io> Signed-off-by: Juergen Gross <jgross@suse.com>
2025-01-19Merge tag 'x86_urgent_for_v6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Mark serialize() noinstr so that it can be used from instrumentation- free code - Make sure FRED's RSP0 MSR is synchronized with its corresponding per-CPU value in order to avoid double faults in hotplug scenarios - Disable EXECMEM_ROX on x86 for now because it didn't receive proper x86 maintainers review, went in and broke a bunch of things * tag 'x86_urgent_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/asm: Make serialize() always_inline x86/fred: Fix the FRED RSP0 MSR out of sync with its per-CPU cache x86: Disable EXECMEM_ROX support
2025-01-18riscv/mm/fault: add show_pte() before die()Yunhui Cui
When the kernel displays "Unable to handle kernel paging request at virtual address", we would like to confirm the status of the virtual address in the page table. So add show_pte() before die(). Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20240723021820.87718-1-cuiyunhui@bytedance.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18Merge patch series "riscv: Add support for xtheadvector"Palmer Dabbelt
Charlie Jenkins <charlie@rivosinc.com> says: xtheadvector is a custom extension that is based upon riscv vector version 0.7.1 [1]. All of the vector routines have been modified to support this alternative vector version based upon whether xtheadvector was determined to be supported at boot. vlenb is not supported on the existing xtheadvector hardware, so a devicetree property thead,vlenb is added to provide the vlenb to Linux. There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 that is used to request which thead vendor extensions are supported on the current platform. This allows future vendors to allocate hwprobe keys for their vendor. Support for xtheadvector is also added to the vector kselftests. [1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc * b4-shazam-merge: riscv: Add ghostwrite vulnerability selftests: riscv: Support xtheadvector in vector tests selftests: riscv: Fix vector tests riscv: hwprobe: Document thead vendor extensions and xtheadvector extension riscv: hwprobe: Add thead vendor extension probing riscv: vector: Support xtheadvector save/restore riscv: Add xtheadvector instruction definitions riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT RISC-V: define the elements of the VCSR vector CSR riscv: vector: Use vlenb from DT for thead riscv: Add thead and xtheadvector as a vendor extension riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree dt-bindings: cpus: add a thead vlen register length property dt-bindings: riscv: Add xtheadvector ISA extension description Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: Add ghostwrite vulnerabilityCharlie Jenkins
Follow the patterns of the other architectures that use GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite vulnerability and mitigation. The mitigation is to disable all vector which is accomplished by clearing the bit from the cpufeature field. Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, so the vulerability will only be mitigated on these CPUs. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-14-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: hwprobe: Add thead vendor extension probingCharlie Jenkins
Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-10-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: vector: Support xtheadvector save/restoreCharlie Jenkins
Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-9-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: Add xtheadvector instruction definitionsCharlie Jenkins
xtheadvector uses different encodings than standard vector for vsetvli and vector loads/stores. Write the instruction formats to be used in assembly code. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-8-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSATCharlie Jenkins
The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT has an encoding of 0x9. Co-developed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-7-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18RISC-V: define the elements of the VCSR vector CSRHeiko Stuebner
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: vector: Use vlenb from DT for theadCharlie Jenkins
If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-5-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: Add thead and xtheadvector as a vendor extensionCharlie Jenkins
Add support to the kernel for THead vendor extensions with the target of the new extension xtheadvector. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetreeCharlie Jenkins
The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18RISC-V: Mark riscv_v_init() as __initPalmer Dabbelt
This trips up with Xtheadvector enabled, but as far as I can tell it's just been an issue since the original patchset. Fixes: 7ca7a7b9b635 ("riscv: Add sysctl to set the default vector rule for new processes") Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20250115180251.31444-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2025-01-18ARC: migrate to the generic rule for built-in DTBMasahiro Yamada
Commit 654102df2ac2 ("kbuild: add generic support for built-in boot DTBs") introduced generic support for built-in DTBs. Select GENERIC_BUILTIN_DTB to use the generic rule. To keep consistency across architectures, this commit also renames CONFIG_ARC_BUILTIN_DTB_NAME to CONFIG_BUILTIN_DTB_NAME. Now, "nsim_700" is the default value for CONFIG_BUILTIN_DTB_NAME, rather than a fallback in case it is empty. Acked-by: Vineet Gupta <vgupta@kernel.org> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2025-01-17sparc/irq: Remove unneeded if check in sun4v_cookie_only_virqs()Thorsten Blum
Remove the unnecessary if check and return the result directly. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Andreas Larsson <andreas@gaisler.com> Link: https://lore.kernel.org/r/20250114202502.912690-1-thorsten.blum@linux.dev Signed-off-by: Andreas Larsson <andreas@gaisler.com>
2025-01-17sparc/irq: Use str_enabled_disabled() helper functionThorsten Blum
Remove hard-coded strings by using the str_enabled_disabled() helper function. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Andreas Larsson <andreas@gaisler.com> Link: https://lore.kernel.org/r/20250115090344.918290-2-thorsten.blum@linux.dev Signed-off-by: Andreas Larsson <andreas@gaisler.com>
2025-01-17sparc: replace zero-length array with flexible-array memberZhang Kunbo
The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last, which is beneficial to cultivate a high-quality code.[2] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Zhang Kunbo <zhangkunbo@huawei.com> Reviewed-by: Andreas Larsson <andreas@gaisler.com> Link: https://lore.kernel.org/r/20241218074439.3271397-1-zhangkunbo@huawei.com Signed-off-by: Andreas Larsson <andreas@gaisler.com>
2025-01-17sparc/irq: use seq_put_decimal_ull_width() for decimal valuesDavid Wang
Performance improvement for reading /proc/interrupts on arch sparc Signed-off-by: David Wang <00107082@163.com> Reviewed-by: Andreas Larsson <andreas@gaisler.com> Tested-by: Andreas Larsson <andreas@gaisler.com> Link: https://lore.kernel.org/r/20241108161123.9637-1-00107082@163.com Signed-off-by: Andreas Larsson <andreas@gaisler.com>
2025-01-17Merge branch 'for-next/mm' into for-next/coreWill Deacon
* for-next/mm: arm64: mm: Test for pmd_sect() in vmemmap_check_pmd() arm64/mm: Replace open encodings with PXD_TABLE_BIT arm64/mm: Rename pte_mkpresent() as pte_mkvalid() arm64: Kconfig: force ARM64_PAN=y when enabling TTBR0 sw PAN arm64/kvm: Avoid invalid physical addresses to signal owner updates arm64/kvm: Configure HYP TCR.PS/DS based on host stage1 arm64/mm: Override PARange for !LPA2 and use it consistently arm64/mm: Reduce PA space to 48 bits when LPA2 is not enabled
2025-01-17Merge branch 'for-next/misc' into for-next/coreWill Deacon
* for-next/misc: arm64: Remove duplicate included header arm64/Kconfig: Drop EXECMEM dependency from ARCH_WANTS_EXECMEM_LATE arm64: asm: Fix typo in pgtable.h arm64/mm: Ensure adequate HUGE_MAX_HSTATE arm64/mm: Replace open encodings with PXD_TABLE_BIT arm64/mm: Drop INIT_MM_CONTEXT()
2025-01-17Merge branch 'for-next/cpufeature' into for-next/coreWill Deacon
* for-next/cpufeature: kselftest/arm64: Add 2024 dpISA extensions to hwcap test KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1 arm64/hwcap: Describe 2024 dpISA extensions to userspace arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-12 arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu() arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09 arm64/sysreg: Get rid of CPACR_ELx SysregFields arm64/sysreg: Convert *_EL12 accessors to Mapping arm64/sysreg: Get rid of the TCR2_EL1x SysregFields arm64/sysreg: Allow a 'Mapping' descriptor for system registers arm64/cpufeature: Refactor conditional logic in init_cpu_ftr_reg() arm64: cpufeature: Add HAFT to cpucap_is_possible()
2025-01-17Merge tag 'at91-soc-6.14' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm Microchip AT91 SoC updates for v6.14 This update includes: - support for the SAMA7D65 SoC - support for automatic mode in the backup unit power switch, eliminating the need for software intervention when entering low power mode - a fix to release a device node reference in the failure path of the SoC driver initialization * tag 'at91-soc-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: add new SoC sama7d65 ARM: at91: pm: change BU Power Switch to automatic mode soc: atmel: fix device_node release in atmel_soc_device_init() Link: https://lore.kernel.org/r/20250107081424.758980-3-claudiu.beznea@tuxon.dev Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-17arm64/sysreg: Get rid of TRFCR_ELx SysregFieldsMarc Zyngier
There is no such thing as TRFCR_ELx in the architecture. What we have is TRFCR_EL1, for which TRFCR_EL12 is an accessor. Rename TRFCR_ELx_* to TRFCR_EL1_*, and fix the bit of code using these names. Similarly, TRFCR_EL12 is redefined as a mapping to TRFCR_EL1. Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/87cygsqgkh.wl-maz@kernel.org Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Brown <broonie@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com>
2025-01-17Merge branch kvm-arm64/misc-6.14 into kvmarm-master/nextMarc Zyngier
* kvm-arm64/misc-6.14: : . : Misc KVM/arm64 changes for 6.14 : : - Don't expose AArch32 EL0 capability when NV is enabled : : - Update documentation to reflect the full gamut of kvm-arm.mode : behaviours : : - Use the hypervisor VA bit width when dumping stacktraces : : - Decouple the hypervisor stack size from PAGE_SIZE, at least : on the surface... : : - Make use of str_enabled_disabled() when advertising GICv4.1 support : : - Explicitly handle BRBE traps as UNDEFINED : . KVM: arm64: Explicitly handle BRBE traps as UNDEFINED KVM: arm64: vgic: Use str_enabled_disabled() in vgic_v3_probe() arm64: kvm: Introduce nvhe stack size constants KVM: arm64: Fix nVHE stacktrace VA bits mask Documentation: Update the behaviour of "kvm-arm.mode" KVM: arm64: nv: Advertise the lack of AArch32 EL0 support Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-17Merge branch kvm-arm64/nv-resx-fixes-6.14 into kvmarm-master/nextMarc Zyngier
* kvm-arm64/nv-resx-fixes-6.14: : . : Fixes for NV sysreg accessors. From the cover letter: : : "Joey recently reported that some rather basic tests were failing on : NV, and managed to track it down to critical register fields (such as : HCR_EL2.E2H) not having their expect value. : : Further investigation has outlined a couple of critical issues: : : - Evaluating HCR_EL2.E2H must always be done with a sanitising : accessor, no ifs, no buts. Given that KVM assumes a fixed value for : this bit, we cannot leave it to the guest to mess with. : : - Resetting the sysreg file must result in the RESx bits taking : effect. Otherwise, we may end-up making the wrong decision (see : above), and we definitely expose invalid values to the guest. Note : that because we compute the RESx masks very late in the VM setup, we : need to apply these masks at that particular point as well. : [...]" : . KVM: arm64: nv: Apply RESx settings to sysreg reset values KVM: arm64: nv: Always evaluate HCR_EL2 using sanitising accessors Signed-off-by: Marc Zyngier <maz@kernel.org> # Conflicts: # arch/arm64/kvm/nested.c
2025-01-17Merge branch kvm-arm64/coresight-6.14 into kvmarm-master/nextMarc Zyngier
* kvm-arm64/coresight-6.14: : . : Trace filtering update from James Clark. From the cover letter: : : "The guest filtering rules from the Perf session are now honored for both : nVHE and VHE modes. This is done by either writing to TRFCR_EL12 at the : start of the Perf session and doing nothing else further, or caching the : guest value and writing it at guest switch for nVHE. In pKVM, trace is : now be disabled for both protected and unprotected guests." : . KVM: arm64: Fix selftests after sysreg field name update coresight: Pass guest TRFCR value to KVM KVM: arm64: Support trace filtering for guests KVM: arm64: coresight: Give TRBE enabled state to KVM coresight: trbe: Remove redundant disable call arm64/sysreg/tools: Move TRFCR definitions to sysreg tools: arm64: Update sysreg.h header files Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-17Merge branch kvm-arm64/pkvm-memshare-declutter into kvmarm-master/nextMarc Zyngier
* kvm-arm64/pkvm-memshare-declutter: : . : pKVM memory transition simplifications, courtesy of Quentin Perret. : : From the cover letter: : "Since its early days, pKVM has formalized memory 'transitions' (shares : and donations) using 'struct pkvm_mem_transition' and bunch of helpers : to manipulate it. The intention was for all transitions to use this : machinery to ensure we're checking things consistently. However, as : development progressed, it became clear that the rigidity of this model : made it really difficult to use in some use-cases which ended-up : side-stepping it entirely. That is the case for the : hyp_{un}pin_shared_mem() and host_{un}share_guest() paths upstream which : use lower level helpers directly, as well as for several other pKVM : features that should land upstream in the future (ex: when a guest : relinquishes a page during ballooning, when annotating a page that is : being DMA'd to, ...). On top of this, the pkvm_mem_transition machinery : requires a lot of boilerplate which makes the code hard to read, but : also adds layers of indirection that no compilers seems to see through, : hence leading to suboptimal generated code. : : Given all the above, this series removes the pkvm_mem_transition : machinery from mem_protect.c, and converts all its users to use : __*_{check,set}_page_state_range() low-level helpers directly." : . KVM: arm64: Drop pkvm_mem_transition for host/hyp donations KVM: arm64: Drop pkvm_mem_transition for host/hyp sharing KVM: arm64: Drop pkvm_mem_transition for FF-A KVM: arm64: Only apply PMCR_EL0.P to the guest range of counters KVM: arm64: nv: Reload PMU events upon MDCR_EL2.HPME change KVM: arm64: Use KVM_REQ_RELOAD_PMU to handle PMCR_EL0.E change KVM: arm64: Add unified helper for reprogramming counters by mask KVM: arm64: Always check the state from hyp_ack_unshare() KVM: arm64: Fix set_id_regs selftest for ASIDBITS becoming unwritable Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-17Merge branch kvm-arm64/nv-timers into kvmarm-master/nextMarc Zyngier
* kvm-arm64/nv-timers: : . : Nested Virt support for the EL2 timers. From the initial cover letter: : : "Here's another batch of NV-related patches, this time bringing in most : of the timer support for EL2 as well as nested guests. : : The code is pretty convoluted for a bunch of reasons: : : - FEAT_NV2 breaks the timer semantics by redirecting HW controls to : memory, meaning that a guest could setup a timer and never see it : firing until the next exit : : - We go try hard to reflect the timer state in memory, but that's not : great. : : - With FEAT_ECV, we can finally correctly emulate the virtual timer, : but this emulation is pretty costly : : - As a way to make things suck less, we handle timer reads as early as : possible, and only defer writes to the normal trap handling : : - Finally, some implementations are badly broken, and require some : hand-holding, irrespective of NV support. So we try and reuse the NV : infrastructure to make them usable. This could be further optimised, : but I'm running out of patience for this sort of HW. : : [...]" : . KVM: arm64: nv: Fix doc header layout for timers KVM: arm64: nv: Document EL2 timer API KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity KVM: arm64: nv: Sanitise CNTHCTL_EL2 KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT} KVM: arm64: Handle counter access early in non-HYP context KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor context KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in use KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state KVM: arm64: nv: Sync nested timer state with FEAT_NV2 KVM: arm64: nv: Add handling of EL2-specific timer registers Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-17riscv: dts: spacemit: move aliases to board dtsYixun Lan
aliases info should belong to board dts, instead of putting it at SoC dtsi file. Fixes: d8fe64691955 ("riscv: dts: add initial SpacemiT K1 SoC device tree") Link: https://lore.kernel.org/all/6a8bb914-858e-479d-a7d9-09e0ff688160@app.fastmail.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-17riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3Yixun Lan
Before pinctrl driver implemented, the uart0 controller reply on bootloader for setting correct pin mux and configurations. Now, let's add pinctrl property to uart0 of Bananapi-F3 board. Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-17riscv: defconfig: enable SpacemiT SoCYangyu Chen
Enable SpacemiT SoC config in defconfig to allow the default upstream kernel booting on Banana Pi BPI-F3 board. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Jesse Taube <jesse@rivosinc.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-17riscv: dts: spacemit: add Banana Pi BPI-F3 board device treeYangyu Chen
Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip [2]. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1] Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2] Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Jesse Taube <jesse@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-17riscv: dts: add initial SpacemiT K1 SoC device treeYangyu Chen
Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1]. Key features: - 4 cores per cluster, 2 clusters on chip - UART IP is Intel XScale UART Some key considerations: - ISA string is inferred from vendor documentation[2] - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3] - No coherent DMA on this board Inferred by taking vendor ethernet and MMC drivers to the mainline kernel. Without dma-noncoherent in soc node, the driver fails. - Add cache nodes K1 SoC has 128 sets of 32KiB L1 I/D Cache for each hart, and 512 sets of 512KiB L2 Cache for each cluster. Currently only support booting into console with only uart, other features will be added soon later. Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1] Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2] Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3] Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Jesse Taube <jesse@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-17riscv: add SpacemiT SoC family Kconfig supportYangyu Chen
The first SoC in the SpacemiT series is K1, which contains 8 RISC-V cores with RISC-V Vector v1.0 support. Link: https://www.spacemit.com/en/spacemit-key-stone-2/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-01-16Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.13-rc8). Conflicts: drivers/net/ethernet/realtek/r8169_main.c 1f691a1fc4be ("r8169: remove redundant hwmon support") 152d00a91396 ("r8169: simplify setting hwmon attribute visibility") https://lore.kernel.org/20250115122152.760b4e8d@canb.auug.org.au Adjacent changes: drivers/net/ethernet/broadcom/bnxt/bnxt.c 152f4da05aee ("bnxt_en: add support for rx-copybreak ethtool command") f0aa6a37a3db ("eth: bnxt: always recalculate features after XDP clearing, fix null-deref") drivers/net/ethernet/intel/ice/ice_type.h 50327223a8bb ("ice: add lock to protect low latency interface") dc26548d729e ("ice: Fix quad registers read on E825") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-01-16EDAC/cell: Remove powerpc Cell driverMichael Ellerman
This driver can no longer be built since support for IBM Cell Blades was removed, in particular PPC_CELL_COMMON. Remove the driver. [ bp: Remove EDAC_CELL from Cell's defconfig too. ] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20241218105523.416573-23-mpe@ellerman.id.au
2025-01-16Merge tag 'omap-for-v6.14/soc-signed' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/arm soc: omap: minor updates for v6.14 * tag 'omap-for-v6.14/soc-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap: ARM: omap1: Fix up the Retu IRQ on Nokia 770 ARM: omap2plus_defconfig: enable charger of TWL603X ARM: OMAP2+: Fix a typo Link: https://lore.kernel.org/r/7hikqqb41a.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16x86/asm: Make serialize() always_inlineJuergen Gross
In order to allow serialize() to be used from noinstr code, make it __always_inline. Fixes: 0ef8047b737d ("x86/static-call: provide a way to do very early static-call updates") Closes: https://lore.kernel.org/oe-kbuild-all/202412181756.aJvzih2K-lkp@intel.com/ Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20241218100918.22167-1-jgross@suse.com
2025-01-16Merge tag 'riscv-dt-for-v6.14' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt ~RISC-V~ StarFive Devicetrees for v6.14 Not so much RISC-V, but rather StarFive, this time around as there are only two changes: the Milk-V Mars and Pine64 Star64 boards get their usb0 interfaces moved from peripheral to host mode. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110-milkv-mars: enable usb0 host function riscv: dts: starfive: jh7110-pine64-star64: enable usb0 host function Link: https://lore.kernel.org/r/20250113-kennel-outplayed-21a52a654c36@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'mvebu-dt64-6.14-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.14 (part 1) Fix errors reported by dtbs_check for sata related nodes Fix cp1 comphy link on Marvell CN913x platforms * tag 'mvebu-dt64-6.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: drop additional phy-names for sata arm64: dts: marvell: only enable complete sata nodes arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy links Link: https://lore.kernel.org/r/87frlnygej.fsf@BLaptop.bootlin.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'qcom-arm64-for-6.14' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.14 This adds support for the new Snapdragon 8 Elite platform with MTP and QRD boards, QCS615 platform with the Ride board, QCS8300 platform with its Ride board, IPQ5424 platform with the RDP466 board, MSM8917 platform with Xiaomi Redmi 5A, and the SAR2130P platform with the Snapdragon AR2 Gen1 Smart Viewer Development Kit. On X Elite the HP Omnibook X laptop and the Snapdragon Devkit are added. The 8cx Gen3-based Huawaei Matebook E Go and Microsoft Windows Dev Kit 2023 are introduced. IPQ9574 gains PCIe and TRNG descriptions, together with a few other smaller improvements. TRNG is also enabled on the IPQ5332 platform. On MSM8994, Huawei Nexus 6P gains power and volume keys support. USB interrupts are corrected. On QCM6490 the FairPhone 5 gains camera EEPROM and Rb3Gen2 development kit gains description of the onboard LEDs. On QRB4210 RB2 support for HDMI audio playback is added. SA8775P gains missing clock controllers, CPUs are tied to PSCI power domains, DisplayPort is introduced and enabled on the Ride board. On SDM670 the GPU components are described and enabled for Google Pixel 3a, together with camera clock controller and flash LED. Xiaomi Mi Pad 5 Pro, on SM8250, gets WiFi and Bluetooth enabled. "global" IRQ for PCIe RC controllers are described on SM8550 and SM8650, to allow for hotplug events. Coresight support is added for SM8450, SM8650, X 1 Elite, QCS615, and QCS8300. The X Elite platform gains QUP power domains and OPPs, another PCIe controller, another UART, and its SDHCI controllers. The ASUS Vivobook S 15 gets GPU and lid switch enabled. Microsoft Surface Laptop 7 gains audio configuration, SD card reader support, and USB retimers. The Lenovo Yoga Slim 7x gets its LID switch described. Dell XPS 13 gains retimers described. The Lenovo Thinkpad T14s has additional USB ports enabled, as well as sound and fingerprint sensor. USB U1/U2 entry is disabled across a variety of platforms, to improve USB stability. sleep clock frequencies are reviewed and corrected for a variety of platforms, so is also various remoteproc mmio address ranges. * tag 'qcom-arm64-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (240 commits) arm64: dts: qcom: x1e80100-romulus: Update firmware nodes arm64: dts: qcom: msm8916-samsung-serranove: Add display panel arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes arm64: dts: qcom: Remove unused and undocumented properties arm64: dts: qcom: sdm450-lenovo-tbx605f: add DSI panel nodes arm64: dts: qcom: pmi8950: add LAB-IBB nodes arm64: dts: qcom: ipq5424: enable the download mode support arm64: dts: qcom: ipq5424: add scm node arm64: dts: qcom: sm8250: Fix interrupt types of camss interrupts arm64: dts: qcom: sdm845: Fix interrupt types of camss interrupts arm64: dts: qcom: sc8280xp: Fix interrupt type of camss interrupts arm64: dts: qcom: qcs8300-ride: Enable USB controllers arm64: dts: qcom: qcs8300: Add support for usb nodes arm64: dts: qcom: qcs8300: Add support for clock controllers arm64: dts: qcom: sm8450: Add coresight nodes arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions arm64: dts: qcom: qcs615-ride: Enable UFS node arm64: dts: qcom: qcs615: add UFS node arm64: dts: qcom: ipq5424: Add USB controller and phy nodes ... Link: https://lore.kernel.org/r/20250111181025.394631-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'qcom-arm32-for-6.14' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm32 DeviceTree updates for v6.14 Describe the interconnect paths for PCIe EP controllers on SDX55 and SDX65. Disable USB U1/U2 entry to improve USB stability on the same. * tag 'qcom-arm32-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: sdx55: Disable USB U1/U2 entry ARM: dts: qcom: sdx65: Disable USB U1/U2 entry ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect path ARM: dts: qcom: sdx65: Add PCIe EP interconnect path Link: https://lore.kernel.org/r/20250111171126.369502-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'v6.14-rockchip-dts64-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards rk3576-evb1, H96 Max V58 TV Box (rk3588), BigTreeTech CB2 (SoM + baseboard) and Pi2 (SBC), Firefly ITX-3588J (Core-3588J SoM), Orange Pi 5 Max. A interesting case is the Radxa E52C using a soc called rk3582. This is rk3588-variant where some cpu cores are disabled during production and the bootloader needs to read the available cores from efuses and adapt the DT it hands over to the kernel. New supported peripherals are just the naneng combophy + the usb controllers using them on the rk3576 as well as the arm,smmu attached to the PCI controller on rk3588. And finally there are of course a number of board-specific enablements and refinements (MCU on Qnap-TS433, USB3 on NanoPi R6C/R6S and Orange Pi 5+ etc. * tag 'v6.14-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (31 commits) arm64: dts: rockchip: add DTs for Firefly ITX-3588J and its Core-3588J SoM dt-bindings: arm: rockchip: Add Firefly ITX-3588J board arm64: dts: rockchip: Add Orange Pi 5 Max board dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Max arm64: dts: rockchip: refactor common rk3588-orangepi-5.dtsi arm64: dts: rockchip: add WLAN to rk3588-evb1 controller arm64: dts: rockchip: increase gmac rx_delay on rk3399-puma arm64: dts: rockchip: Delete redundant RK3328 GMAC stability fixes arm64: dts: rockchip: enable hdmi out audio on wolfvision pf5 arm64: dts: rockchip: fix num-channels property of wolfvision pf5 mic arm64: dts: rockchip: Enable the USB 3.0 port on NanoPi R6C/R6S arm64: dts: rockchip: Add FRAM MB85RS128TY to rk3568-mecsbc arm64: dts: rockchip: Remove unused i2c2 node from rk3568-mecsbc arm64: dts: rockchip: Fix PCIe3 handling for Edgeble-6TOPS Modules arm64: dts: rockchip: Add Radxa E52C dt-bindings: arm: rockchip: Add Radxa E52C arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2 dt-bindings: arm: rockchip: Add BigTreeTech CB2 and Pi2 arm64: dts: rockchip: Enable USB 3.0 ports on orangepi-5-plus arm64: dts: rockchip: Add H96 Max V58 TV Box based on RK3588 SoC ... Link: https://lore.kernel.org/r/2193001.3Lj2Plt8kZ@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'ti-k3-dt-for-v6.14' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt TI K3 device tree updates for v6.14 Generic Fixups/Cleanups: - Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties for ethernet phy - Clock description added to ICSS-G SoC Specific features and Fixes: - Duplicate GICR reg defines in am62x/am62ax - Mailbox nodes are enabled at board level bringing AM67/j722s/am62p to same behavior as other K3 SoCs. - Introduction of deep-sleep state defines for pinctrl header AM62Ax - Enable ti-sysc for wkup_uart0 AM64: - Switch ICSSG clock to core clock. J7200: - Disable SPI1 loopback default. J784s4: - Clock ID fix for McSPI instances - Use j7200-padconf compatibility for padconf to enable suspend-to-ram support. Board Specific: AM62 - phyboard - hdmi bridge regulator and using 16bit input for hdmi bridge, vcc-supply for i2c eeprom - SK - SoC wakeup using USB1, Add bootph property around cpsw mac syscon node, M4 mailbox node redefinition fixup. - BeaglePlay: Fix ethernet phy reset time AM64 - hummingboard-t: Convert PCIE/USB overlays to independent dts. j7200: - EVM: fix typo in overlay name. j721e: - EVM: overlay for pcie1 endpoint mode. j722s: - EVM: Add mcu_i2c0 support for expansion pins., Add USB0 DFU support, Enable PMIC - AM67a-beagley-ai: Add remote proc nodes j784s4: - AM69-SK/ j784s4-EVM - Mark PMIC regulators with bootph-all property to indicate ones that are needed through boot phases. - AM69-sk: PIC0 Endpoint mode overlay, USB Superspeed mode. * tag 'ti-k3-dt-for-v6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (31 commits) arm64: dts: ti: k3-am62a-wakeup: Configure ti-sysc for wkup_uart0 arm64: dts: ti: k3-j722s-evm: Enable PMIC arm64: dts: ti: k3-am69-sk: Add USB SuperSpeed support arm64: dts: ti: k3-am625-beagleplay: Fix DP83TD510E reset time arm64: dts: ti: k3-am642-hummingboard-t: Convert overlay to board dts arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode arm64: dts: ti: k3-am68-sk-base-board: Add overlay for PCIE1 Endpoint Mode arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE1 Endpoint Mode arm64: dts: ti: Makefile: Fix typo "k3-j7200-evm-pcie1-ep.dtbo" arm64: dts: ti: k3-j7200: Add node to disable loopback connection arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatible arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU boot arm64: dts: ti: k3-am62a: Remove duplicate GICR reg arm64: dts: ti: k3-am62: Remove duplicate GICR reg arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodes arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board level arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinition arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0 arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in cpsw_mac_syscon node arm64: dts: ti: Remove unused and undocumented "ti,(rx|tx)-fifo-depth" properties ... Link: https://lore.kernel.org/r/20250110210812.bdpypzvmg6s6sr5t@itinerary Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'tegra-for-6.14-arm64-dt' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree fixes for v6.14-rc1 These patches fix up an issue with the DMA support on one of the SPI controllers, as well as properly identify the SCE fabric and disable it to prevent accessing registers that may not be accessible to the CPU. Finally, the GIC's #address-cells property is set to 0 to fix a problem in the PCIe interrupt-map property. * tag 'tegra-for-6.14-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Fix Tegra234 PCIe interrupt-map arm64: tegra: Disable Tegra234 sce-fabric node arm64: tegra: Fix typo in Tegra234 dce-fabric compatible arm64: tegra: Fix DMA ID for SPI2 Link: https://lore.kernel.org/r/20250110185355.4143505-3-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'tegra-for-6.14-arm-dt' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt ARM: tegra: Device tree fixes for v6.14-rc1 This contains a fix that makes sure the power to the USB ports is maintained during boot. This helps with booting from USB storage. * tag 'tegra-for-6.14-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: nyan: Maintain power to USB ports on boot Link: https://lore.kernel.org/r/20250110185355.4143505-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'arm-soc/for-6.14/devicetree-arm64' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.14: - Dave adds the display pipeline DT nodes on BCM2712 (Raspberry Pi 5) - Rob removes some undocumented properties - Same ensures that the CFE stub area is reserved to allow secondary CPUs to be successfully brought up in Linux, also making sure that the address used in the spin table is also carved out. Finally he adds support for the Zyxel EX3510-B router using BCM4906 - Rosen converts the BCM4908 platforms to use the more flexible nvmem-layout representation * tag 'arm-soc/for-6.14/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: bcm4908: nvmem-layout conversion arm64: dts: broadcom: bcmbca: bcm4908: Add DT for Zyxel EX3510-B dt-bindings: arm64: bcmbca: Add Zyxel EX3510-B based on BCM4906 arm64: dts: broadcom: bcmbca: bcm4908: Protect cpu-release-addr arm64: dts: broadcom: bcmbca: bcm4908: Reserve CFE stub area arm64: dts: broadcom: Remove unused and undocumented properties arm64: dts: broadcom: Add DT for D-step version of BCM2712 arm64: dts: broadcom: Add display pipeline support to BCM2712 arm64: dts: broadcom: Add firmware clocks and power nodes to Pi5 DT Link: https://lore.kernel.org/r/20250109224756.3632025-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-01-16Merge tag 'arm-soc/for-6.14/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree updates for 6.14, please pull the following: - Rob removes some unused and undocumented properties pertaining to the SPI flash controller on Broadcom boards - Linus adds a number of BCM6846 peripherals: HWRNG, watchdog, GPIO, MDIO, LED controller, DMA and then proceeds with adding support for the GEnexsis XG6846B PON router - Rosen sets the MAC address NVMEM reference on the Meraki MR26 platform * tag 'arm-soc/for-6.14/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: meraki-mr26: set mac address for gmac0 ARM: dts: broadcom: Add Genexis XG6846B DTS file dt-bindings: arm: bcmbca: Add Genexis XG6846B dt-bindings: vendor-prefixes: Add Genexis ARM: dts: bcm6846: Add ARM PL081 DMA block ARM: dts: bcm6846: Add LED controller ARM: dts: bcm6846: Add MDIO control block ARM: dts: bcm6846: Add GPIO blocks ARM: dts: bcm6846: Enable watchdog ARM: dts: bcm6846: Add iproc rng arm: dts: broadcom: Remove unused and undocumented properties Link: https://lore.kernel.org/r/20250109224756.3632025-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit (git 2.34.1) at 2025-10-01 20:13:38 +0000