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2020-05-21Merge tag 'socfpga_dts_update_for_v5.8' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.8 - Leave the FPGA bridges disabled in base dtsi - Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi * tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges ARM: dts: socfgpa: set bridges status to disabled Link: https://lore.kernel.org/r/20200515193029.11318-2-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'sunxi-dt-for-5.8-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual number of patches to improve the Allwinner Device Tree support, including: - Support for the IOMMU on the H6 - Support for cpufreq / thermal throttling on the H6 - Support for the mailbox on the A64, A83t, H3, H5 and H6 - New boards: A20-OLinuXino-LIME-eMMC * tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (23 commits) arm64: dts: allwinner: h6: Add IOMMU arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6 arm64: dts: allwinner: h6: add voltage range to OPP table arm64: dts: allwinner: sun50i-a64: Add missing address/size-cells arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64 arm64: dts: allwinner: Sort Pine H64 device-tree nodes arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3 arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1 arm64: dts: allwinner: h6: Add CPU Operating Performance Points table arm64: dts: allwinner: h6: Add thermal trip points/cooling map arm64: dts: allwinner: h6: Add clock to CPU cores arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo module arm64: dts: allwinner: h6: orangepi: Disable OTG mode arm64: dts: allwinner: h6: orangepi: Add gpio power supply ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity arm64: dts: allwinner: h6: Add msgbox node arm64: dts: allwinner: a64: Add msgbox node ARM: dts: sunxi: h3/h5: Add msgbox node ARM: dts: sunxi: a83t: Add msgbox node ARM: dts: sun8i-h3: add opp table for mali gpu ... Link: https://lore.kernel.org/r/cfa66bd9-f74c-4614-9ea5-9ef8546cc571.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'tegra-for-5.8-arm-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.8-rc1 This contains a bit of cleanup and CPU frequency scaling support for the Tegra30 Beaver board. * tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: dts: tegra30: beaver: Add CPU Operating Performance Points ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS ARM: tegra: Kill off "simple-panel" compatibles Link: https://lore.kernel.org/r/20200515145311.1580134-11-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21RISC-V: gp_in_global needs register keywordPalmer Dabbelt
The Intel kernel build robot recently pointed out that I missed the register keyword on this one when I refactored the code to remove local register variables (which aren't supported by LLVM). GCC's manual indicates that global register variables must have the register keyword, As far as I can tell lacking the register keyword causes GCC to ignore the __asm__ and treat this as a regular variable, but I'm not sure how that didn't show up as some sort of failure. Fixes: 52e7c52d2ded ("RISC-V: Stop relying on GCC's register allocator's hueristics") Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-21exec: Remove recursion from search_binary_handlerEric W. Biederman
Recursion in kernel code is generally a bad idea as it can overflow the kernel stack. Recursion in exec also hides that the code is looping and that the loop changes bprm->file. Instead of recursing in search_binary_handler have the methods that would recurse set bprm->interpreter and return 0. Modify exec_binprm to loop when bprm->interpreter is set. Consolidate all of the reassignments of bprm->file in that loop to make it clear what is going on. The structure of the new loop in exec_binprm is that all errors return immediately, while successful completion (ret == 0 && !bprm->interpreter) just breaks out of the loop and runs what exec_bprm has always run upon successful completion. Fail if the an interpreter is being call after execfd has been set. The code has never properly handled an interpreter being called with execfd being set and with reassignments of bprm->file and the assignment of bprm->executable in generic code it has finally become possible to test and fail when if this problematic condition happens. With the reassignments of bprm->file and the assignment of bprm->executable moved into the generic code add a test to see if bprm->executable is being reassigned. In search_binary_handler remove the test for !bprm->file. With all reassignments of bprm->file moved to exec_binprm bprm->file can never be NULL in search_binary_handler. Link: https://lkml.kernel.org/r/87sgfwyd84.fsf_-_@x220.int.ebiederm.org Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2020-05-21exec: Move the call of prepare_binprm into search_binary_handlerEric W. Biederman
The code in prepare_binary_handler needs to be run every time search_binary_handler is called so move the call into search_binary_handler itself to make the code simpler and easier to understand. Link: https://lkml.kernel.org/r/87d070zrvx.fsf_-_@x220.int.ebiederm.org Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: James Morris <jamorris@linux.microsoft.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2020-05-21arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 contextAnshuman Khandual
ID_MMFR4_EL1 has been missing in the CPU context (i.e cpuinfo_arm64). This just adds the register along with other required changes. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-18-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 registerAnshuman Khandual
Enable the following features bits in ID_AA64PFR1 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-12-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 registerAnshuman Khandual
Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-11-git-send-email-anshuman.khandual@arm.com [will: Make SEL2 a NONSTRICT feature per Suzuki] Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 registerAnshuman Khandual
Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-10-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add remaining feature bits in ID_MMFR4 registerAnshuman Khandual
Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX, SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-9-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add remaining feature bits in ID_PFR0 registerAnshuman Khandual
Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487F.a specification. Except RAS and AMU, all other feature bits are now enabled. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-8-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Introduce ID_MMFR5 CPU registerAnshuman Khandual
This adds basic building blocks required for ID_MMFR5 CPU register which provides information about the implemented memory model and memory management support in AArch32 state. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-7-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Introduce ID_DFR1 CPU registerAnshuman Khandual
This adds basic building blocks required for ID_DFR1 CPU register which provides top level information about the debug system in AArch32 state. We hide the register from KVM guests, as we don't emulate the 'MTPMU' feature. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Reviewed-by : Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-6-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Introduce ID_PFR2 CPU registerAnshuman Khandual
This adds basic building blocks required for ID_PFR2 CPU register which provides information about the AArch32 programmers model which must be interpreted along with ID_PFR0 and ID_PFR1 CPU registers. This is added per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-5-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0Anshuman Khandual
Double lock feature can have the following possible values. 0b0000 - Double lock implemented 0b1111 - Double lock not implemented But in case of a conflict the safe value should be 0b1111. Hence this must be a signed feature instead. Also change FTR_EXACT to FTR_LOWER_SAFE. While here, fix the erroneous bit width value from 28 to 4. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-4-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 registerAnshuman Khandual
ID_DFR0 based TraceFilt feature should not be exposed to guests. Hence lets drop it. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-3-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 registerAnshuman Khandual
ID_ISAR0[31..28] bits are RES0 in ARMv8, Reserved/UNK in ARMv7. Currently these bits get exposed through generic_id_ftr32[] which is not desirable. Hence define an explicit ftr_id_isar0[] array for ID_ISAR0 register where those bits can be hidden. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-22powerpc/64s: Disable STRICT_KERNEL_RWXMichael Ellerman
Several strange crashes have been eventually traced back to STRICT_KERNEL_RWX and its interaction with code patching. Various paths in our ftrace, kprobes and other patching code need to be hardened against patching failures, otherwise we can end up running with partially/incorrectly patched ftrace paths, kprobes or jump labels, which can then cause strange crashes. Although fixes for those are in development, they're not -rc material. There also seem to be problems with the underlying strict RWX logic, which needs further debugging. So for now disable STRICT_KERNEL_RWX on 64-bit to prevent people from enabling the option and tripping over the bugs. Fixes: 1e0fc9d1eb2b ("powerpc/Kconfig: Enable STRICT_KERNEL_RWX for some configs") Cc: stable@vger.kernel.org # v4.13+ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200520133605.972649-1-mpe@ellerman.id.au
2020-05-21Merge tag 'ti-k3-dt-for-v5.8' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC DT updates for v5.8 - Add DSS support for both AM65x and J721e - Add watchdog support for J721e - Add EHRPWM support for AM65x - Add Thermal support for AM65x * tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries arm64: dts: ti: k3-am65-main: Add ehrpwm nodes arm64: dts: ti: am654: Add thermal zones arm64: dts: ti: am65-wakeup: Add VTM node arm64: dts: ti: k3-j721e-common-proc-board: add assigned clks for DSS arm64: dts: ti: k3-j721e-main: Add DSS node arm64: dts: ti: am654: Add DSS node Link: https://lore.kernel.org/r/7484d3c9-323f-36a3-f0df-1287586f356d@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'renesas-arm-dt-for-v5.8-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.8 (take two) - Initial support for the Renesas RZ/G1H SoC on the iWave RainboW Qseven SOM (G21M) and board (G21D), - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the Silicon Linux EK874 RZ/G2E evaluation kit. * tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1 ARM: dts: r8a7742: Add GPIO nodes ARM: dts: r8a7742: Add [H]SCIF{A|B} support ARM: dts: r8a7742: Add IRQC support ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM ARM: dts: r8a7742: Initial SoC device tree clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'stm32-dt-for-v5.8-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v5.8, round 1 Highlights: ---------- MCU part: -fix a typo for DAC io-channel-cells on f429 and h743 MPU part: -Generic: -Bump tp PSCI 1.0 -Fix a typo for DAC io-channel-cells -Add M4 pdds for deep sleep mode -Add I2C fatmode plus support -Add new Octavio lxa-mc1 board based on OSDMP15x SiP -Add new Stinger96 board support. It is a 96Boards IoT Extended board based on stm32mp157a SoC. Some figures: 256MB DDR, 125MB and flash, Onboard BG96 modem... -Add IoT Box board support based on stinger96 board + Wifi/BT, CCS811 VOC sensor, 2 digitals microphones ... -DH: -Adapt dhcom-som and dhcom-pdk2 dts(i) files to STM32MP15 SoC diversity -Add GPIO led and GPIO keys support on PDK2 board -AV96: -Major rework to support official avenger96 board based on DHCOR SOM. -Prototype board is no more supported * tag 'stm32-dt-for-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (58 commits) ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2 ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2 ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2 ARM: dts: stm32: Add IoT Box board support dt-bindings: arm: stm32: Document IoT Box compatible ARM: dts: stm32: Add Stinger96 board support dt-bindings: arm: stm32: Document Stinger96 compatible ARM: dts: stm32: Add missing pinctrl entries for STM32MP15 dt-bindings: Add vendor prefix for Shiratech Solutions ARM: dts: stm32: Add bindings for SPI2 on AV96 ARM: dts: stm32: Add alternate pinmux for SPI2 pins ARM: dts: stm32: Add bindings for ADC on AV96 ARM: dts: stm32: Add alternate pinmux for ADC pins ARM: dts: stm32: Add bindings for FDCAN2 on AV96 ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins ARM: dts: stm32: Add bindings for FDCAN1 on AV96 ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins ARM: dts: stm32: Repair I2C2 operation on AV96 ARM: dts: stm32: Add alternate pinmux for I2C2 pins ... Link: https://lore.kernel.org/r/19160355-364d-170c-7ae2-5ba7f714103f@st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'samsung-dt-5.8' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.8 1. Add DTS for Exynos4210-based Samsung Galaxy S2 (GT-I9100) mobile phone, 2. Enable WiFi and Bluetooth in multiple boards, 3. Add new features to S5Pv210-based Aries family of mobile phones (e.g. Samsung Galaxy S): necessary configuration for suspend, audio support, USB mux, touch keys, panel, i2c-gpio adapters, FM radio, ADC, 4. Many minor fixes (e.g. GPIO polarity, interrupts). * tag 'samsung-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (29 commits) ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boards ARM: dts: s5pv210: Correct FIMC definitions ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boards ARM: dts: s5pv210: Enable ADC on Aries boards ARM: dts: s5pv210: Add an ADC node ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards ARM: dts: s5pv210: Add si470x FM radio to Galaxy S ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boards ARM: dts: s5pv210: Add panel support to Aries boards ARM: dts: s5pv210: Add touchkey support to Aries boards ARM: dts: s5pv210: Add FSA9480 support to Aries boards ARM: dts: s5pv210: Add WM8994 support to Aries boards ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for Aries ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on Aries ARM: dts: s5pv210: Correct gpi pinctrl node name ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy S ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4G ARM: dts: s5pv210: Add helper define for sleep gpio config ARM: dts: exynos: Enable WLAN support for the UniversalC210 board ARM: dts: exynos: Enable WLAN support for the Rinato board ... Link: https://lore.kernel.org/r/20200512122922.5700-2-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21arm64: mm: Add asid_gen_match() helperJean-Philippe Brucker
Add a macro to check if an ASID is from the current generation, since a subsequent patch will introduce a third user for this test. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20200519175502.2504091-6-jean-philippe@linaro.org Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21Merge tag 'arm-soc/for-5.8/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for v5.8, please pull the following: - Nicolas updates the Raspberry Pi 4 board DTS to include the GPIO controlling power to the SD card, adds support for the vmmc regulator for the emmc2 controller and finally updates the power management provider for V3D to use the firmware to solve instabilities. * tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm283x: Use firmware PM driver for V3D ARM: dts: bcm2711: Add vmmc regulator in emmc2 ARM: dts: bcm2711: Update expgpio's GPIO labels Link: https://lore.kernel.org/r/20200511210522.28243-2-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into arm/dt ARM64: DT: Hisilicon SoCs DT updates for 5.8 - Add pinconf for spi2 and spi3 nodes and increase the drive strength to achieve the max speed for the Hikey960 board - Add CTI nodes for the Hikey620 board * tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi6220: Add CTI options arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf Link: https://lore.kernel.org/r/5EBE430E.6090508@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21arm64: vdso: Fix CFI directives in sigreturn trampolineWill Deacon
Daniel reports that the .cfi_startproc is misplaced for the sigreturn trampoline, which causes LLVM's unwinder to misbehave: | I run into this with LLVM’s unwinder. | This combination was always broken. This prompted Dave to question our use of CFI directives more generally, and I ended up going down a rabbit hole trying to figure out how this very poorly documented stuff gets used. Move the CFI directives so that the "mysterious NOP" is included in the .cfi_{start,end}proc block and add a bunch of comments so that I can save myself another headache in future. Cc: Tamas Zsoldos <tamas.zsoldos@arm.com> Reported-by: Dave Martin <dave.martin@arm.com> Reported-by: Daniel Kiss <daniel.kiss@arm.com> Tested-by: Daniel Kiss <daniel.kiss@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21arm64: vdso: Don't prefix sigreturn trampoline with a BTI C instructionWill Deacon
For better or worse, GDB relies on the exact instruction sequence in the VDSO sigreturn trampoline in order to unwind from signals correctly. Commit c91db232da48 ("arm64: vdso: Convert to modern assembler annotations") unfortunately added a BTI C instruction to the start of __kernel_rt_sigreturn, which breaks this check. Thankfully, it's also not required, since the trampoline is called from a RET instruction when returning from the signal handler Remove the unnecessary BTI C instruction from __kernel_rt_sigreturn, and do the same for the 32-bit VDSO as well for good measure. Cc: Daniel Kiss <daniel.kiss@arm.com> Cc: Tamas Zsoldos <tamas.zsoldos@arm.com> Reviewed-by: Dave Martin <dave.martin@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Fixes: c91db232da48 ("arm64: vdso: Convert to modern assembler annotations") Signed-off-by: Will Deacon <will@kernel.org>
2020-05-21Merge tag 'realtek-dt-for-5.8' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt Realtek Arm based SoC DT for v5.8 Add RTD1195, RTD1395 and RTD1619 SoCs as well as Xnano X5 TV box. Clean up memory nodes and /soc ranges. Factor out r-bus and partition it into CRT, Iso, Misc, SB2 and SCPU Wrapper blocks. * tag 'realtek-dt-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: (35 commits) dt-bindings: reset: rtd1295: Add SB2 reset arm64: dts: realtek: rtd16xx: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd139x: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd129x: Add SB2 and SCPU Wrapper syscon nodes ARM: dts: rtd1195: Add SB2 and SCPU Wrapper syscon nodes arm64: dts: realtek: rtd16xx: Add CRT syscon node ARM: dts: rtd1195: Add UART resets ARM: dts: rtd1195: Add reset nodes dt-bindings: reset: Add Realtek RTD1195 ARM: dts: rtd1195: Add CRT syscon node arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon arm64: dts: realtek: rtd129x: Introduce CRT, iso and misc syscon ARM: dts: rtd1195: Introduce iso and misc syscon arm64: dts: realtek: rtd1295: Add Xnano X5 dt-bindings: arm: realtek: Add Xnano X5 dt-bindings: vendor-prefixes: Add Xnano arm64: dts: realtek: rtd16xx: Add memory reservations arm64: dts: realtek: rtd16xx: Carve out boot ROM from memory arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB ... Link: https://lore.kernel.org/r/20200510232158.18477-2-afaerber@suse.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'aspeed-5.8-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dt ASPEED device tree updates for 5.8 New machines: - YADRO's ast2500 OpenPower P9 Nicole BMC - Facebook's ast2500 x86 Yosemite V2 BMC The AST2600 machines Rainier and Tacoma were fleshed out. Machines have started describing the GPIO names as userspace attempts to use the GPIO chardev API. * tag 'aspeed-5.8-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: (32 commits) ARM: dts: aspeed: Change KCS nodes to v2 binding ARM: dts: Aspeed: AST2600: Add XDMA PCI-E root control reset ARM: dts: aspeed: ast2600: Add XDMA Engine ARM: dts: aspeed: ast2500: Add XDMA Engine ARM: dts: aspeed: Adding Facebook Yosemite V2 BMC ARM: dts: aspeed: Add YADRO Nicole BMC ARM: dts: aspeed: mihawk: add aliases for i2c ARM: dts: aspeed: tacoma: Add TPM ARM: dts: aspeed: tacoma: Enable the second VUART ARM: dts: aspeed: tacoma: Add iio-hwmon nodes for IIO devices ARM: dts: aspeed: rainier: Add VGA reserved memory region ARM: dts: aspeed: rainier: Add gpio line names ARM: dts: aspeed: tacoma: Add gpio line names ARM: dts: aspeed: zaius: Add gpio line names ARM: dts: aspeed: romulus: Add gpio line names ARM: dts: aspeed: witherspoon: Add gpio line names ARM: dts: aspeed: ast2600: Set arch timer always-on ARM: dts: aspeed: tacoma: Add GPIOs for FSI ARM: dts: aspeed: mihawk: Change the name of leds ARM: dts: aspeed: rainier: Remove regulators ... Link: https://lore.kernel.org/r/CACPK8Xd-=XFREvvS-mK_ECyn14y0GPAMyy5BpEEUYfaw4jAgsw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'omap-for-v5.8/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt DTS changes for omaps for v5.8 merge window We add support for beaglebone-ai board that's am5729 based devices. Then we have a series changes to configure more hardware acceletators found on omap variants. With the recent ti-sysc related changes, we can now better configure the accelerators with help of the clock framework and reset driver. So with a series of changes from Suman Anna and Tero Kristo, let's configure IPUs and DSPs for dra7 devices like beagle-x15. And let's also configure the missing crypto accelerators for omap5 as those have been missing. Note that there are still some pending driver related patches to use IPU and DSP related features with mainline kernel, but those are independent of the devicetree changes. Then there is a display related change for am57xx-idk for tc358778 bridge, and a change to configure the missing clock source for some PWM timers. * tag 'omap-for-v5.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits) ARM: OMAP5: Make L4SEC clock domain SWSUP only ARM: OMAP4: Make L4SEC clock domain SWSUP only ARM: dts: omap5: add DES crypto accelerator node ARM: dts: omap5: add SHA crypto accelerator node ARM: dts: omap5: add aes2 entry ARM: dts: omap5: add aes1 entry ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files ARM: dts: DRA72x: Add aliases for rproc nodes ARM: dts: DRA74x: Add aliases for rproc nodes ... Link: https://lore.kernel.org/r/pull-1588873628-477615@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'renesas-arm-dt-for-v5.8-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.8 - USB, UART, PWM, and PCIe support for R-Car M3-W+, - PWM (16-bit Timer Pulse Unit and PWM Timers) support for R-Car M2-W, - Minor fixes and cleanups. * tag 'renesas-arm-dt-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Fix IOMMU device node names ARM: dts: renesas: Fix IOMMU device node names ARM: dts: shmobile: Update CMT1 compatible values ARM: dts: r8a7791: Add PWM device nodes ARM: dts: r8a7791: Add TPU device node arm64: dts: renesas: r8a77961: Add PCIe device nodes arm64: dts: renesas: r8a77961: Add PWM device nodes arm64: dts: renesas: r8a77961: Add SCIF and HSCIF nodes arm64: dts: renesas: r8a77961: Add USB3.0 device nodes arm64: dts: renesas: r8a77961: Add USB2.0 device nodes Link: https://lore.kernel.org/r/20200430084849.1457-3-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'versatile-dts-v5.8-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt Versatile DTS updates for the v5.8 kernel: Create a new device tree for the Integrator/AP with the IM-PD1 expansion module fitted in the first slot. If we want to augment the slot where it is sitting, we can alter the device tree or make the bootloader do so. * tag 'versatile-dts-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: dts: Add devicetree for Integrator/AP with IM-PD1 Link: https://lore.kernel.org/r/CACRpkdZ-28o+pPdP7i_fc+7g4ndPWf+SWTsjnhFEegTggiXVSg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21Merge tag 'sti-dt-for-v5.8-round1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into arm/dt STi DT fixes: - Remove duplicated rng node in stih407-family.dtsi - Fix complain about IRQ_TYPE_NONE usage in stih418.dtsi * tag 'sti-dt-for-v5.8-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: dts: arm: stih407-family: remove duplicated rng nodes dts: arm: stih418: Fix complain about IRQ_TYPE_NONE usage Link: https://lore.kernel.org/r/4b0c02e7-a247-50c0-d729-88d16b9dd7fd@st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21arm64: dts: Add SC9863A emmc and sd card nodesChunyan Zhang
Add emmc and sd card devicetree nodes for SC9863A. Link: https://lore.kernel.org/r/20200414101636.24503-3-zhang.lyra@gmail.com Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21arm64: dts: Add SC9863A clock nodesChunyan Zhang
add clock devicetree nodes for SC9863A. Link: https://lore.kernel.org/r/20200414101636.24503-2-zhang.lyra@gmail.com Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21arm64: dts: mt6358: add PMIC MT6358 related nodesHsin-Hsiung Wang
add PMIC MT6358 related nodes which is for MT8183 platform Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1587438012-24832-7-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-21mips: MAAR: Use more precise address maskSerge Semin
Indeed according to the MIPS32 Privileged Resource Architecgture the MAAR pair register address field either takes [12:31] bits for non-XPA systems and [12:55] otherwise. In any case the current address mask is just wrong for 64-bit and 32-bits XPA chips. So lets extend it to 59-bits of physical address value. This shall cover the 64-bits architecture and systems with XPA enabled, and won't cause any problem for non-XPA 32-bit systems, since address values exceeding the architecture specific MAAR mask will be just truncated with setting zeros in the unsupported upper bits. Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21MIPS: SGI-IP27: Remove not used definition TICK_SIZE in ip27-timer.cTiezhu Yang
After commit f5ff0a280201 ("[MIPS] Use generic NTP code for all MIPS platforms"), TICK_SIZE is not used in ip27-timer.c for many years, remove it. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21arm64: dts: rockchip: fix pinctrl-names for gpio-leds node on rk3326-odroid-go2Johan Jonker
The 'pinctrl-names' property should contain a list of names to the assigned states. The value 'led_pins' in the gpio-leds node on rk3326-odroid-go2 is not a state that is normally used, so change it the common name 'default'. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200519111444.2208-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-20ARM: dts: bcm: HR2: Fix PPI interrupt typesHamish Martin
These error messages are output when booting on a BCM HR2 system: GIC: PPI11 is secure or misconfigured GIC: PPI13 is secure or misconfigured Per ARM documentation these interrupts are triggered on a rising edge. See ARM Cortex A-9 MPCore Technical Reference Manual, Revision r4p1, Section 3.3.8 Interrupt Configuration Registers. The same issue was resolved for NSP systems in commit 5f1aa51c7a1e ("ARM: dts: NSP: Fix PPI interrupt types"). Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file") Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-05-20ARM: dts: bcm2835-rpi-zero-w: Fix led polarityVincent Stehlé
The status "ACT" led on the Raspberry Pi Zero W is on when GPIO 47 is low. This has been verified on a board and somewhat confirmed by both the GPIO name ("STATUS_LED_N") and the reduced schematics [1]. [1]: https://www.raspberrypi.org/documentation/hardware/raspberrypi/schematics/rpi_SCH_ZeroW_1p1_reduced.pdf Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W") Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-05-20riscv: Fix print_vm_layout build error if NOMMUKefeng Wang
arch/riscv/mm/init.c: In function ‘print_vm_layout’: arch/riscv/mm/init.c:68:37: error: ‘FIXADDR_START’ undeclared (first use in this function); arch/riscv/mm/init.c:69:20: error: ‘FIXADDR_TOP’ undeclared arch/riscv/mm/init.c:70:37: error: ‘PCI_IO_START’ undeclared arch/riscv/mm/init.c:71:20: error: ‘PCI_IO_END’ undeclared arch/riscv/mm/init.c:72:38: error: ‘VMEMMAP_START’ undeclared arch/riscv/mm/init.c:73:20: error: ‘VMEMMAP_END’ undeclared (first use in this function); Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-20riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structureYash Shah
Implement cache_get_priv_group() that will make use of a generic ops structure to return a private attribute group for custom cache info. Using riscv_set_cacheinfo_ops() users can hook their own custom function to return the private attribute group for cacheinfo. In future we can add more ops to this generic ops structure for SOC specific cacheinfo. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-20arm64: dts: meson-g12b-gtking-pro: add initial device-treeChristian Hewitt
The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference board with an S922X chip. - 4GB LPDDR4 RAM - 64GB eMMC storage - 10/100/1000 Base-T Ethernet - AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1) - HDMI 2.1 video - Analogue audio output - 1x RS232 port - 2x USB 2.0 port - 2x USB 3.0 ports - IR receiver - 1x micro SD card slot - 1x Power on/off button Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200520014329.12469-6-christianshewitt@gmail.com
2020-05-20arm64: dts: meson-g12b-gtking: add initial device-treeChristian Hewitt
The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference board with an S922X chip. - 4GB LPDDR4 RAM - 64GB eMMC storage - 10/100/1000 Base-T Ethernet - AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1) - HDMI 2.1 video - S/PDIF optical output - Analogue audio output - 1x USB 2.0 port - 2x USB 3.0 ports - IR receiver - 1x micro SD card slot Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200520014329.12469-4-christianshewitt@gmail.com
2020-05-20arm64: dts: meson: convert ugoos-am6 to common w400 dtsiChristian Hewitt
Convert the Ugoos AM6 dts into meson-g12b-w400.dtsi, and then create a new AM6 dts that references it. This is in preparation for several new G12B devices that will share the common w400 dtsi. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200520014329.12469-2-christianshewitt@gmail.com
2020-05-20Merge tag 'for-linus-5.7-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml Pull UML fixes from Richard Weinberger: - Two missing includes which caused build issues on recent systems - Correctly set TRANS_GRE_LEN in our vector network driver * tag 'for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml: um: Fix typo in vector driver transport option definition um: syscall.c: include <asm/unistd.h> um: Fix xor.h include
2020-05-20firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x insteadSudeep Holla
Instead of maintaining 2 sets of enums/macros for tracking SMCCC version, let us drop smccc_version enum and use ARM_SMCCC_VERSION_1_x directly instead. This is in preparation to drop smccc_version here and move it separately under drivers/firmware/smccc. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Steven Price <steven.price@arm.com> Reviewed-by: Etienne Carriere <etienne.carriere@st.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20200518091222.27467-5-sudeep.holla@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-05-20arm64/cpufeature: Drop open encodings while extracting parangeAnshuman Khandual
Currently there are multiple instances of parange feature width mask open encodings while fetching it's value. Even the width mask value (0x7) itself is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() which can extract given standard feature (4 bits width i.e 0xf mask) field. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/1589360614-1164-1-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-20 19:12:56 +0000