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2024-04-29x86/mm: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. [ dhansen: vertically align 0's in invlpg_miss_ids[] ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181518.41946-1-tony.luck%40intel.com
2024-04-29x86/tsc_msr: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181518.41927-1-tony.luck%40intel.com
2024-04-29x86/tsc: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181517.41907-1-tony.luck%40intel.com
2024-04-29x86/cpu: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. [ dhansen: vertically align macro and remove stray subject / ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181516.41887-1-tony.luck%40intel.com
2024-04-29x86/resctrl: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. [ bp: Squash two resctrl patches into one. ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181514.41848-1-tony.luck%40intel.com
2024-04-29x86/microcode/intel: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181513.41829-1-tony.luck%40intel.com
2024-04-29x86/mce: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* mce patches into one, fold in fix: https://lore.kernel.org/r/20240429022051.63360-1-tony.luck@intel.com ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181511.41772-1-tony.luck%40intel.com
2024-04-29x86/cpu: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181511.41753-1-tony.luck%40intel.com
2024-04-29x86/cpu/intel_epb: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181510.41733-1-tony.luck%40intel.com
2024-04-29x86/aperfmperf: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181505.41654-1-tony.luck%40intel.com
2024-04-29x86/apic: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181504.41634-1-tony.luck%40intel.com
2024-04-29perf/x86/msr: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181503.41614-1-tony.luck%40intel.com
2024-04-29perf/x86/intel/uncore: Switch to new Intel CPU model definesTony Luck
New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* uncore patches into one. ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/all/20240424181501.41557-1-tony.luck%40intel.com
2024-04-29Merge tag 'samsung-dt-6.10' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM changes for v6.10 1. Few cleanups of deprecated properties and node names pointed out by bindings newly converted to DT schema. 2. Fix S5PV210 NAND node size-cells, pointed out by DT schema. 3. Add FIFO depth to each SPI node so we can avoid matching this through DTS alias. Difference SPI instances on given SoC have different FIFO depths. 4. Fix Exynos4212 Galaxy Tab3 usable memory, because stock bootloader is not telling us truth. * tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos4212-tab3: limit usable memory range ARM: dts: samsung: s5pv210: specify the SPI FIFO depth ARM: dts: samsung: exynos5420: specify the SPI FIFO depth ARM: dts: samsung: exynos5250: specify the SPI FIFO depth ARM: dts: samsung: exynos4: specify the SPI FIFO depth ARM: dts: samsung: exynos3250: specify the SPI FIFO depth ARM: dts: samsung: s5pv210: correct onenand size-cells ARM: dts: samsung: s5pv210: align onenand node name with bindings ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs ARM: dts: samsung: smdk4412: align keypad node names with dtschema ARM: dts: samsung: smdk4412: fix keypad no-autorepeat ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat ARM: dts: samsung: smdkv310: fix keypad no-autorepeat Link: https://lore.kernel.org/r/20240425071856.9235-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29Merge tag 'omap-for-v6.10/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt Devicetree changes for omaps for v6.10 Update n900 charge limit, and make use of the clksel binding for dra7 for the clksel clocks and other dpll output related clocks. * tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE ARM: dts: n900: set charge current limit to 950mA Link: https://lore.kernel.org/r/pull-1714020191-304166@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usageRob Herring
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-29Merge tag 'renesas-dts-for-v6.10-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.10 - Add HDMI capture support for the Function expansion board for the Eagle development board, - Add PMIC support for the RZ/G2UL SMARC EVK development board, - Add thermal, more serial ((H)SCIF), and timer (CMT and TMU) support for the R-Car V4M SoC, - Add Timer Unit (TMU) support for the R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases arm64: dts: renesas: r8a779h0: Add TMU nodes arm64: dts: renesas: r8a779h0: Add CMT nodes arm64: dts: renesas: gray-hawk-single: Enable nfsroot ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent arm64: dts: renesas: gray-hawk-single: Add second debug serial port arm64: dts: renesas: r8a779h0: Add SCIF nodes arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes ARM: dts: renesas: rcar-gen2: Add TMU nodes ARM: dts: renesas: rzg1: Add TMU nodes ARM: dts: renesas: r8a73a4: Add TMU nodes ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes arm64: dts: renesas: r8a779h0: Add thermal nodes arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY arm64: dts: renesas: eagle: Add capture overlay for Function expansion board Link: https://lore.kernel.org/r/cover.1712915536.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-28xtensa: remove redundant flush_dcache_page and ↵Barry Song
ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE macros xtensa's flush_dcache_page() can be a no-op sometimes. There is a generic implementation for this case in include/asm-generic/ cacheflush.h. #ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE static inline void flush_dcache_page(struct page *page) { } #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #endif So remove the superfluous flush_dcache_page() definition, which also helps silence potential build warnings complaining the page variable passed to flush_dcache_page() is not used. In file included from crypto/scompress.c:12: include/crypto/scatterwalk.h: In function 'scatterwalk_pagedone': include/crypto/scatterwalk.h:76:30: warning: variable 'page' set but not used [-Wunused-but-set-variable] 76 | struct page *page; | ^~~~ crypto/scompress.c: In function 'scomp_acomp_comp_decomp': >> crypto/scompress.c:174:38: warning: unused variable 'dst_page' [-Wunused-variable] 174 | struct page *dst_page = sg_page(req->dst); | The issue was originally reported on LoongArch by kernel test robot (Huacai fixed it on LoongArch), then reported by Guenter and me on xtensa. This patch also removes lots of redundant macros which have been defined by asm-generic/cacheflush.h. Cc: Huacai Chen <chenhuacai@loongson.cn> Cc: Herbert Xu <herbert@gondor.apana.org.au> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202403091614.NeUw5zcv-lkp@intel.com/ Reported-by: Barry Song <v-songbaohua@oppo.com> Closes: https://lore.kernel.org/all/CAGsJ_4yDk1+axbte7FKQEwD7X2oxUCFrEc9M5YOS1BobfDFXPA@mail.gmail.com/ Reported-by: Guenter Roeck <linux@roeck-us.net> Closes: https://lore.kernel.org/all/aaa8b7d7-5abe-47bf-93f6-407942436472@roeck-us.net/ Fixes: 77292bb8ca69 ("crypto: scomp - remove memcpy if sg_nents is 1 and pages are lowmem") Signed-off-by: Barry Song <v-songbaohua@oppo.com> Message-Id: <20240319010920.125192-1-21cnbao@gmail.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2024-04-28riscv: hwprobe: export Zihintpause ISA extensionClément Léger
Export the Zihintpause ISA extension through hwprobe which allows using "pause" instructions. Some userspace applications (OpenJDK for instance) uses this to handle some locking back-off. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240221083108.1235311-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28riscv: misaligned: remove CONFIG_RISCV_M_MODE specific codeClément Léger
While reworking code to fix sparse errors, it appears that the RISCV_M_MODE specific could actually be removed and use the one for normal mode. Even though RISCV_M_MODE can do direct user memory access, using the user uaccess helpers is also going to work. Since there is no need anymore for specific accessors (load_u8()/store_u8()), we can directly use memcpy()/copy_{to/from}_user() and get rid of the copy loop entirely. __read_insn() is also fixed to use an unsigned long instead of a pointer which was cast in __user address space. The insn_addr parameter is now cast from unsigned lnog to the correct address space directly. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240206154104.896809-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28riscv: Do not save the scratch CSR during suspendSamuel Holland
While the processor is executing kernel code, the value of the scratch CSR is always zero, so there is no need to save the value. Continue to write the CSR during the resume flow, so we do not rely on firmware to initialize it. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20240312195641.1830521-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28Merge patch series "riscv: 64-bit NOMMU fixes and enhancements"Palmer Dabbelt
Samuel Holland <samuel.holland@sifive.com> says: This series aims to improve support for NOMMU, specifically by making it easier to test NOMMU kernels in QEMU and on various widely-available hardware (errata permitting). After all, everything supports Svbare... After applying this series, a NOMMU kernel based on defconfig (changing only the three options below*) boots to userspace on QEMU when passed as -kernel. # CONFIG_RISCV_M_MODE is not set # CONFIG_MMU is not set CONFIG_NONPORTABLE=y *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS, because LLD bails on out-of-range references to undefined weak symbols. * b4-shazam-merge: riscv: Allow NOMMU kernels to run in S-mode riscv: Remove MMU dependency from Zbb and Zicboz riscv: Fix loading 64-bit NOMMU kernels past the start of RAM riscv: Fix TASK_SIZE on 64-bit NOMMU Link: https://lore.kernel.org/r/20240227003630.3634533-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28RISC-V: enable building 64-bit kernels with rust supportMiguel Ojeda
The rust modules work on 64-bit RISC-V, with no twiddling required. Select HAVE_RUST and provide the required flags to kbuild so that the modules can be used. The Makefile and Kconfig changes are lifted from work done by Miguel in the Rust-for-Linux tree, hence his authorship. Following the rabbit hole, the Makefile changes originated in a script, created based on config files originally added by Gary, hence his co-authorship. 32-bit is broken in core rust code, so support is limited to 64-bit: ld.lld: error: undefined symbol: __udivdi3 As 64-bit RISC-V is now supported, add it to the arch support table. Co-developed-by: Gary Guo <gary@garyguo.net> Signed-off-by: Gary Guo <gary@garyguo.net> Signed-off-by: Miguel Ojeda <ojeda@kernel.org> Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240409-silencer-book-ce1320f06aab@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28Merge patch series "Rework & improve riscv cmpxchg.h and atomic.h"Palmer Dabbelt
Leonardo Bras <leobras@redhat.com> says: While studying riscv's cmpxchg.h file, I got really interested in understanding how RISCV asm implemented the different versions of {cmp,}xchg. When I understood the pattern, it made sense for me to remove the duplications and create macros to make it easier to understand what exactly changes between the versions: Instruction sufixes & barriers. Also, did the same kind of work on atomic.c. After that, I noted both cmpxchg and xchg only accept variables of size 4 and 8, compared to x86 and arm64 which do 1,2,4,8. Now that deduplication is done, it is quite direct to implement them for variable sizes 1 and 2, so I did it. Then Guo Ren already presented me some possible users :) I did compare the generated asm on a test.c that contained usage for every changed function, and could not detect any change on patches 1 + 2 + 3 compared with upstream. Pathes 4 & 5 were compiled-tested, merged with guoren/qspinlock_v11 and booted just fine with qemu -machine virt -append "qspinlock". (tree: https://gitlab.com/LeoBras/linux/-/commits/guo_qspinlock_v11) Latest tests happened based on this tree: https://github.com/guoren83/linux/tree/qspinlock_v12 * b4-shazam-lts: riscv/cmpxchg: Implement xchg for variables of size 1 and 2 riscv/cmpxchg: Implement cmpxchg for variables of size 1 and 2 riscv/atomic.h : Deduplicate arch_atomic.* riscv/cmpxchg: Deduplicate cmpxchg() asm and macros riscv/cmpxchg: Deduplicate xchg() asm functions Link: https://lore.kernel.org/r/20240103163203.72768-2-leobras@redhat.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-04-28Merge tag 'x86-urgent-2024-04-28' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: - Make the CPU_MITIGATIONS=n interaction with conflicting mitigation-enabling boot parameters a bit saner. - Re-enable CPU mitigations by default on non-x86 - Fix TDX shared bit propagation on mprotect() - Fix potential show_regs() system hang when PKE initialization is not fully finished yet. - Add the 0x10-0x1f model IDs to the Zen5 range - Harden #VC instruction emulation some more * tag 'x86-urgent-2024-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: cpu: Ignore "mitigations" kernel parameter if CPU_MITIGATIONS=n cpu: Re-enable CPU mitigations by default for !X86 architectures x86/tdx: Preserve shared bit on mprotect() x86/cpu: Fix check for RDPKRU in __show_regs() x86/CPU/AMD: Add models 0x10-0x1f to the Zen5 range x86/sev: Check for MWAITX and MONITORX opcodes in the #VC handler
2024-04-28ARM: dts: imx6ul-pico: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-kontron-bl-common: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-kontron-bl-43: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dtb: pwm@20f8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-isiot: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-imx6ull-opos6uldev: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-geam: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-geam.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-ccimx6ulsbcpro: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dtb: pwm@20f0000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6ul-14x14-evk: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6sx-softing-vining-2000: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@22a8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm nodes as the soc dtsi doesn't disable these devices. Drop these properties, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6sx-sdb: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6sx-nitrogen6sx: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6sll-evk: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sll-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6sl-evk: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sl-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable these devices. Drop this property, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6q-var-dt6customboard: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6q-prti6q: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6q-pistachio: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6q-novena: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-novena.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6q-kp: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-skov-cpu: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-savageboard: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-sabresd: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-sabrelite: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-sabreauto: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-phytec-mira: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-04-28ARM: dts: imx6qdl-nitrogen6x: Use #pwm-cells = <3> for imx27-pwm deviceUwe Kleine-König
The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-10-02 17:31:24 +0000