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2022-02-25arm64: Always use individual bits in CPACR floating point enablesMark Brown
CPACR_EL1 has several bitfields for controlling traps for floating point features to EL1, each of which has a separate bits for EL0 and EL1. Marc Zyngier noted that we are not consistent in our use of defines to manipulate these, sometimes using a define covering the whole field and sometimes using defines for the individual bits. Make this consistent by expanding the whole field defines where they are used (currently only in the KVM code) and deleting them so that no further uses can be introduced. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220207152109.197566-3-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: Define CPACR_EL1_FPEN similarly to other floating point controlsMark Brown
The base floating point, SVE and SME all have enable controls for EL0 and EL1 in CPACR_EL1 which have a similar layout and function. Currently the basic floating point enable FPEN is defined differently to the SVE control, specified as a single define in kvm_arm.h rather than in sysreg.h. Move the define to sysreg.h and provide separate EL0 and EL1 control bits so code managing the different floating point enables can look consistent. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220207152109.197566-2-broonie@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25Merge tag 'renesas-arm-dt-for-v5.18-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.18 - External interrupt (INTC-EX) support for the R-Car V3U SoC, - Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and RZ/V2L SMARC EVK development boards, - Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle and Condor development boards, - NAND support for the RZ/N1D SoC, - DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC, - LVDS support for the R-Car M3-W+ SoC, - HDMI output and 9-axis sensor support for the Kingfisher (ULCB extension) board, - MAX96712 GMSL serializer support for the Falcon development board, - MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3 SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits) arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings arm64: dts: renesas: rzg2l-smarc: Add common dtsi file arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound arm64: dts: renesas: rcar-gen3: Add MOST devices arm64: dts: renesas: Miscellaneous whitespace fixes arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712 arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device arm64: dts: renesas: ulcb-kf: Add KF HDMI output arm64: dts: renesas: r8a77961: Add lvds0 device node arm64: dts: renesas: r8a779f0: Add sys-dmac nodes ARM: dts: r9a06g032: Describe the NAND controller arm64: dts: renesas: Add GMSL cameras .dtsi ... Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'samsung-dt-pinctrl-5.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung pinctrl DTS and driver changes for v5.18 Conversion of Samsung pinctrl bindings to dtschema followed up with alignment of DTS files to the dtschema. The entire work consists of three parts but everything should be merged at once to avoid dtschema check errors: 1. Samsung pinctrl driver change necessary to accept new DTS (driver depends on node names and this has to be adjusted because of dtschema). 2. Conversion to dtschema which brings requirement of different naming of the GPIO nodes. 3. DTS commits depending on driver (1) above, which convert all GPIO pin bank names to new naming, required by dtschema. This also includes few cleanups around DTS which are here to avoid any merge conflicts. The Samsung pinctrl driver changes are backwards compatible. However the DTS changes (renaming nodes) could cause problems in out-of-tree or other project implementations of the driver. * tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits) arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9 ARM: dts: s5pv210: align pinctrl with dtschema ARM: dts: s3c64xx: align pinctrl with dtschema ARM: dts: s3c24xx: align pinctrl with dtschema arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9 arm64: dts: exynos: align pinctrl with dtschema in Exynos7 arm64: dts: exynos: align pinctrl with dtschema in Exynos5433 ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800 ARM: dts: exynos: align pinctrl with dtschema in Exynos5410 ARM: dts: exynos: align pinctrl with dtschema in Exynos5260 ARM: dts: exynos: align pinctrl with dtschema in Exynos5250 ARM: dts: exynos: align pinctrl with dtschema in Exynos4412 ARM: dts: exynos: align pinctrl with dtschema in Exynos4210 ARM: dts: exynos: align pinctrl with dtschema in Exynos3250 ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi ARM: dts: exynos: override pins by label in Peach Pi ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit ARM: dts: exynos: override pins by label in Peach Pit ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU ... Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'socfpga_dts_update_for_v5.18_part1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v5.18, part 1 - Cleanup of Altera/Intel ARMv7 and ARMv8 DTS and bindings * tag 'socfpga_dts_update_for_v5.18_part1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: (22 commits) ARM: dts: socfpga: cyclone5: align regulator node with dtschema ARM: dts: socfpga: arria10: align regulator node with dtschema arm64: dts: agilex: align pl330 node name with dtschema arm64: dts: stratix10: align pl330 node name with dtschema arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema arm64: dts: agilex: align mmc node names with dtschema arm64: dts: agilex: add board compatible for N5X DK arm64: dts: agilex: add board compatible for SoCFPGA DK arm64: dts: stratix10: align regulator node names with dtschema arm64: dts: stratix10: align mmc node names with dtschema arm64: dts: stratix10: move ARM timer out of SoC node arm64: dts: stratix10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for SoCFPGA DK ARM: dts: arria10: add board compatible for Mercury AA1 ARM: dts: arria5: add board compatible for SoCFPGA DK dt-bindings: clock: intel,stratix10: convert to dtschema dt-bindings: intel: document Agilex based board compatibles dt-bindings: altera: document Stratix 10 based board compatibles dt-bindings: altera: document VT compatibles dt-bindings: altera: document Arria 10 based board compatibles ... Link: https://lore.kernel.org/r/20220211112556.98940-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'samsung-dt64-5.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM64 changes for v5.18 1. Minor improvements and dtschema fixes (node names, properties). 2. Fix issues pointed out by DT schema checks: - Add necessary clock controller inputs on Exynos7. - Add USB DWC3 supplies. - Drop old syscon phandle on Exynos5433. 3. Add initial Exynos850 support and WinLink E850-96 board using it. * tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS arm64: dts: exynos: align pl330 node name with dtschema arm64: dts: exynos: Add initial E850-96 board support arm64: dts: exynos: Add initial Exynos850 SoC support arm64: dts: exynos: add USB DWC3 supplies to Espresso board arm64: dts: exynos: add necessary clock inputs in Exynos7 arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2 Link: https://lore.kernel.org/r/20220209145226.184375-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'samsung-dt-5.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.18 1. Minor improvements and dtschema fixes (node names, properties). 2. Fix issues pointed out by DT schema checks: - Add necessary clock controller inputs on Exynos5260. - Drop unsupported regulators on Odroid XU. - Add USB DWC3 supplies. - Drop old thermal properties from Exynos4210. 3. Add support for Samsung Chagall WiFi (Exynos5420, Samsung Galaxy Tab S 10.5", SM-T800 ) and a similar Samsung Klimt WiFi (Samsung Galaxy Tab S 8.4"). 4. Add battery to Samsung P4Nnote (Exynos4412, Samsung Galaxy Note 10.1). * tag 'samsung-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (22 commits) ARM: dts: exynos: use generic node name for LPDDR3 timings in Odroid ARM: dts: exynos: add charger and battery to p4note ARM: dts: exynos: update dma node name with dtschema ARM: dts: exynos: use define for TMU clock on Exynos4412 ARM: dts: exynos: drop old thermal properties from Exynos4210 ARM: dts: exynos: add fake USB DWC3 supplies to SMDK5410 ARM: dts: exynos: add USB DWC3 supplies to SMDK5420 ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pi ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pit ARM: dts: exynos: add USB DWC3 supplies to ArndaleOcta ARM: dts: exynos: add USB DWC3 supplies to Chromebook Spring ARM: dts: exynos: add USB DWC3 supplies to Chromebook Snow ARM: dts: exynos: add USB DWC3 supplies to SMDK5250 ARM: dts: exynos: add USB DWC3 supplies to Arndale ARM: dts: exynos: Add support for Samsung Klimt WiFi dt-bindings: arm: samsung: document Klimt WiFi board binding ARM: dts: exynos: Add support for Samsung Chagall WiFi dt-bindings: arm: samsung: document Chagall WiFi board binding ARM: dts: exynos: drop unsupported MAX77802 regulators on Odroid XU ARM: dts: exynos: add necessary clock controller inputs in Exynos5260 ... Link: https://lore.kernel.org/r/20220209145226.184375-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'tesla-dt64-5.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Tesla FSD ARM64 changes for v5.18 Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry and defconfig change. This brings and enables this new platform. This includes clock controller bindings (header files with clock IDs) which are shared also with Tesla FSD SoC clock controller pull request. * tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add SPI device nodes arm64: defconfig: Enable Tesla FSD SoC arm64: dts: fsd: Add initial pinctrl support arm64: dts: fsd: Add initial device tree support dt-bindings: clock: Document FSD CMU bindings dt-bindings: clock: Add bindings definitions for FSD CMU blocks dt-bindings: arm: add Tesla FSD ARM SoC dt-bindings: add vendor prefix for Tesla Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25arm64: module: remove (NOLOAD) from linker scriptFangrui Song
On ELF, (NOLOAD) sets the section type to SHT_NOBITS[1]. It is conceptually inappropriate for .plt and .text.* sections which are always SHT_PROGBITS. In GNU ld, if PLT entries are needed, .plt will be SHT_PROGBITS anyway and (NOLOAD) will be essentially ignored. In ld.lld, since https://reviews.llvm.org/D118840 ("[ELF] Support (TYPE=<value>) to customize the output section type"), ld.lld will report a `section type mismatch` error. Just remove (NOLOAD) to fix the error. [1] https://lld.llvm.org/ELF/linker_script.html As of today, "The section should be marked as not loadable" on https://sourceware.org/binutils/docs/ld/Output-Section-Type.html is outdated for ELF. Tested-by: Nathan Chancellor <nathan@kernel.org> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Fangrui Song <maskray@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20220218081209.354383-1-maskray@google.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Remove cpu_has_fwb() checkVladimir Murzin
cpu_has_fwb() is supposed to warn user is following architectural requirement is not valid: LoUU, bits [29:27] - Level of Unification Uniprocessor for the cache hierarchy. Note When FEAT_S2FWB is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches. LoUIS, bits [23:21] - Level of Unification Inner Shareable for the cache hierarchy. Note When FEAT_S2FWB is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches. It is not really clear what user have to do if assertion fires. Having assertions about the CPU design like this inspire even more assertions to be added and the kernel definitely is not the right place for that, so let's remove cpu_has_fwb() altogether. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Link: https://lore.kernel.org/r/20220224164739.119168-1-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25Merge branch kvm-arm64/psci-1.1 into kvmarm-master/nextMarc Zyngier
* kvm-arm64/psci-1.1: : . : Limited PSCI-1.1 support from Will Deacon: : : This small series exposes the PSCI SYSTEM_RESET2 call to guests, which : allows the propagation of a "reset_type" and a "cookie" back to the VMM. : Although Linux guests only ever pass 0 for the type ("SYSTEM_WARM_RESET"), : the vendor-defined range can be used by a bootloader to provide additional : information about the reset, such as an error code. : . KVM: arm64: Remove unneeded semicolons KVM: arm64: Indicate SYSTEM_RESET2 in kvm_run::system_event flags field KVM: arm64: Expose PSCI SYSTEM_RESET2 call to the guest KVM: arm64: Bump guest PSCI version to 1.1 Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-02-25KVM: arm64: Remove unneeded semicolonsChangcheng Deng
Fix the following coccicheck review: ./arch/arm64/kvm/psci.c: 379: 3-4: Unneeded semicolon Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> [maz: squashed another instance of the same issue in the patch] Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20220223092750.1934130-1-deng.changcheng@zte.com.cn Link: https://lore.kernel.org/r/20220225122922.GA19390@willie-the-truck
2022-02-25ARM: tegra: tamonten: Fix I2C3 pad settingRichard Leitner
This patch fixes the tristate configuration for i2c3 function assigned to the dtf pins on the Tamonten Tegra20 SoM. Signed-off-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25arm64: tegra: Drop arm,armv8-pmuv3 compatible stringThierry Reding
The arm,armv8-pmuv3 compatible string is meant to be used only for software models and not silicon chips. Drop them and use silicon- specific compatible strings instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-25arm64: Add support of PAuth QARMA3 architected algorithmVladimir Murzin
QARMA3 is relaxed version of the QARMA5 algorithm which expected to reduce the latency of calculation while still delivering a suitable level of security. Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 APA3, bits [15:12] Indicates whether the QARMA3 algorithm is implemented in the PE for address authentication in AArch64 state. GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-4-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Mark existing PAuth architected algorithm as QARMA5Vladimir Murzin
In preparation of supporting PAuth QARMA3 architected algorithm mark existing one as QARMA5, so we can distingwish between two. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-3-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25arm64: cpufeature: Account min_field_value when cheking secondaries for PAuthVladimir Murzin
In case, both boot_val and sec_val have value below min_field_value we would wrongly report that address authentication is supported. It is not a big issue because we enable address authentication based on boot cpu (and check there is correct). Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220224124952.119612-2-vladimir.murzin@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25KVM: s390: pv: make use of ultravisor AIV supportMichael Mueller
This patch enables the ultravisor adapter interruption vitualization support indicated by UV feature BIT_UV_FEAT_AIV. This allows ISC interruption injection directly into the GISA IPM for PV kvm guests. Hardware that does not support this feature will continue to use the UV interruption interception method to deliver ISC interruptions to PV kvm guests. For this purpose, the ECA_AIV bit for all guest cpus will be cleared and the GISA will be disabled during PV CPU setup. In addition a check in __inject_io() has been removed. That reduces the required instructions for interruption handling for PV and traditional kvm guests. Signed-off-by: Michael Mueller <mimu@linux.ibm.com> Reviewed-by: Janosch Frank <frankja@linux.ibm.com> Link: https://lore.kernel.org/r/20220209152217.1793281-2-mimu@linux.ibm.com Reviewed-by: Christian Borntraeger <borntraeger@linux.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com>
2022-02-25KVM: x86/mmu: clear MMIO cache when unloading the MMUPaolo Bonzini
For cleanliness, do not leave a stale GVA in the cache after all the roots are cleared. In practice, kvm_mmu_load will go through kvm_mmu_sync_roots if paging is on, and will not use vcpu_match_mmio_gva at all if paging is off. However, leaving data in the cache might cause bugs in the future. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: Always use current mmu's role when loading new PGDPaolo Bonzini
Since the guest PGD is now loaded after the MMU has been set up completely, the desired role for a cache hit is simply the current mmu_role. There is no need to compute it again, so __kvm_mmu_new_pgd can be folded in kvm_mmu_new_pgd. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: load new PGD after the shadow MMU is initializedPaolo Bonzini
Now that __kvm_mmu_new_pgd does not look at the MMU's root_level and shadow_root_level anymore, pull the PGD load after the initialization of the shadow MMUs. Besides being more intuitive, this enables future simplifications and optimizations because it's not necessary anymore to compute the role outside kvm_init_mmu. In particular, kvm_mmu_reset_context was not attempting to use a cached PGD to avoid having to figure out the new role. With this change, it could follow what nested_{vmx,svm}_load_cr3 are doing, and avoid unloading all the cached roots. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: look for a cached PGD when going from 32-bit to 64-bitPaolo Bonzini
Right now, PGD caching avoids placing a PAE root in the cache by using the old value of mmu->root_level and mmu->shadow_root_level; it does not look for a cached PGD if the old root is a PAE one, and then frees it using kvm_mmu_free_roots. Change the logic instead to free the uncacheable root early. This way, __kvm_new_mmu_pgd is able to look up the cache when going from 32-bit to 64-bit (if there is a hit, the invalid root becomes the least recently used). An example of this is nested virtualization with shadow paging, when a 64-bit L1 runs a 32-bit L2. As a side effect (which is actually the reason why this patch was written), PGD caching does not use the old value of mmu->root_level and mmu->shadow_root_level anymore. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: do not pass vcpu to root freeing functionsPaolo Bonzini
These functions only operate on a given MMU, of which there is more than one in a vCPU (we care about two, because the third does not have any roots and is only used to walk guest page tables). They do need a struct kvm in order to lock the mmu_lock, but they do not needed anything else in the struct kvm_vcpu. So, pass the vcpu->kvm directly to them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: do not consult levels when freeing rootsPaolo Bonzini
Right now, PGD caching requires a complicated dance of first computing the MMU role and passing it to __kvm_mmu_new_pgd(), and then separately calling kvm_init_mmu(). Part of this is due to kvm_mmu_free_roots using mmu->root_level and mmu->shadow_root_level to distinguish whether the page table uses a single root or 4 PAE roots. Because kvm_init_mmu() can overwrite mmu->root_level, kvm_mmu_free_roots() must be called before kvm_init_mmu(). However, even after kvm_init_mmu() there is a way to detect whether the page table may hold PAE roots, as root.hpa isn't backed by a shadow when it points at PAE roots. Using this method results in simpler code, and is one less obstacle in moving all calls to __kvm_mmu_new_pgd() after the MMU has been initialized. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: use struct kvm_mmu_root_info for mmu->rootPaolo Bonzini
The root_hpa and root_pgd fields form essentially a struct kvm_mmu_root_info. Use the struct to have more consistency between mmu->root and mmu->prev_roots. The patch is entirely search and replace except for cached_root_available, which does not need a temporary struct kvm_mmu_root_info anymore. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86/mmu: avoid NULL-pointer dereference on page freeing bugsPaolo Bonzini
WARN and bail if KVM attempts to free a root that isn't backed by a shadow page. KVM allocates a bare page for "special" roots, e.g. when using PAE paging or shadowing 2/3/4-level page tables with 4/5-level, and so root_hpa will be valid but won't be backed by a shadow page. It's all too easy to blindly call mmu_free_root_page() on root_hpa, be nice and WARN instead of crashing KVM and possibly the kernel. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: do not deliver asynchronous page faults if CR0.PG=0Paolo Bonzini
Enabling async page faults is nonsensical if paging is disabled, but it is allowed because CR0.PG=0 does not clear the async page fault MSR. Just ignore them and only use the artificial halt state, similar to what happens in guest mode if async #PF vmexits are disabled. Given the increasingly complex logic, and the nicer code if the new "if" is placed last, opportunistically change the "||" into a chain of "if (...) return false" statements. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: Reinitialize context if host userspace toggles EFER.LMEPaolo Bonzini
While the guest runs, EFER.LME cannot change unless CR0.PG is clear, and therefore EFER.NX is the only bit that can affect the MMU role. However, set_efer accepts a host-initiated change to EFER.LME even with CR0.PG=1. In that case, the MMU has to be reset. Fixes: 11988499e62b ("KVM: x86: Skip EFER vs. guest CPUID checks for host-initiated writes") Cc: stable@vger.kernel.org Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: Provide per VM capability for disabling PMU virtualizationDavid Dunn
Add a new capability, KVM_CAP_PMU_CAPABILITY, that takes a bitmask of settings/features to allow userspace to configure PMU virtualization on a per-VM basis. For now, support a single flag, KVM_PMU_CAP_DISABLE, to allow disabling PMU virtualization for a VM even when KVM is configured with enable_pmu=true a module level. To keep KVM simple, disallow changing VM's PMU configuration after vCPUs have been created. Signed-off-by: David Dunn <daviddunn@google.com> Message-Id: <20220223225743.2703915-2-daviddunn@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: Fix pointer mistmatch warning when patching RET0 static callsSean Christopherson
Cast kvm_x86_ops.func to 'void *' when updating KVM static calls that are conditionally patched to __static_call_return0(). clang complains about using mismatching pointers in the ternary operator, which breaks the build when compiling with CONFIG_KVM_WERROR=y. >> arch/x86/include/asm/kvm-x86-ops.h:82:1: warning: pointer type mismatch ('bool (*)(struct kvm_vcpu *)' and 'void *') [-Wpointer-type-mismatch] Fixes: 5be2226f417d ("KVM: x86: allow defining return-0 static calls") Reported-by: Like Xu <like.xu.linux@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Reviewed-by: David Dunn <daviddunn@google.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Message-Id: <20220223162355.3174907-1-seanjc@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: VMX: Remove scratch 'cpu' variable that shadows an identical scratch varPeng Hao
From: Peng Hao <flyingpeng@tencent.com> Remove a redundant 'cpu' declaration from inside an if-statement that that shadows an identical declaration at function scope. Both variables are used as scratch variables in for_each_*_cpu() loops, thus there's no harm in sharing a variable. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peng Hao <flyingpeng@tencent.com> Message-Id: <20220222103954.70062-1-flyingpeng@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25kvm: vmx: Fix typos comment in __loaded_vmcs_clear()Peng Hao
Fix a comment documenting the memory barrier related to clearing a loaded_vmcs; loaded_vmcs tracks the host CPU the VMCS is loaded on via the field 'cpu', it doesn't have a 'vcpu' field. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peng Hao <flyingpeng@tencent.com> Message-Id: <20220222104029.70129-1-flyingpeng@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: nVMX: Make setup/unsetup under the same conditionsPeng Hao
Make sure nested_vmx_hardware_setup/unsetup() are called in pairs under the same conditions. Calling nested_vmx_hardware_unsetup() when nested is false "works" right now because it only calls free_page() on zero- initialized pointers, but it's possible that more code will be added to nested_vmx_hardware_unsetup() in the future. Reviewed-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peng Hao <flyingpeng@tencent.com> Message-Id: <20220222104054.70286-1-flyingpeng@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25Merge branch 'kvm-hv-xmm-hypercall-fixes' into HEADPaolo Bonzini
The fixes for 5.17 conflict with cleanups made in the same area earlier in the 5.18 development cycle.
2022-02-25arm64: dts: renesas: spider: Complete SCIF3 descriptionGeert Uytterhoeven
Complete the description of the serial console by adding RTS/CTS, the external clock crystal, and pin control. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8e5701ca2a5f5925918217ab79e8489535339e7b.1645458249.git.geert+renesas@glider.be
2022-02-25arm64: dts: renesas: r8a779f0: Add pinctrl device nodeGeert Uytterhoeven
Add a device node for the Pin Function Controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that the register block does not include registers for banks 4-7, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/cf4d261ba1253879e117f1598b9f47798cbda635.1645458249.git.geert+renesas@glider.be
2022-02-25arm64: Change elfcore for_each_mte_vma() to use VMA iteratorLiam Howlett
Rework for_each_mte_vma() to use a VMA iterator instead of an explicit linked-list. This will allow easy integration with the maple tree work which removes the VMA list altogether. Signed-off-by: Liam R. Howlett <Liam.Howlett@oracle.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220218023650.672072-1-Liam.Howlett@oracle.com [will: Folded in fix from Catalin] Link: https://lore.kernel.org/r/YhUcywqIhmHvX6dG@arm.com Signed-off--by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2022-02-25ARM: at91: Kconfig: select PM_OPPClaudiu Beznea
Select PM_OPP. This is requested for CPUFreq driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-6-claudiu.beznea@microchip.com
2022-02-25ARM: at91: PM: add cpu idle support for sama7g5Claudiu Beznea
Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO register to divide the CPU clock by 16 before switching it to idle and use automatic self-refresh option of DDR controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-5-claudiu.beznea@microchip.com
2022-02-25ARM: at91: ddr: fix typo to align with datasheet namingClaudiu Beznea
Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet naming. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
2022-02-25ARM: configs: at91: sama7: add config for cpufreqClaudiu Beznea
Add config flags for CPUFreq. This includes enabling CPUFreq support, CPUFreq DT driver and governors, default one being the conservative governor. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-11-claudiu.beznea@microchip.com
2022-02-25ARM: configs: at91: sama7: enable cpu idleClaudiu Beznea
Enable CPU idle support for SAMA7 config. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-10-claudiu.beznea@microchip.com
2022-02-25KVM: x86: hyper-v: HVCALL_SEND_IPI_EX is an XMM fast hypercallVitaly Kuznetsov
It has been proven on practice that at least Windows Server 2019 tries using HVCALL_SEND_IPI_EX in 'XMM fast' mode when it has more than 64 vCPUs and it needs to send an IPI to a vCPU > 63. Similarly to other XMM Fast hypercalls (HVCALL_FLUSH_VIRTUAL_ADDRESS_{LIST,SPACE}{,_EX}), this information is missing in TLFS as of 6.0b. Currently, KVM returns an error (HV_STATUS_INVALID_HYPERCALL_INPUT) and Windows crashes. Note, HVCALL_SEND_IPI is a 'standard' fast hypercall (not 'XMM fast') as all its parameters fit into RDX:R8 and this is handled by KVM correctly. Cc: stable@vger.kernel.org # 5.14.x: 3244867af8c0: KVM: x86: Ignore sparse banks size for an "all CPUs", non-sparse IPI req Cc: stable@vger.kernel.org # 5.14.x Fixes: d8f5537a8816 ("KVM: hyper-v: Advertise support for fast XMM hypercalls") Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220222154642.684285-5-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: hyper-v: Fix the maximum number of sparse banks for XMM fast TLB ↵Vitaly Kuznetsov
flush hypercalls When TLB flush hypercalls (HVCALL_FLUSH_VIRTUAL_ADDRESS_{LIST,SPACE}_EX are issued in 'XMM fast' mode, the maximum number of allowed sparse_banks is not 'HV_HYPERCALL_MAX_XMM_REGISTERS - 1' (5) but twice as many (10) as each XMM register is 128 bit long and can hold two 64 bit long banks. Cc: stable@vger.kernel.org # 5.14.x Fixes: 5974565bc26d ("KVM: x86: kvm_hv_flush_tlb use inputs from XMM registers") Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220222154642.684285-4-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: hyper-v: Drop redundant 'ex' parameter from kvm_hv_flush_tlb()Vitaly Kuznetsov
'struct kvm_hv_hcall' has all the required information already, there's no need to pass 'ex' additionally. No functional change intended. Cc: stable@vger.kernel.org # 5.14.x Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220222154642.684285-3-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25KVM: x86: hyper-v: Drop redundant 'ex' parameter from kvm_hv_send_ipi()Vitaly Kuznetsov
'struct kvm_hv_hcall' has all the required information already, there's no need to pass 'ex' additionally. No functional change intended. Cc: stable@vger.kernel.org # 5.14.x Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220222154642.684285-2-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-25ARM: dts: at91: sama7g5: add oppsClaudiu Beznea
Add OPPs for SAMA7G5 along with clock for CPU. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-9-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5ek: set regulator voltages for standby stateClaudiu Beznea
Set regulator voltages for standby state to avoid wrong behavior of system while in standby. The CPU voltage has been chosen as being the one corresponding to OPP=600MHz. Next commit will set the 600MHz OPP as the suspend OPP. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-8-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: fix low limit for CPU regulatorClaudiu Beznea
Fix low limit for CPU regulator. Otherwise setting voltages lower than 1.125V will not be allowed (CPUFreq will not be allowed to set proper voltages on proper frequencies). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220113144900.906370-7-claudiu.beznea@microchip.com
2022-02-25ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ekHari Prasath
Enable the can0 and can1 controllers in sama7g5-ek board along with its pin mux settings. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220222113924.25799-3-Hari.PrasathGE@microchip.com
generated by cgit (git 2.34.1) at 2025-10-01 15:20:29 +0000