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2025-05-21x86/bugs: Restructure ITS mitigationDavid Kaplan
Restructure the ITS mitigation to use select/update/apply functions like the other mitigations. There is a particularly complex interaction between ITS and Retbleed as CDT (Call Depth Tracking) is a mitigation for both, and either its=stuff or retbleed=stuff will attempt to enable CDT. retbleed_update_mitigation() runs first and will check the necessary pre-conditions for CDT if either ITS or Retbleed stuffing is selected. If checks pass and ITS stuffing is selected, it will select stuffing for Retbleed as well. its_update_mitigation() runs after and will either select stuffing if retbleed stuffing was enabled, or fall back to the default (aligned thunks) if stuffing could not be enabled. Enablement of CDT is done exclusively in retbleed_apply_mitigation(). its_apply_mitigation() is only used to enable aligned thunks. Signed-off-by: David Kaplan <david.kaplan@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/20250516193212.128782-1-david.kaplan@amd.com
2025-05-21Merge tag 'v6.15-rc7' into x86/core, to pick up fixesIngo Molnar
Pick up build fixes from upstream to make this tree more testable. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-21x86/xen/msr: Fix uninitialized variable 'err'Xin Li (Intel)
xen_read_msr_safe() currently passes an uninitialized argument 'err' to xen_do_read_msr(). But as xen_do_read_msr() may not set the argument, xen_read_msr_safe() could return err with an unpredictable value. To ensure correctness, initialize err to 0 (representing success) in xen_read_msr_safe(). Do the same in xen_read_msr(), even err is not used after being passed to xen_do_read_msr(). Closes: https://lore.kernel.org/xen-devel/aBxNI_Q0-MhtBSZG@stanley.mountain/ Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Xin Li (Intel) <xin@zytor.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: H. Peter Anvin <hpa@zytor.com> Link: https://lore.kernel.org/r/20250517165713.935384-1-xin@zytor.com
2025-05-21RISC-V: KVM: add KVM_CAP_RISCV_MP_STATE_RESETRadim Krčmář
Add a toggleable VM capability to reset the VCPU from userspace by setting MP_STATE_INIT_RECEIVED through IOCTL. Reset through a mp_state to avoid adding a new IOCTL. Do not reset on a transition from STOPPED to RUNNABLE, because it's better to avoid side effects that would complicate userspace adoption. The MP_STATE_INIT_RECEIVED is not a permanent mp_state -- IOCTL resets the VCPU while preserving the original mp_state -- because we wouldn't gain much from having a new state it in the rest of KVM, but it's a very non-standard use of the IOCTL. Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250515143723.2450630-5-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-21RISC-V: KVM: Remove scounteren initializationAtish Patra
Scounteren CSR controls the direct access the hpmcounters and cycle/ instret/time from the userspace. It's the supervisor's responsibility to set it up correctly for it's user space. They hypervisor doesn't need to decide the policy on behalf of the supervisor. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250515-fix_scounteren_vs-v3-1-729dc088943e@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-21KVM: RISC-V: remove unnecessary SBI reset stateRadim Krčmář
The SBI reset state has only two variables -- pc and a1. The rest is known, so keep only the necessary information. The reset structures make sense if we want userspace to control the reset state (which we do), but I'd still remove them now and reintroduce with the userspace interface later -- we could probably have just a single reset state per VM, instead of a reset state for each VCPU. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250403112522.1566629-6-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-21KVM: RISC-V: refactor sbi reset requestRadim Krčmář
The same code is used twice and SBI reset sets only two variables. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250403112522.1566629-5-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-21KVM: RISC-V: refactor vector state resetRadim Krčmář
Do not depend on the reset structures. vector.datap is a kernel memory pointer that needs to be preserved as it is not a part of the guest vector data. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250403112522.1566629-4-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-21RISC-V: KVM: Remove experimental tag for RISC-VAtish Patra
RISC-V KVM port is no longer experimental. Let's remove it to avoid confusion. Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250505-kvm_tag_change-v1-1-6dbf6af240af@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20net: phy: fixed_phy: remove irq argument from fixed_phy_addHeiner Kallweit
All callers pass PHY_POLL, therefore remove irq argument from fixed_phy_add(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Simon Horman <horms@kernel.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Greg Ungerer <gerg@linux-m68k.org> Link: https://patch.msgid.link/b3b9b3bc-c310-4a54-b376-c909c83575de@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-05-21crypto: powerpc/poly1305 - add depends on BROKEN for nowEric Biggers
As discussed in the thread containing https://lore.kernel.org/linux-crypto/20250510053308.GB505731@sol/, the Power10-optimized Poly1305 code is currently not safe to call in softirq context. Disable it for now. It can be re-enabled once it is fixed. Fixes: ba8f8624fde2 ("crypto: poly1305-p10 - Glue code for optmized Poly1305 implementation for ppc64le") Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-21Revert "crypto: powerpc/poly1305 - Add SIMD fallback"Herbert Xu
This reverts commit c66d7ebbe2fa14e41913adb421090a7426f59786. Link: https://lore.kernel.org/all/02c22854-eebf-4ad1-b89e-8c2b65ab8236@csgroup.eu/ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-20arm64: dts: rockchip: move rk3562 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-7-heiko@sntech.de
2025-05-20arm64: dts: rockchip: fix rk3562 pcie unit addressesHeiko Stuebner
The rk3562 pcie node currently uses the apb register as its unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:624.26-675.5: Warning (simple_bus_reg): /soc/pcie@ff500000: simple-bus unit address format error, expected "fe000000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. With the move also move the reg + reg-names below the compatible, as is the preferred position. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-6-heiko@sntech.de
2025-05-20arm64: dts: rockchip: move rk3528 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-5-heiko@sntech.de
2025-05-20arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsiHeiko Stuebner
Two empty lines between nodes, is one too many. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-4-heiko@sntech.de
2025-05-20arm64: dts: rockchip: move rk3576 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
2025-05-20arm64: dts: rockchip: fix rk3576 pcie unit addressesHeiko Stuebner
The rk3576 pcie nodes currently use the apb register as their unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000" ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de
2025-05-20arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588Diederik de Haas
The assigned-clocks and assigned-clock-rates properties were moved from the scmi_clk node onto cpu nodes in commit 87810bda8a84 ("arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s") During review of v1 of that patch set, the following comment was made: why aren't you using OPP tables to define CPU frequencies. Assigned-clocks looks like a temporary hack because you haven't done proper OPP tables. Some time later, proper OPP tables for rk3588 were added in commit 276856db91b4 ("arm64: dts: rockchip: Add OPP data for CPU cores on RK3588") So this 'temporary hack' is no longer needed. Dropping it fixes the following dtb validation issues: cpu@0: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@400: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@600: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Link: https://lore.kernel.org/linux-rockchip/CAL_JsqL_EogoKOQ1xwU75=rJSC4o7yV3Jej4vadtacX2Pt3-hw@mail.gmail.com/ Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250519101909.62754-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-20arm64: dts: rockchip: Add missing SFC power-domains to rk3576Sebastian Reichel
Add the power-domains for the RK3576 SFC nodes according to the TRM part 1. This fixes potential SErrors when accessing the SFC registers without other peripherals (e.g. eMMC) doing a prior power-domain enable. For example this is easy to trigger on the Rock 4D, which enables the SFC0 interface, but does not enable the eMMC interface at the moment. Cc: stable@vger.kernel.org Fixes: 36299757129c8 ("arm64: dts: rockchip: Add SFC nodes for rk3576") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250520-rk3576-fix-fspi-pmdomain-v1-1-f07c6e62dadd@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-20parisc: fix building with gcc-15Arnd Bergmann
The decompressor is built with the default C dialect, which is now gnu23 on gcc-15, and this clashes with the kernel's bool type definition: In file included from include/uapi/linux/posix_types.h:5, from arch/parisc/boot/compressed/misc.c:7: include/linux/stddef.h:11:9: error: cannot use keyword 'false' as enumeration constant 11 | false = 0, Add the -std=gnu11 argument here, as we do for all other architectures. Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Helge Deller <deller@gmx.de>
2025-05-20LoongArch: KVM: Do not flush tlb if HW PTW supportedBibo Mao
With HW PTW supported, invalid TLB is not added when page fault happens. But for EXCCODE_TLBM exception, stale TLB may exist because of the last read access. Thus TLB flush operation is necessary for the EXCCODE_TLBM exception, but not necessary for other tyeps of page fault exceptions. With SW PTW supported, invalid TLB is added in the TLB refill exception. TLB flush operation is necessary for all types of page fault exceptions. Here remove unnecessary TLB flush opereation with HW PTW supported. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-20LoongArch: KVM: Add ecode parameter for exception handlersBibo Mao
For some KVM exception types, they share the same exception handler. To show the difference, ecode (exception code) is added as a new parameter in exception handlers. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-20Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"AngeloGioacchino Del Regno
As clearly seen on other non-MediaTek platforms, this is known to eventually produce regressions in the future, as drivers may break ABI and stop working with older firmware versions. Although the firmware-name property was used in multiple MediaTek devicetrees for the System Companion Processor (SCP) node, avoid doing the same on MT8390 to lessen eventual ABI breakages that may happen with a driver update to change the firmware retrieval logic for the SCP. This reverts commit 2f0066dae66f30386ecd6408410e27a4d6818c15. Link: https://lore.kernel.org/r/20250520111002.282841-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodesAngeloGioacchino Del Regno
Address various dt-binding warnings for most of the MDP3 nodes by adding and removing interrupts and power domains where required. Also, remove the mediatek,mt8195-mdp3-rdma fallback compatible from the main MDP3 RDMA node as the two have never really been fully compatible. Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250520104024.3706723-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mt6359: Rename RTC node to match binding expectationsJulien Massot
Rename the node 'mt6359rtc' to 'rtc', as required by the binding. Fix the following dtb-check error: mediatek/mt8395-radxa-nio-12l.dtb: pmic: 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+' Fixes: 3b7d143be4b7 ("arm64: dts: mt6359: add PMIC MT6359 related nodes") Signed-off-by: Julien Massot <julien.massot@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250514-mt8395-dtb-errors-v2-3-d67b9077c59a@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mt8365-evk: Add goodix touchscreen supportLouis-Alexis Eyraud
The Mediatek Genio 350-EVK board has on the DSI0 connector a StarTek KD070FHFID015 display panel that uses a Goodix GT9271 I2C capacitive touch controller. The mt8365-evk devicetree already have the display panel support but lacks the touchscreen support, so add it. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://lore.kernel.org/r/20250515-mt8365-evk-enable-touchscreen-v1-1-7ba3c87b2a71@collabora.com [Angelo: Reordered regulator nodes and interurpts-extended property] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt8188: Add missing #reset-cells propertyJulien Massot
The binding now require the '#reset-cells' property but the devicetree has not been updated which trigger dtb-check errors. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-2-fb60bef1b8e1@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation boardLorenzo Bianconi
Introduce PCIe controller nodes to EN7581 SoC and EN7581 evaluation board. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20250517-en7581-evb-pcie-v1-2-97297eb063bb@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: airoha: en7581: Add gpio-ranges property for gpio controllerLorenzo Bianconi
Introduce missing gpio-ranges property for Airoha EN7581 gpio controller Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20250517-en7581-evb-pcie-v1-1-97297eb063bb@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodesFrank Wunderlich
Configure and enable SPI nodes on Bananapi R4 board. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20250516180147.10416-13-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmapsFrank Wunderlich
Add Fan and cooling maps for Bananapi-R4 board. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20250516180147.10416-12-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988: add phy calibration efuse subnodesFrank Wunderlich
MT7988 contains buildin mt753x switch which needs calibration data from efuse. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20250516180147.10416-9-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc dtsiFrank Wunderlich
In order to use uart0 or spi1 there is only 1 possible pin definition so move them to soc dtsi to reuse them in other boards and avoiding conflict if defined twice. Suggested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20250516180147.10416-7-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988: add spi controllersFrank Wunderlich
Add SPI controllers for mt7988. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphyFrank Wunderlich
Enable XS-Phy on Bananapi R4 for pcie2. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250422132438.15735-9-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2Frank Wunderlich
First usb and third pcie controller on mt7988 need a xs-phy to work properly. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: mediatek: mt7988a-bpi-r4: allow hw variants of bpi-r4Frank Wunderlich
Sinovoip has released other variants of Bananapi-R4 board. The known changes affecting only the LAN SFP+ slot which is replaced by a 2.5G phy with optional PoE. Just move the common parts to a new dtsi and keep differences (only i2c for lan-sfp) in dts. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogiaocchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250422132438.15735-3-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-20arm64: dts: renesas: white-hawk-ard-audio: Fix TPU0 groupsThuan Nguyen
White Hawk ARD audio uses a clock generated by the TPU, but commit 3d144ef10a44 ("pinctrl: renesas: r8a779g0: Fix TPU suffixes") renamed pin group "tpu_to0_a" to "tpu_to0_b". Update DTS accordingly otherwise the sound driver does not receive a clock signal. Fixes: 3d144ef10a448f89 ("pinctrl: renesas: r8a779g0: Fix TPU suffixes") Signed-off-by: Thuan Nguyen <thuan.nguyen-hong@banvien.com.vn> Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/TYCPR01MB8740608B675365215ADB0374B49CA@TYCPR01MB8740.jpnprd01.prod.outlook.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-20mips: dts: Add EcoNet DTS with EN751221 and SmartFiber XP8421-B boardCaleb James DeLisle
Add DTS files in support of EcoNet platform, including SmartFiber XP8421-B, a low cost commercially available board based on EN751221. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-05-20mips: Add EcoNet MIPS platform supportCaleb James DeLisle
Add platform support for EcoNet MIPS SoCs. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-05-20mips: dts: pic32: pic32mzda: Rename the sdhci nodename to match with common ↵Charan Pedumuru
mmc-controller binding Rename the sdhci nodename from "sdhci@" to "mmc@" to align with linux common mmc-controller binding. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-05-20MIPS: SMP: Move the AP sync point before the non-parallel aware functionsGregory CLEMENT
When CONFIG_HOTPLUG_PARALLEL is enabled, the code executing before cpuhp_ap_sync_alive() is executed in parallel, while after it is serialized. The functions set_cpu_sibling_map() and set_cpu_core_map() were not designed to be executed in parallel, so by moving the cpuhp_ap_sync_alive() before cpuhp_ap_sync_alive(), we then ensure they will be called serialized. The measurement done on EyeQ5 did not show any relevant boot time increase after applying this patch. Fixes: 76c43eb507bc ("MIPS: SMP: Implement parallel CPU bring up for EyeQ") Reported-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-05-19arm64: dts: qcom: sm4450: Add RPMh power domains supportAjit Pandey
Add device node for RPMh power domains on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250417-sm4450_rpmhpd-v1-3-361846750d3a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add retimers, dp altmode supportJens Glathe
comparing with CRD and other dts for a more complete support of the 7X only retimers, gpios, regulators, dp outputs Tested-by: Rob Clark <robdclark@gmail.com> Tested-by: Jos Dehaes <jos.dehaes@gmail.com> Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250417-slim7x-retimer-v2-1-dbe2dd511137@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllersManikanta Mylavarapu
Enable the PCIe controller and PHY nodes corresponding to RDP466. The IPQ5424 RDP466 does not have a wake gpio because it does not support low power mode. It only supports a perst gpio. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250416122538.2953658-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodesManikanta Mylavarapu
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250416122538.2953658-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: sc7280: Mark FastRPC context banks as dma-coherentXilin Wu
The FastRPC context banks are DMA-coherent on sc7280 platform. Mark them as such. This allows LLM inferencing on the CDSP using Qualcomm AI Engine Direct SDK on the qcs6490 platform. Signed-off-by: Xilin Wu <sophon@radxa.com> Link: https://lore.kernel.org/r/20250416-sc7280-fastrpc-dma-v1-1-60ca91116b1e@radxa.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: sdx75-idp: Enable QPIC BAM & QPIC NAND supportKaushal Kumar
Enable QPIC BAM and QPIC NAND devicetree nodes for Qualcomm SDX75-IDP board. Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415072756.20046-6-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-19arm64: dts: qcom: sdx75: Add QPIC NAND supportKaushal Kumar
Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250415072756.20046-5-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-29 05:15:12 +0000