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path: root/drivers/clk/rockchip
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2025-01-09clk: rockchip: rk3588: make refclko25m_ethX criticalHeiko Stuebner
Ethernet phys normally need a 25MHz refclk input. On a lot of boards this is done with a dedicated 25MHz crystal. But the rk3588 CRU also provides a means for that via the refclko25m_ethX clock outputs that can be used for that function. The mdio bus normally probes devices on the bus at runtime, by reading specific phy registers. This requires the phy to be running and thus also being supplied by its reference clock. While there exist the possibility and dt-binding to declare these input clocks for each phy in the phy-dt-node, this is only relevant _after_ the phy has been detected and during the drivers probe-run. This results in a chicken-and-egg-problem. The refclks in the CRU are running on boot of course, but phy-probing can very well happen after clk_disable_unused has run. In the past I tried to make clock-handling part of the mdio bus code [0] but that wasn't very well received, due to it being specific to OF and clocks with the consensus being that resources needed for detection need to be enabled before. So to make probing ethernet phys using the internal refclks possible, make those 2 clocks critical. [0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/ Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: rk3588: drop RK3588_LINKED_CLKSebastian Reichel
With the proper GATE_LINK support, we no longer need to keep the linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL flag for them. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: implement linked gate clock supportSebastian Reichel
Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These clock gates will only have a running output clock when all of the following conditions are met: 1. the parent clock is enabled 2. the enable bit is set correctly 3. the linked clock is enabled To handle them this code registers them as a normal gate type clock, which takes care of condition 1 + 2. The linked clock is handled by using runtime PM clocks. Handling it via runtime PM requires setting up a struct device for each of these clocks with a driver attached to use the correct runtime PM operations. Thus the complete handling of these clocks has been moved into its own driver. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: expose rockchip_clk_set_lookupSebastian Reichel
Move rockchip_clk_add_lookup to clk.h, so that it can be used by sub-devices with their own driver. These might also have to do a lookup, so rename the function to rockchip_clk_set_lookup and add a matching rockchip_clk_get_lookup. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: rk3588: register GATE_LINK laterSebastian Reichel
The proper GATE_LINK implementation will use runtime PM to handle the linked gate clocks, which requires device context. Currently all clocks are registered early via CLK_OF_DECLARE, which is before the kernel knows about devices. Moving the full clocks registration to the probe routine does not work, since the clocks needed for timers must be registered early. To work around this issue, most of the clock tree is registered early, but GATE_LINK clocks are handled in the probe routine. Since the resets are not needed early either, they have also been moved to the probe routine. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241211165957.94922-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09clk: rockchip: support clocks registered lateSebastian Reichel
When some clocks are registered late and some clocks are registered early we need to make sure the late registered clocks report probe defer until the final registration has happened. But we do not want to keep reporting probe defer after the late registration has happened. Also not all Rockchip SoCs have late registered clocks and may not need to report probe defer at all. This restructures code a bit, so that there is a new function rockchip_clk_init_early(), which should be used for initializing the CRU structure on SoCs making use of late initialization in addition to the early init. These platforms should call rockchip_clk_finalize() once all clocks have been registered. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function] Link: https://lore.kernel.org/r/20241211165957.94922-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-09clk: rockchip: fix finding of maximum clock IDYao Zi
If an ID of a branch's child is greater than current maximum, we should set new maximum to the child's ID, instead of its parent's. Fixes: 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage") Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20240912133204.29089-2-ziyao@disroot.org Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-09clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitionsArnd Bergmann
When -Wunused-const-variable is enabled (not the default), there is a warning about two definitions in this file: In file included from drivers/clk/rockchip/clk-rk3576.c:14: drivers/clk/rockchip/clk-rk3576.c:334:7: error: 'mclk_pdm0_p' defined but not used [-Werror=unused-const-variable=] 334 | PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; | ^~~~~~~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ drivers/clk/rockchip/clk-rk3576.c:333:7: error: 'pdm0_p' defined but not used [-Werror=unused-const-variable=] 333 | PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; | ^~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 | #define PNAME(x) static const char *const x[] __initconst | ^ Remove them for the moment. If they are needed later, they can be added back at that point. Fixes: cc40f5baa91b ("clk: rockchip: Add clock controller for the RK3576") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240909121116.254036-1-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-30clk: rockchip: fix error for unknown clocksSebastian Reichel
There is a clk == NULL check after the switch to check for unsupported clk types. Since clk is re-assigned in a loop, this check is useless right now for anything but the first round. Let's fix this up by assigning clk = NULL in the loop before the switch statement. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure for clock branches") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added fixes + stable-cc] Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-30clk: rockchip: rk3588: drop unused codeSebastian Reichel
All clocks are registered early using CLK_OF_DECLARE(), which marks the DT node as processed. For the processed DT node the probe routine is never called. Thus this whole code is never executed. This could be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the DT node as processed. But then the probe routine would re-register all the clocks by calling rk3588_clk_init() again. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: rockchip: Add clock controller for the RK3576Elaine Zhang
Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com [dropped additional blank line at EOF in rst-rk3576.c dropped the whole (non-)working as module part] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: rockchip: Add new pll type pll_rk3588_ddrElaine Zhang
That PLL type is similar to the other rk3588 pll types but the actual rate is twice the configured rate. Therefore, the returned calculated rate must be multiplied by two. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan
The 32kHz input clock is named "xin32k" in the driver, so the name "32k" appears to be a typo in this case. Lets fix this. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/45f83b1f-64f8-4ea5-bc93-ebf7507a9709@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2a19c3cc-5f4d-4d03-90b2-e0bb13b0502f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3328: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/38ea6be0-3596-49ec-8de9-aef9c7f2bbb6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3308: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/9fbca2d8-f904-4913-ba05-8715e748a454@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3288: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/af141286-7994-4e3f-93e2-6ee4e718ef8a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3228: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2ee6f0a5-a1bb-4b62-ae6b-8f3828f8eccc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: rk3036: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/c8e73847-f472-4473-ac55-068cb28b98f6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/5ad12808-61f5-4e3b-801e-85231375b6a6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-07-29clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman
Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically parented by the hdmiphy clk and it is expected that the DCLK_VOP and hdmiphy clk rate are kept in sync. Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used on RK3328, to make full use of all possible supported display modes. Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP") Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-27clk: rockchip: rk3188: Drop CLK_NR_CLKS usageJohan Jonker
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/1cd309fa-a4d3-4283-aa47-1330a40448a7@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-23clk: rockchip: Switch to use kmemdup_array()Andy Shevchenko
Let the kememdup_array() take care about multiplication and possible overflows. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240606161028.2986587-3-andriy.shevchenko@linux.intel.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-23clk: rockchip: rk3128: Add HCLK_SFCAlex Bee
The SFC IP exists only in RK3128 version of the SoC, thus the clock gets added to rk3128_clk_branches. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240606143401.32454-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-06-08clk: rockchip: rk3128: Drop CLK_NR_CLKS usageAlex Bee
In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240606143401.32454-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-05-28clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocksAlex Bee
The DSI controller needs this clock to be enabled in order to be able to access the registers. Make it critical for that purpose. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240509140653.168591-5-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-05-28clk: rockchip: rk3128: Export PCLK_MIPIPHYAlex Bee
Export the D-DHY's APB clock for usage in the DT. Also drop the CLK_IGNORE_UNUSED-flag, as the clock will be enabled on demand. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240509140653.168591-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-05-04clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach
This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-05-04clk: rockchip: Remove an unused field in struct rockchip_mmc_clockChristophe JAILLET
In "struct rockchip_mmc_clock", the 'id' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/410bc0f86c7b9f1c80f8a4e9a2a028a9a6ee1ec0.1713970085.git.christophe.jaillet@wanadoo.fr Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-04-10clk: rockchip: rk3588: Add reset line for HDMI ReceiverShreeya Patel
Export hdmirx_biu reset line required by the Synopsys DesignWare HDMIRX Controller. Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-04-10clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander
The USB480M clock can source from a MUX that selects the clock to come from either of the USB-phy internal 480MHz PLLs. These clocks are provided by the USB phy driver. Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20240405-clk-rk3568-usb480m-phy-mux-v1-2-6c89de20a6ff@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-27clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parentOndrej Jirman
Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires setting high divider value on clk_i2s0_div, and then muxes back to clk_i2s0_frac, clk_i2s0_frac would have no way to change the clk_i2s0_div's divider ratio back to 1 so that it can satisfy the condition for m/n > 20 for fractional division to work correctly. Bug is reproducible by playing 44.1k audio, then 48k audio, and then 44.1k audio again. This results in clk_i2s0_div being set to 49 and clk_i2s0_frac not being able to cope with such a low input clock rate and audio playing extremely slowly. The identical issue is on i2s1 and i2s2 clocks, too. Signed-off-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20240217193439.1762213-1-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-27clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel
In preparation for properly supporting GATE_LINK switch the unused linked clock argument from the clock's name to its ID. This allows easy and fast lookup of the 'struct clk'. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-27clk: rockchip: rk3588: fix indentSebastian Reichel
pclk_mailbox2 is the only RK3588 clock indented with one tab instead of two tabs. Let's fix this. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-27clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel
Currently pclk_vo1grf is not exposed, but it should be referenced from the vo1_grf syscon, which needs it enabled. That syscon is required for HDMI RX and TX functionality among other things. Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates and need the VO's hclk enabled in addition to their parent clock. No Fixes tag has been added, since the logic requiring these clocks is not yet upstream anyways. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-02-27Merge branch 'v6.9-shared/clkids' into v6.9-clk/nextHeiko Stuebner
2024-02-27clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel
CLK_NR_CLKS is not part of the DT bindings and needs to be removed from it, just like it recently happened for other platforms. This takes care of it by introducing a new function identifying the maximum used clock ID at runtime. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-25clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan
Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC series to run at 60hz. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20240123212111.202146-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2023-12-05clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan
In the reference manual under "2.8.6 NIU Clock gating reliance" it is stated that pclk_usb_niu has a dependency on hclk_usb_niu. While the manual does not state that this is a bi-directional relationship it was noted that the sdmmc2 failed to operate for me in mmc mode if the pclk_usb was not marked as critical. The parent clock of the hclk_sdmmc2 is hclk_usb. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231204185719.569021-8-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-05clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan
Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel can run at a requested 60hz. I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-28clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee
SCLK_SDMMC is the parent for SCLK_SDMMC_DRV and SCLK_SDMMC_SAMPLE, but used with the (more) correct name sclk_sdmmc. SD card tuning does currently fail as the parent can't be found under that name. There is no need to suffix the name with '0' since RK312x SoCs do have a single sdmmc controller - so rename it to the name which is already used by it's children. Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-28clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao
According to the TRM there are no specific gpll_peri, cpll_peri, gpll_div2_peri or gpll_div3_peri gates, but a single clk_peri_src gate. Instead mux_clk_peri_src directly connects to the plls respectively the pll divider clocks. Fix this by creating a single gated composite. Also rename all occurrences of aclk_peri_src to clk_peri_src, since it is the parent for peri aclks, pclks and hclks. That name also matches the one used in the TRM. Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128") Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [renamed aclk_peri_src -> clk_peri_src and added commit message] Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231127181415.11735-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-16clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li
The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON. Signed-off-by: Weihao Li <cn.liweihao@gmail.com> Link: https://lore.kernel.org/r/20231031111816.8777-1-cn.liweihao@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-16clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan
Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel can run at a requested 60hz (59.96, close enough). I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-11-16clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan
Add support for a PLL rate of 115.2MHz so that the Powkiddy RK2023 panel can run at a requested 60hz (59.99, close enough). I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20231018161848.346947-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-23clk: Use device_get_match_data()Rob Herring
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231006213959.334439-1-robh@kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #msm part Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # Samsung Acked-by: David Lechner <david@lechnology.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd
'clk-rockchip' into clk-next - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-08-10clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki
PD_VO clock tree diagram in RV1126 is connected to - BIU_VO - VOP - RGA - IEP - DSIHOST Add entire PD_VO clock tree for rv1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230731110012.2913742-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2025-07-29 09:21:19 +0000