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2020-01-20clk: ti: dra7: fix parent for gmac_clkctrlGrygorii Strashko
The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation. Hence, fix it. Fixes: dffa9051d546 ('clk: ti: dra7: add new clkctrl data') Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-20clk: ti: dra7: add vpe clkctrl dataBenoit Parrot
Add clkctrl data for VPE. Signed-off-by: Benoit Parrot <bparrot@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-20clk: ti: dra7: add cam clkctrl dataBenoit Parrot
Add clkctrl data for CAM domain. Signed-off-by: Benoit Parrot <bparrot@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-01-16Merge tag 'armsoc-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Olof Johansson: "I've been sitting on these longer than I meant, so the patch count is a bit higher than ideal for this part of the release. There's also some reverts of double-applied patches that brings the diffstat up a bit. With that said, the biggest changes are: - Revert of duplicate i2c device addition on two Aspeed (BMC) Devicetrees. - Move of two device nodes that got applied to the wrong part of the tree on ASpeed G6. - Regulator fix for Beaglebone X15 (adding 12/5V supplies) - Use interrupts for keys on Amlogic SM1 to avoid missed polls In addition to that, there is a collection of smaller DT fixes: - Power supply assignment fixes for i.MX6 - Fix of interrupt line for magnetometer on i.MX8 Librem5 devkit - Build fixlets (selects) for davinci/omap2+ - More interrupt number fixes for Stratix10, Amlogic SM1, etc. - ... and more similar fixes across different platforms And some non-DT stuff: - optee fix to register multiple shared pages properly - Clock calculation fixes for MMP3 - Clock fixes for OMAP as well" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits) MAINTAINERS: Add myself as the co-maintainer for Actions Semi platforms ARM: dts: imx7: Fix Toradex Colibri iMX7S 256MB NAND flash support ARM: dts: imx6sll-evk: Remove incorrect power supply assignment ARM: dts: imx6sl-evk: Remove incorrect power supply assignment ARM: dts: imx6sx-sdb: Remove incorrect power supply assignment ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL ARM: omap2plus: select RESET_CONTROLLER ARM: davinci: select CONFIG_RESET_CONTROLLER ARM: dts: aspeed: rainier: Fix fan fault and presence ARM: dts: aspeed: rainier: Remove duplicate i2c busses ARM: dts: aspeed: tacoma: Remove duplicate flash nodes ARM: dts: aspeed: tacoma: Remove duplicate i2c busses ARM: dts: aspeed: tacoma: Fix fsi master node ARM: dts: aspeed-g6: Fix FSI master location ARM: dts: mmp3: Fix the TWSI ranges clk: mmp2: Fix the order of timer mux parents ARM: mmp: do not divide the clock rate arm64: dts: rockchip: Fix IR on Beelink A1 optee: Fix multi page dynamic shm pool alloc ...
2020-01-13Merge tag 'sunxi-clk-fixes-for-5.5' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clk fixes from Maxime Ripard: Our usual set of fixes for Allwinner, to fix the number of reported clocks on the v3s, fixing the external clock on the R40, and some fixes for the AR100 co-processor clocks. * tag 'sunxi-clk-fixes-for-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs clk: sunxi-ng: v3s: Fix incorrect number of hw_clks.
2020-01-12clk: imx: Add support for i.MX8MP clock driverAnson Huang
Add clock driver support for i.MX8MP which is a new SoC of i.MX8M family. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-12clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang
Switch the imx_clk_gate4_flags() function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko
The VDE parent won't be changed automatically to PLLC if bootloader didn't do that for us, hence let's explicitly set the parent for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko
Both Tegra20 and Tegra30 are initializing display's parent clock incorrectly because PLLP is running at 216/408MHz while display rate is set to 600MHz, but pre-setting the parent isn't needed at all because display driver selects proper parent anyways. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10clk: tegra: divider: Check UART's divider enable-bit state on rate's ↵Dmitry Osipenko
recalculation UART clock is divided using divisor values from DLM/DLL registers when enable-bit is unset in clk register and clk's divider configuration isn't taken onto account in this case. This doesn't cause any problems, but let's add a check for the divider's enable-bit state, for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni
pm_runtime_irq_safe() is not needed as interrupts are allowed during suspend and resume. This was added mistakenly during DFLL suspend and resume support patch. While at it, also update the description of the dev argument that is passed to the tegra_dfll_suspend() function. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09clk: qcom: Add ipq6018 Global Clock Controller supportSricharan R
This patch adds support for the global clock controller found on the ipq6018 based devices. Also fixed the sparse warnings reported by, Reported-by: kbuild test robot <lkp@intel.com> Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lkml.kernel.org/r/1578557121-423-3-git-send-email-sricharan@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-08Merge tag 'cpuidle_psci-v5.5-rc4' of ↵Olof Johansson
git://git.linaro.org/people/ulf.hansson/linux-pm into arm/drivers Initial support for hierarchical CPU arrangement, managed by PSCI and its corresponding cpuidle driver. This support is based upon using the generic PM domain, which already supports devices belonging to CPUs. Finally, these is a DTS patch that enables the hierarchical topology to be used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated mode. * tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm: (611 commits) arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 cpuidle: psci: Add support for PM domains by using genpd PM / Domains: Introduce a genpd OF helper that removes a subdomain cpuidle: psci: Support CPU hotplug for the hierarchical model cpuidle: psci: Manage runtime PM in the idle path cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains cpuidle: psci: Attach CPU devices to their PM domains cpuidle: psci: Add a helper to attach a CPU to its PM domain cpuidle: psci: Support hierarchical CPU idle states cpuidle: psci: Simplify OF parsing of CPU idle state nodes cpuidle: dt: Support hierarchical CPU idle states of: base: Add of_get_cpu_state_node() to get idle states for a CPU node firmware: psci: Export functions to manage the OSI mode dt: psci: Update DT bindings to support hierarchical PSCI states cpuidle: psci: Align psci_power_state count with idle state count Linux 5.5-rc4 locks: print unsigned ino in /proc/locks riscv: export flush_icache_all to modules riscv: reject invalid syscalls below -1 riscv: fix compile failure with EXPORT_SYMBOL() & !MMU ... Link: https://lore.kernel.org/r/20200102160820.3572-1-ulf.hansson@linaro.org Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren
For a little over a year, U-Boot on Tegra124 has configured the flow controller to perform automatic RAM re-repair on off->on power transitions of the CPU rail[1]. This is mandatory for correct operation of Tegra124. However, RAM re-repair relies on certain clocks, which the kernel must enable and leave running. The fuse clock is one of those clocks. Mark this clock as critical so that LP1 power mode (system suspend) operates correctly. [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Cc: stable@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-08clk: renesas: Prepare for split of R-Car H3 config symbolGeert Uytterhoeven
Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers. Hence the SoC configuration symbol will be split in two separate config symbols. As the Clock Pulse Generator / Module Standby and Software Reset blocks in both SoCs are very similar, they will keep on sharing a driver. Extend the dependency of CONFIG_CLK_R8A7795, to prepare for the split. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20191230080902.2832-1-geert+renesas@glider.be
2020-01-07clk: divider: Add support for specifying parents via DT/pointersStephen Boyd
After commit fc0c209c147f ("clk: Allow parents to be specified without string names") we can use DT or direct clk_hw pointers to specify parents. Create a generic function that shouldn't be used very often to encode the multitude of ways of registering a divider clk with different parent information. Then add a bunch of wrapper macros that only pass down what needs to be passed down to the generic function to support this with less arguments. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-13-sboyd@kernel.org [sboyd@kernel.org: Export __clk_hw_register_divider]
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. This fixes a potential hang when changing the GPU frequency at runtime. Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-01-06clk: gate: Add support for specifying parents via DT/pointersStephen Boyd
After commit fc0c209c147f ("clk: Allow parents to be specified without string names") we can use DT or direct clk_hw pointers to specify parents. Create a generic function that shouldn't be used very often to encode the multitude of ways of registering a gate clk with different parent information. Then add a bunch of wrapper macros that only pass down what needs to be passed down to the generic function to support this with less arguments. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-12-sboyd@kernel.org
2020-01-06clk: mux: Add support for specifying parents via DT/pointersStephen Boyd
After commit fc0c209c147f ("clk: Allow parents to be specified without string names") we can use DT or direct clk_hw pointers to specify parents. Create a generic function that shouldn't be used very often to encode the multitude of ways of registering a mux clk with different parent information. Then add a bunch of wrapper macros that only pass down what needs to be passed down to the generic function to support this with less arguments. Note: the msm drm driver passes an anonymous array through the macro which seems to confuse my compiler. Adding a parenthesis around the whole thing at the call site seems to fix it but it must be wrong. Maybe it's better to split this patch and pick out the array bits there? Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-11-sboyd@kernel.org
2020-01-06clk: asm9260: Use parent accuracy in fixed rate clkStephen Boyd
This fixed rate clk is registered with the accuracy of the parent. Use CLK_FIXED_RATE_PARENT_ACCURACY for that instead of getting the parent clk and finding out the accuracy that way. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-10-sboyd@kernel.org
2020-01-06clk: fixed-rate: Add clk flags for parent accuracyStephen Boyd
Some clk providers want to use the accuracy of the parent clk and use the fixed rate basic type clk to do that. This requires getting the parent clk and extracting the accuracy before registering the fixed rate clk. Let's add a flag for this and update the clk_ops to support this. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-8-sboyd@kernel.org
2020-01-06clk: mmp2: Add HSIC clocksLubomir Rintel
There are two USB HSIC controllers on MMP2 and MMP3. Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06clk: mmp2: Fix the order of timer mux parentsLubomir Rintel
Determined empirically, no documentation is available. The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing what is going on, ended up just dividing the rate as of commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")' Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06clk: qcom: gcc-msm8996: Fix parent for CLKREF clocksBjorn Andersson
The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the SoC. Update the definition of these clocks to allow this to be wired up to the appropriate clock source. Retain "xo" as the global named parent to make the change a nop in the event that DT doesn't carry the necessary clocks definition. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06clk: qcom: rpmh: Add IPA clock for SC7180Taniya Das
The Qualcomm IP Accelerator (IPA) clock resource that is managed by the BCM is required by the IPA driver in order to scale its core clock. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1578305923-29125-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06clk: qcom: rpmh: skip undefined clocks when registeringTaniya Das
When iterating over a platform's available clocks in clk_rpmh_probe(), check for undefined (null) entries in the clocks array. Not all clock indexes necessarily have clocks defined. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1578305923-29125-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Leave 'name' declaration at beginning of loop] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2020-01-05clk: Add support for setting clk_rate via debugfsGeert Uytterhoeven
For testing, it is useful to be able to specify a clock rate manually. As this is a dangerous feature, it is not enabled by default. Users need to modify the source directly and #define CLOCK_ALLOW_WRITE_DEBUGFS. This follows the spirit of commit 09c6ecd394105c48 ("regmap: Add support for writing to regmap registers via debugfs"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lkml.kernel.org/r/20190828132306.19012-1-geert+renesas@glider.be Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05clk: at91: sam9x60: fix programmable clock prescalerEugen Hristev
The prescaler works as parent rate divided by (PRES + 1) (is_pres_direct == 1) It does not work in the way of parent rate shifted to the right by (PRES + 1), which means division by 2^(PRES + 1) (is_pres_direct == 0) Thus is_pres_direct must be enabled for this SoC, to make the right computation. This field was added in commit 45b06682113b ("clk: at91: fix programmable clock for sama5d2") SAM9X60 has the same field as SAMA5D2 in the PCK Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1575977088-16781-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default valueEugen Hristev
Product datasheet recommends different values for UPLL and PLLA analog control register. Adapt accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1573478913-19737-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05clk: ti: dra7-atl: Remove pm_runtime_irq_safe()Peter Ujfalusi
This is not needed for anything, and prevents proper PM transitions for parent devices which is bad in case of ti-sysc; this effectively kills PM completely. Thus, remove the flag. Suggested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lkml.kernel.org/r/20191114101718.20619-1-peter.ujfalusi@ti.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-05clk: fixed-rate: Add support for specifying parents via DT/pointersStephen Boyd
After commit fc0c209c147f ("clk: Allow parents to be specified without string names") we can use DT or direct clk_hw pointers to specify parents. Create a generic function that shouldn't be used very often to encode the multitude of ways of registering a fixed rate clk with different parent information. Then add a bunch of wrapper macros that only pass down what needs to be passed down to the generic function to support this with less arguments. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-7-sboyd@kernel.org
2020-01-05clk: fixed-rate: Move to_clk_fixed_rate() to C fileStephen Boyd
The only user of this macro is the fixed rate basic type. Move it there to avoid polluting provider drivers. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-5-sboyd@kernel.org
2020-01-05clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()Stephen Boyd
There aren't any users of this API anymore. Remove it. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-4-sboyd@kernel.org
2020-01-05clk: fixed-rate: Convert to clk_hw based APIsStephen Boyd
This code still uses struct clk to register clks from the probe path. Migrate this to the clk_hw based APIs to modernize the code. Also, this isn't a module and it can't be one because the driver is always builtin so drop the module table. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-3-sboyd@kernel.org
2020-01-05clk: gpio: Use DT way of specifying parentsStephen Boyd
Nobody has used the gpio clk registration functions nor the gpio clk_ops exposed by the basic gpio clk type. Let's remove all those APIs and move the gpio clk support into the C file. Since nothing is using the exported APIs, simplify the driver to be a platform driver that uses clk_parent_data to pick 0th or 1st cell of the node's clocks property. Cc: Simon Horman <horms@verge.net.au> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190830150923.259497-2-sboyd@kernel.org
2020-01-05clk: qcom: gcc-sdm845: Add missing flag to votable GDSCsGeorgi Djakov
On sdm845 devices, during boot we see the following warnings (unless we have added 'pd_ignore_unused' to the kernel command line): hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on' hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on' hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on' hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on' As the name of these GDSCs suggests, they are "votable" and in downstream DT, they all have the property "qcom,no-status-check-on-disable", which means that we should not poll the status bit when we disable them. Luckily the VOTABLE flag already exists and it does exactly what we need, so let's make use of it to make the warnings disappear. Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Reported-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.org Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: Fix Kconfig indentationKrzysztof Kozlowski
Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lkml.kernel.org/r/1574306335-29026-1-git-send-email-krzk@kernel.org [sboyd@kernel.org: Fixup mediatek to have two spaces for help indent] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: ux500: Fix up the SGA clock for some variantsLinus Walleij
Some of the special PRCMU firmware variants were not properly detected in the Ux500 clock driver, resulting in the wrong clock for the SGA. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20191217210504.27888-1-linus.walleij@linaro.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: qcom: Add video clock controller driver for SC7180Taniya Das
Add support for the video clock controller found on SC7180 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1577428714-17766-7-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: qcom: Add graphics clock controller driver for SC7180Taniya Das
Add support for the graphics clock controller found on SC7180 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1577428714-17766-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: Warn about critical clks that fail to enableStephen Boyd
If we don't warn here users of the CLK_IS_CRITICAL flag may not know that their clk isn't actually enabled because it silently fails to enable. Let's print a warning in that case so developers find these problems faster. Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200102005503.71923-1-sboyd@kernel.org Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
2020-01-04clk: qcom: apcs-msm8916: use clk_parent_data to specify the parentNiklas Cassel
Allow accessing the parent clock names required for the driver operation by using the device tree 'clock-names' property, while falling back to the previous method of using names in the global name space. This permits extending the driver to other platforms without having to modify its source code. Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Link: https://lkml.kernel.org/r/20200103111429.1347-1-nks@flawful.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04clk: uniphier: Add SCSSI clock gate for each channelKunihiko Hayashi
SCSSI has clock gates for each channel in the SoCs newer than Pro4, so this adds missing clock gates for channel 1, 2 and 3. And more, this moves MCSSI clock ID after SCSSI. Fixes: ff388ee36516 ("clk: uniphier: add clock frequency support for SPI") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-04Merge branch 'clk-register-dt-node-better' into clk-qcomStephen Boyd
* clk-register-dt-node-better: clk: Use parent node pointer during registration if necessary
2020-01-04clk: Use parent node pointer during registration if necessaryStephen Boyd
Sometimes clk drivers are attached to devices which are children of a parent device that is connected to a node in DT. This happens when devices are MFD-ish and the parent device driver mostly registers child devices to match against drivers placed in their respective subsystem directories like drivers/clk, drivers/regulator, etc. When the clk driver calls clk_register() with a device pointer, that struct device pointer won't have a device_node associated with it because it was created purely in software as a way to partition logic to a subsystem. This causes problems for the way we find parent clks for the clks registered by these child devices because we look at the registering device's device_node pointer to lookup 'clocks' and 'clock-names' properties. Let's use the parent device's device_node pointer if the registering device doesn't have a device_node but the parent does. This simplifies clk registration code by avoiding the need to assign some device_node to the device registering the clk. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reported-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191230190455.141339-1-sboyd@kernel.org [sboyd@kernel.org: Fixup kernel-doc notation] Reviewed-by: Niklas Cassel <nks@flawful.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-04clk: sunxi: a23/a33: Export the MIPI PLLMaxime Ripard
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings headers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04clk: sunxi: a31: Export the MIPI PLLMaxime Ripard
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings headers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick
Export CLK_CPUX so we can reference it in CPU node. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-01-04clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng
The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU clock to workaround the problem. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
generated by cgit (git 2.34.1) at 2025-09-10 17:22:18 +0000