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path: root/drivers/clk
AgeCommit message (Expand)Author
2018-03-12Merge branch 'clk-helpers' (early part) into clk-fixesStephen Boyd
2018-03-12clk: qcom: use divider_ro_round_rate helperJerome Brunet
2018-03-12clk: divider: read-only divider can propagate rate changeJerome Brunet
2018-03-12clk: call the clock init() callback before any other ops callbackJerome Brunet
2018-03-12clk: mux: add helper function for index/value translationJerome Brunet
2018-03-12clk: divider: export clk_div_mask() helperJerome Brunet
2018-03-12clk: fix determine rate error with pass-through clockJerome Brunet
2018-03-12Merge branch 'clk-phase' into clk-fixesStephen Boyd
2018-03-12Merge tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm into cl...Stephen Boyd
2018-03-12Merge tag 'clk-imx-fixes-4.16' of git://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd
2018-03-12Merge tag 'sunxi-clk-fixes-for-4.16' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd
2018-03-12clk: migrate the count of orphaned clocks at initJerome Brunet
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2018-03-12clk: samsung: exynos5420: Add more entries to EPLL rate tableSylwester Nawrocki
2018-03-12clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clkSylwester Nawrocki
2018-03-12clk: hi3798cv200: add emmc sample and drive clocktianshuliang
2018-03-12clk: hisilicon: add hisi phase clock supporttianshuliang
2018-03-11clk: update cached phase to respect the fact when setting phaseShawn Lin
2018-03-11clk: stm32mp1: add Debug clocksGabriel Fernandez
2018-03-11clk: stm32mp1: add MCO clocksGabriel Fernandez
2018-03-11clk: stm32mp1: add RTC clockGabriel Fernandez
2018-03-11clk: stm32mp1: add Peripheral & Kernel ClocksGabriel Fernandez
2018-03-11clk: stm32mp1: add Kernel timersGabriel Fernandez
2018-03-11clk: stm32mp1: add Sub System clocksGabriel Fernandez
2018-03-11clk: stm32mp1: add Post-dividers for PLLGabriel Fernandez
2018-03-11clk: stm32mp1: add PLL clocksGabriel Fernandez
2018-03-11clk: stm32mp1: add Source Clocks for PLLsGabriel Fernandez
2018-03-11clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillatorsGabriel Fernandez
2018-03-11clk: stm32mp1: Introduce STM32MP1 clock driverGabriel Fernandez
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver
2018-03-08clk: ti: am43xx: add set-rate-parent support for display clkctrl clockTero Kristo
2018-03-08clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flagTero Kristo
2018-03-08clk: ti: am33xx: add set-rate-parent support for display clkctrl clockTero Kristo
2018-03-08clk: keystone: sci-clk: add support for dynamically probing clocksTero Kristo
2018-03-08clk: ti: add support for clock latching to mux clocksTero Kristo
2018-03-08clk: ti: add support for clock latching to divider clocksTero Kristo
2018-03-08clk: ti: add generic support for clock latchingTero Kristo
2018-03-08clk: ti: add support for register read-modify-write low-level operationTero Kristo
2018-03-06clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski
2018-03-06clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMUMarek Szyprowski
2018-03-06clk: samsung: Add Exynos5 sub-CMU clock driverMarek Szyprowski
2018-03-05clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin
2018-03-02clk: rockchip: Free the memory on the error pathShawn Lin
2018-03-02clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEOJernej Skrabec
2018-03-02clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec