| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-08-20 | RISC-V: Remove CLINT related code from timer and arch | Anup Patel |
| 2020-06-09 | clocksource/drivers/timer-riscv: Use per-CPU timer interrupt | Anup Patel |
| 2020-01-04 | clocksource: riscv: add notrace to riscv_sched_clock | Zong Li |
| 2019-11-13 | riscv: add support for MMIO access to the timer registers | Christoph Hellwig |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
| 2019-09-05 | riscv: don't use the rdtime(h) pseudo-instructions | Christoph Hellwig |
| 2019-08-06 | RISC-V: Remove per cpu clocksource | Atish Patra |
| 2019-03-23 | clocksource/drivers/riscv: Fix clocksource mask | Atish Patra |
| 2019-02-23 | clocksource/drivers/riscv: Add required checks during clock source init | Atish Patra |
| 2018-12-18 | clocksource/drivers/riscv: Change name riscv_timer to timer-riscv | Daniel Lezcano |
