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path: root/drivers/gpu/drm
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2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU.Francisco Jerez
Sleeping doesn't pay off for very short delays in comparison with the minimum granularity of schedule_timeout(). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Use WC memory on the AGP GART.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez
There have been reports of PFIFO cache errors during context take down (fdo bug 31637). They are caused by some GPU objects being taken out while the channel is still potentially processing commands. Make sure that all the previous rendering has landed before releasing a GPU object. Reported-by: Grzesiek Sójka <pld@pfu.pl> Reported-by: Patrice Mandin <patmandin@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.Francisco Jerez
nvxx_graph_isr is already taking care of it. In some cases this could've made you miss PGRAPH interrupts (e.g. when you were supposed to get several IRQs of the same kind in a row). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez
No functional changes, just simplify some code paths a bit. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/radeon/kms: fix vram base calculation on rs780/rs880Alex Deucher
Avoid overflowing a 32 bit value. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/radeon/kms: fix formatting of vram and gtt infoAlex Deucher
print the full 64 bit values. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/radeon/kms: forbid big bo allocation (fdo 31708) v3Jerome Glisse
Forbid allocating buffer bigger than visible VRAM or GTT, also properly set lpfn field. v2 - use max macro - silence warning v3 - don't explicitly set range limit - use min macro Cc: stable <stable@kernel.org> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm: Don't try and disable an encoder that was never enabledChris Wilson
Prevents code that assumes that the encoder is active when asked to be disabled from dying a horrible death. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm: Add missing drm_vblank_put() along queue vblank error pathChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-07drm/i915: Disable renderctx powersaving support for IronlakeChris Wilson
... still causes a failure during suspend. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_dp.c
2010-12-07drm/i915/dp: Only apply the workaround if the select is still activeChris Wilson
As we may try to power down the link at various times, it is not necessarily still coupled with an encoder and so we must be careful not to depend upon an operation that is only valid when the link is still attached to a pipe. Fixes regression in 5bddd17. Reported-and-tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org [after applying 5bddd17]
2010-12-07drm/i915: Emit a request to clear a flushed and idle ring for unbusy boChris Wilson
In order for bos to retire eventually, a request must be sent down the ring. This is expected, for example, by occlusion queries for which mesa will wait upon (whilst running glean) before issuing more batches and so the normal activity upon the ring is suspended and we need to emit a request to clear the idle ring. Reported-by: Jinjin, Wang <jinjin.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30380 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Wait for the bo if a display flip is pipelined on the other ringChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Only emit a flush if there is an outstanding gpu writeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Completely disable fence pipelining.Chris Wilson
I'm still seeing tiling corruption of PutImage and CopyArea (I think) under mutter on pnv, so obviously the pipelining logic is deeply flawed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Uncouple render/power ctx before suspendingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Ignore fenced commands for gpu access on gen4Chris Wilson
Userspace should not have been declaring that it needed fenced GPU access with gen4+ as those GPUs have no fenced commands, but to be on the safe side it is easier to ignore userspace in case they did. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Power Context register is only available for gen4 mobilesChris Wilson
The ability to save the hardware context upon powering down the render clock through PWRCTXA is only available on a couple of gen4 chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Avoid using PIPE_CONTROL on IronlakeChris Wilson
The workaround is hideous and we are using the STORE_DWORD on all other generations on all other rings, so use for the gen5 render ring as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915/lvds: Always restore panel-fitter when enabling the LVDSChris Wilson
Linus Torvalds pointed out that our code was unbalanced when powering on the panel with respect to the power off sequence in that we were failing to restore the panel-fitter. The consequence of this would be that across a simple DPMS off/on for a non-native mode, without an intervening modeset, the panel fitter would remain disabled and the output would shift on the panel. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915/ringbuffer: Only print an error on the second attempt to reset headChris Wilson
There's not much we can do here but hope for the best. However the first failure happens quite frequently and if often remedied by the second attempt to reset HEAD. So only print the error if that attempt also fails. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=19802 Reported-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-05drm/i915/dp: Trivial code tidyChris Wilson
Locally scope the crtc to where it is used. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
2010-12-05drm/i915: announce to userspace that the bsd ring is coherentDaniel Vetter
Otherwise we can't really fix the abi-braindeadness of forcing libva to manually wait for rendering when switching rings. Which in turn makes implementing hw semaphores a pointless exercise (at least for ironlake). [Also added the relaxed fencing param to explain the jump in numbering - relaxed fencing is in -next.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
2010-12-05drm/i915: Enable self-refresh for IronlakeChris Wilson
We disabled this a while ago as it was inexplicably broken. However, it now appears to work... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNBChris Wilson
The bulk of the change is to convert the growing list of rings into an array so that the relationship between the rings and the semaphore sync registers can be easily computed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Be paranoid and bail on resetting if we can't take the lock.Chris Wilson
This will declare the machine wedged, but is better than truly wedging the machine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Allow LVDS to be on pipe A for Ironlake+Chris Wilson
Previously we enabled this for gen4, only to have to revert it due to it causing a large number of spurious wakeups. Try again hoping that the hardware has become more sane in the mean time... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Re-enable RC6 for power-savings.Chris Wilson
Let's see if we've successfully cleared up all the bugs from last time... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Enable CB tuning of the Display PLLChris Wilson
Magic numbers from the specs. This is supposed to allow the PLL some variance to improve jitter performance and VCO headroom across manufacturing and environmental variations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Explain why we need to write DPLL twiceChris Wilson
... it's because setting the Pixel Multiply bits only takes effect once the PLL is enabled and stable. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915/lvds: Connect the PWM to the LVDS pipeChris Wilson
... and do not just assume to always use pipe B. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-04drm/i915: Factor in pixel-repeat in FDI M/N calculationChris Wilson
Fixes the modesetting on the secondary panel of the Libretto W100 and presumably many more Ironlake laptops with SDVO LVDS displays. Reported-and-tested-by: Matthew Willoughby <mattfredwill@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-03drm/i915: Death to the unnecessary 64bit divideChris Wilson
Use the hardware DDA to calculate the ratio with as much accuracy as is possible. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-03drm/i915: Clean conflicting modesetting registers upon initChris Wilson
If we leave the registers in a conflicting state then when we attempt to teardown the active mode, we will not disable the pipes and planes in the correct order -- leaving a plane reading from a disabled pipe and possibly leading to undefined behaviour. Reported-and-tested-by: Andy Whitcroft <apw@canonical.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32078 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-03drm/nouveau: fabricate DCB encoder table for iMac G4Francisco Jerez
In typical Apple fashion there's no standard information about what encoders are present on this machine, this patch adds a quirk to provide it. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: remove some useless GETPARAMsBen Skeggs
These have been unused since UMS support was ripped out, so lets remove them completely. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nv84: fix minor issues in PCRYPT implementationBen Skeggs
Fix running of destroy_context() when create_context() has never been called for the channel, and fill in engine's tlb_flush() function pointer. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nv50: fix 0x100c90 init for NVAFBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nv50: allocate page for unknown PFB object in nv50_fb.cBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-03drm/nv50: rework PGPIO IRQ handling and hotplug detectionBen Skeggs
Allows callers to install their own handlers for when a GPIO line changes state (such as for hotplug detect). This also fixes a bug where we weren't acknowledging the GPIO IRQ until after the bottom half had run, causing a severe IRQ storm in some cases. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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