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path: root/drivers/mmc/host
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2018-07-16mmc: sdhci-of-arasan: Add quirk for unstable clocksHelmut Grohne
Some controllers immediately report SDHCI_CLOCK_INT_STABLE after enabling the clock even when the clock is not stable. When used in conjunction with older/slower cards, this can result in: mmc0: error -84 whilst initialising SD card When the stable reporting is known to be broken, we simply wait for the maximum stabilization period. Signed-off-by: Helmut Grohne <h.grohne@intenta.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-pci: Add support for Intel ICPAdrian Hunter
Add PCI Ids for Intel ICP. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: host: Register changes for sdcc V5Sayali Lokhande
Add support to use the new compatible string "qcom,sdhci-msm-v5". Based on the msm variant, pick the relevant variant data and use it for register read/write to msm specific registers. Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-msm: Add msm version specific ops and data structuresVijay Viswanath
In addition to offsets of certain registers changing, the registers in core_mem have been shifted to HC mem as well. To access these registers, define msm version specific functions. These functions can be loaded into the function pointers at the time of probe based on the msm version detected. Also defind new data structure to hold version specific Ops and register addresses. Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: sdhci-msm: Define new Register address mapSayali Lokhande
For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. Define a new data structure where we can statically define the address offsets for the registers in different SDCC versions. Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: renesas_sdhi: add eMMC HS400 mode supportMasaharu Hayakawa
This patch adds processing for selecting HS400 mode. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tmio: add eMMC HS400 mode supportMasaharu Hayakawa
This patch adds processing for selecting HS400 mode. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: dw_mmc-exynos: fix potential external abort in resume_noirq()Marek Szyprowski
dw_mci_exynos_resume_noirq() performs DWMMC register access without ensuring that respective clocks are enabled. This might cause external abort on some systems (observed on Exynos5433 based boards). Fix this by forcing a PM runtime active state before register access. Using SET_NOIRQ_SYSTEM_SLEEP_PM_OPS allows also to cleanup conditional code a bit. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16mmc: tegra: Use sdhci_pltfm_clk_get_max_clockAapo Vienamo
The sdhci get_max_clock callback is set to sdhci_pltfm_clk_get_max_clock and tegra_sdhci_get_max_clock is removed. It appears that the shdci-tegra specific callback was originally introduced due to the requirement that the host clock has to be twice the bus clock on DDR50 mode. As far as I can tell the only effect the removal has on DDR50 mode is in cases where the parent clock is unable to supply the requested clock rate, causing the DDR50 mode to run at a lower frequency. Currently the DDR50 mode isn't enabled on any of the SoCs and would also require configuring the SDHCI clock divider register to function properly. The problem with tegra_sdhci_get_max_clock is that it divides the clock rate by two and thus artificially limits the maximum frequency of faster signaling modes which don't have the host-bus frequency ratio requirement of DDR50 such as SDR104 and HS200. Furthermore, the call to clk_round_rate() may return an error which isn't handled by tegra_sdhci_get_max_clock. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-16Merge branch 'next_pxa_dma' into nextUlf Hansson
2018-07-09mmc: sdhci-esdhc-imx: allow 1.8V modes without 100/200MHz pinctrl statesStefan Agner
If pinctrl nodes for 100/200MHz are missing, the controller should not select any mode which need signal frequencies 100MHz or higher. To prevent such speed modes the driver currently uses the quirk flag SDHCI_QUIRK2_NO_1_8_V. This works nicely for SD cards since 1.8V signaling is required for all faster modes and slower modes use 3.3V signaling only. However, there are eMMC modes which use 1.8V signaling and run below 100MHz, e.g. DDR52 at 1.8V. With using SDHCI_QUIRK2_NO_1_8_V this mode is prevented. When using a fixed 1.8V regulator as vqmmc-supply the stack has no valid mode to use. In this tenuous situation the kernel continuously prints voltage switching errors: mmc1: Switching to 3.3V signalling voltage failed Avoid using SDHCI_QUIRK2_NO_1_8_V and prevent faster modes by altering the SDHCI capability register. With that the stack is able to select 1.8V modes even if no faster pinctrl states are available: # cat /sys/kernel/debug/mmc1/ios ... timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) ... Link: http://lkml.kernel.org/r/20180628081331.13051-1-stefan@agner.ch Signed-off-by: Stefan Agner <stefan@agner.ch> Fixes: ad93220de7da ("mmc: sdhci-esdhc-imx: change pinctrl state according to uhs mode") Cc: <stable@vger.kernel.org> # v4.13+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-05mmc: sunxi: Disable irq during pm_suspendStefan Mavrodiev
When mmc host controller enters suspend state, the clocks are disabled, but irqs are not. For some reason the irqchip emits false interrupts, which causes system lock loop. Debug log is: ... sunxi-mmc 1c11000.mmc: setting clk to 52000000, rounded 51200000 sunxi-mmc 1c11000.mmc: enabling the clock sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 6(80000146) arg 3210101 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 sunxi-mmc 1c11000.mmc: cmd 13(8000014d) arg 10000 ie 0x0000bbc6 len 0 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00000004 idi 00000000 mmc1: new DDR MMC card at address 0001 mmcblk1: mmc1:0001 AGND3R 14.6 GiB mmcblk1boot0: mmc1:0001 AGND3R partition 1 4.00 MiB mmcblk1boot1: mmc1:0001 AGND3R partition 2 4.00 MiB sunxi-mmc 1c11000.mmc: cmd 18(80003352) arg 0 ie 0x0000fbc2 len 409 sunxi-mmc 1c11000.mmc: irq: rq (ptrval) mi 00004000 idi 00000002 mmcblk1: p1 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 sunxi-mmc 1c11000.mmc: irq: rq (null) mi 00000000 idi 00000000 and so on... This issue apears on eMMC cards, routed on MMC2 slot. The patch is tested with A20-OLinuXino-MICRO/LIME/LIME2 boards. Fixes: 9a8e1e8cc2c0 ("mmc: sunxi: Add runtime_pm support") Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-03mmc: dw_mmc: fix card threshold control configurationx00270170
Card write threshold control is supposed to be set since controller version 2.80a for data write in HS400 mode and data read in HS200/HS400/SDR104 mode. However the current code returns without configuring it in the case of data writing in HS400 mode. Meanwhile the patch fixes that the current code goes to 'disable' when doing data reading in HS400 mode. Fixes: 7e4bf1bc9543 ("mmc: dw_mmc: add the card write threshold for HS400 mode") Signed-off-by: Qing Xia <xiaqing17@hisilicon.com> Cc: stable@vger.kernel.org # v4.8+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-02mmc: renesas_sdhi_internal_dmac: Cannot clear the RX_IN_USE in abortYoshihiro Shimoda
This patch is fixes an issue that the SDHI_INTERNAL_DMAC_RX_IN_USE flag cannot be cleared because tmio_mmc_core sets the host->data to NULL before the tmio_mmc_core calls tmio_mmc_abort_dma(). So, this patch clears the SDHI_INTERNAL_DMAC_RX_IN_USE in the renesas_sdhi_internal_dmac_abort_dma() anyway. This doesn't cause any side effects. Fixes: 0cbc94daa554 ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs") Cc: <stable@vger.kernel.org> # v4.17+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-07-02mmc: renesas_sdhi_internal_dmac: Fix missing unmap in error patchYoshihiro Shimoda
This patch fixes an issue that lacks the dma_unmap_sg() calling in the error patch of renesas_sdhi_internal_dmac_start_dma(). Fixes: 0cbc94daa554 ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs") Cc: <stable@vger.kernel.org> # v4.17+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-06-18mmc: pxamci: remove the dmaengine compat needRobert Jarzmik
As the pxa architecture switched towards the dmaengine slave map, the old compatibility mechanism to acquire the dma requestor line number and priority are not needed anymore. This patch simplifies the dma resource acquisition, using the more generic function dma_request_slave_channel(). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-06-12treewide: devm_kzalloc() -> devm_kcalloc()Kees Cook
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-04mmc: renesas_sdhi: really fix WP logic regressionsWolfram Sang
This reverts commit e060d376cc61 ("mmc: renesas_sdhi: fix WP detection") and adds some code to really fix the regressions. It was missed so far that Renesas R-Car instantiations of SDHI chose to disable internal WP and used the existence of "wp-gpios" to en/disable WP at all. With the first refactoring by Yamada-san with commit 2ad1db059b9a ("mmc: renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT instead of TMIO own flag"), WP was always disabled even when GPIOs were present. With Wolfram's first fix which gets now reverted, GPIOs were honored. But when not available, the fallback was to internal WP and not to disabled WP. This caused wrong WP status on uSD card slots. Restore the old behaviour now. By default, WP is disabled. When a GPIO is found, the GPIO re-enables WP. We will think about possible better ways to handle this in the future. Tested on a previously regressing Renesas Lager board (H2) and a still working Renesas Salvator-X board (M3-W). Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Cc: stable@vger.kernel.org # v4.17+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-31mmc: mvsdio: Enable MMC_CAP_ERASEUlf Hansson
There is no obvious reasons to why mvsdio shouldn't be able to support erase/trim/discard operations, hence let's set MMC_CAP_ERASE for it. Cc: Damien Thebault <damien.thebault@vitec.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Damien Thebault <damien.thebault@vitec.com>
2018-05-31mmc: mvsdio: Respect card busy time out from mmc coreUlf Hansson
Instead of using a hardcoded timeout of 5 * HZ jiffies, let's respect the command busy timeout provided by the mmc core. This make the used timeout more reliable. Cc: Damien Thebault <damien.thebault@vitec.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Damien Thebault <damien.thebault@vitec.com>
2018-05-31mmc: sdhci-msm: Remove NO_CARD_NO_RESET quirkGeorgi Djakov
Now we have a proper implementation for the power irq handling and this quirk is not needed anymore. In fact, it is causing card detection delays on apq8096 platforms and the following error is displayed: sdhci_msm 74a4900.sdhci: mmc0: pwr_irq for req: (4) timed out The quirk is forcing the controller to retain 1.8V signalling on the slot even when a new card is inserted, which is not correct. The proper behavior would be to reset the controller in order to start with 3.3V signaling. Fixes: c0309b3803fe ("mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq") Suggested-by: Vijay Viswanath <vviswana@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-30mmc: sunxi: Use ifdef rather than __maybe_unusedUlf Hansson
To be consistent with code in other mmc host drivers, convert to check the correct PM config #ifdef in favor of using __maybe_unused. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-30mmc: mxmmc: Use ifdef rather than __maybe_unusedUlf Hansson
To be consistent with code in other mmc host drivers, convert to check the correct PM config #ifdef in favor of using __maybe_unused. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-29mmc: mxmmc: include linux/highmem.hArnd Bergmann
The highmem conversion caused a build error in some configurations: drivers/mmc/host/mxcmmc.c: In function 'mxcmci_transfer_data': drivers/mmc/host/mxcmmc.c:622:10: error: implicit declaration of function 'kmap_atomic'; did you mean 'in_atomic'? [-Werror=implicit-function-declaration] This includes the correct header file. Fixes: b189e7589f6d ("mmc: mxcmmc: handle highmem pages") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-29mmc: sunxi: mark PM functions as __maybe_unusedArnd Bergmann
The newly added runtime-pm functions cause a harmless warning when CONFIG_PM is disabled: drivers/mmc/host/sunxi-mmc.c:1452:12: error: 'sunxi_mmc_runtime_suspend' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_suspend(struct device *dev) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/mmc/host/sunxi-mmc.c:1435:12: error: 'sunxi_mmc_runtime_resume' defined but not used [-Werror=unused-function] static int sunxi_mmc_runtime_resume(struct device *dev) This marks them as __maybe_unused to shut up the warning. Fixes: 9a8e1e8cc2c0 ("mmc: sunxi: Add runtime_pm support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-29mmc: au1xmmc: handle highmem pagesChristoph Hellwig
Use kmap_atomic to map the scatterlist entry before using it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-29mmc: sdhci-*: Don't emit error msg if sdhci_add_host() failsJisheng Zhang
I noticed below error msg with sdhci-pxav3 on some berlin platforms: [.....] sdhci-pxav3 f7ab0000.sdhci failed to add host It is due to getting related vmmc or vqmmc regulator returns -EPROBE_DEFER. It doesn't matter at all but it's confusing. >From another side, if driver probing fails and the error number isn't -EPROBE_DEFER, the core will tell us something as below: [.....] sdhci-pxav3: probe of f7ab0000.sdhci failed with error -EXX So it's not necessary to emit error msg if sdhci_add_host() fails. And some other sdhci host drivers also have this issue, let's fix them together. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-28mmc: sdhci-xenon: use match_string() helperXie Yisheng
match_string() returns the index of an array for a matching string, which can be used intead of open coded variant. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Hu Ziji <huziji@marvell.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21Merge branch 'fixes' into nextUlf Hansson
2018-05-21mmc: wbsd: handle highmem pagesChristoph Hellwig
Use sg_copy_{from,to}_buffer to bounce buffer and kmap_atomic to map the scatterlist entry before using it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: ushc: handle highmem pagesChristoph Hellwig
Pass the scatterlist on to the USB subsystem instead of expecting a kernel virtual address. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: mxcmmc: handle highmem pagesChristoph Hellwig
Use kmap_atomic to map the scatterlist entry before using it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: atmel-mci: use sg_copy_{from,to}_bufferChristoph Hellwig
This handles highmem pages, and also cleans up the code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: android-goldfish: use sg_copy_{from,to}_bufferChristoph Hellwig
This handles highmem pages, and also cleans up the code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: sdhci-iproc: add SDHCI_QUIRK2_HOST_OFF_CARD_ON for cygnusCorneliu Doban
The SDHCI_QUIRK2_HOST_OFF_CARD_ON is needed for the driver to properly reset the host controller (reset all) on initialization after exiting deep sleep. Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com> Signed-off-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Srinath Mannam <srinath.mannam@broadcom.com> Fixes: c833e92bbb60 ("mmc: sdhci-iproc: support standard byte register accesses") Cc: stable@vger.kernel.org # v4.10+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: sdhci-iproc: fix 32bit writes for TRANSFER_MODE registerCorneliu Doban
When the host controller accepts only 32bit writes, the value of the 16bit TRANSFER_MODE register, that has the same 32bit address as the 16bit COMMAND register, needs to be saved and it will be written in a 32bit write together with the command as this will trigger the host to send the command on the SD interface. When sending the tuning command, TRANSFER_MODE is written and then sdhci_set_transfer_mode reads it back to clear AUTO_CMD12 bit and write it again resulting in wrong value to be written because the initial write value was saved in a shadow and the read-back returned a wrong value, from the register. Fix sdhci_iproc_readw to return the saved value of TRANSFER_MODE when a saved value exist. Same fix for read of BLOCK_SIZE and BLOCK_COUNT registers, that are saved for a different reason, although a scenario that will cause the mentioned problem on this registers is not probable. Fixes: b580c52d58d9 ("mmc: sdhci-iproc: add IPROC SDHCI driver") Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com> Signed-off-by: Scott Branden <scott.branden@broadcom.com> Cc: stable@vger.kernel.org # v4.1+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: sdhci-iproc: remove hard coded mmc cap 1.8vSrinath Mannam
Remove hard coded mmc cap 1.8v from platform data as it is board specific. The 1.8v DDR mmc caps can be enabled using DTS property for those boards that support it. Fixes: b17b4ab8ce38 ("mmc: sdhci-iproc: define MMC caps in platform data") Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Cc: stable@vger.kernel.org # v4.8+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: meson-gx: add device resetJerome Brunet
Trigger the reset line of the mmc controller while probing, if available. The reset should be optional for now, at least until all related DT nodes have the reset property. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: dw_mmc-bluefield: Add driver extensionLiming Sun
This commit adds extension to the dw_mmc driver for Mellanox BlueField SoC. It updates the UHS_REG_EXT register to bring up the eMMC card on this SoC. Signed-off-by: Liming Sun <lsun@mellanox.com> Reviewed-by: David Woods <dwoods@mellanox.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: renesas_sdhi: Add r8a77965 supportMasaharu Hayakawa
This patch adds r8a77965 support in SDHI. Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-08mmc: tegra: remove redundant return statementAapo Vienamo
A redundant return statement is removed from tegra_sdhci_set_uhs_signaling(). The function returns void and the return does not affect the control flow of the function. Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-08mmc: rtsx_usb: Enable MMC_CAP_ERASE to allow erase/discard/trim requestsUlf Hansson
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Michał Pecio <michal.pecio@gmail.com>
2018-05-08mmc: rtsx_usb: Use the provided busy timeout from the mmc coreUlf Hansson
Instead of using a fixed 3s timeout for commands with R1B responses, convert to use the per request calculated busy timeout from the mmc core. This is needed to cope with requests that requires longer timeout, for example erase/discard commands. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Michał Pecio <michal.pecio@gmail.com>
2018-05-08mmc: rtsx_usb: Use MMC_CAP2_NO_SDIOUlf Hansson
Instead of having to return -EINVAL when requested to send SDIO specific commands, let's set MMC_CAP2_NO_SDIO as it completely prevents them. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Michał Pecio <michal.pecio@gmail.com>
2018-05-03Merge branch 'sdhci_omap' into nextUlf Hansson
Merge immutable branch for sdhci-omap to add UHS/HS200 mode support. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-03mmc: sdhci-omap: Get IODelay values for 3.3v DDR modeKishon Vijay Abraham I
commit 8d20b2eae6c47b095523 ("mmc: sdhci_omap: Add support to set IODELAY values") stored IODelay values for all MM/SD modes in pinctrl_state structure member of sdhci_omap_host. However for DDR mode it gets IODelay values only for 1.8v DDR mode. Since some of the platforms which uses sdhci-omap has IO lines connected to 3.3v, get IODelay values for 3.3v DDR mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-03mmc: sdhci-omap: Add sdhci_omap specific ops for enable_sdio_irqKishon Vijay Abraham I
Add sdhci_omap_enable_sdio_irq to set CTPL and CLKEXTFREE bits in MMCHS_CON register required to detect asynchronous card interrupt on DAT[1]. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-03mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoCKishon Vijay Abraham I
Add support for the new compatible added specifically to support k2g's MMC/SD controller. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-03mmc: sdhci-omap: Workaround for Errata i834Kishon Vijay Abraham I
Errata i834 in AM572x Sitara Processors Silicon Revision 2.0, 1.1 (SPRZ429K July 2014–Revised March 2017 [1]) mentions the maximum obtainable timeout through MMC host controller is 700ms. And for commands taking longer than 700ms, hardware timeout should be disabled and software timeout should be used. The workaround for Errata i834 can be achieved by adding SDHCI_QUIRK2_DISABLE_HW_TIMEOUT quirk in sdhci-omap. [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-03mmc: sdhci: Program a relatively accurate SW timeout valueKishon Vijay Abraham I
sdhci has a 10 second timeout to catch devices that stop responding. In the case of quirk SDHCI_QUIRK2_DISABLE_HW_TIMEOUT, instead of programming 10 second arbitrary value, calculate the total time it would take for the entire transfer to happen and program the timeout value accordingly. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-20 23:33:35 +0000