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path: root/drivers/pinctrl
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2019-10-16pinctrl: oxnas: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191002113819.4927-1-linus.walleij@linaro.org
2019-10-16pinctrl: st: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: the ST pin controller errors out of adding a irqchip if the interrupt is invalid or missing or if the irqmux is not present: the irqchip should not be added if either of these errors happen, so rewrite the code to deal with that. Keep the exit path where the gpio_chip is added no matter what the status of the irq is. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001135147.29416-1-linus.walleij@linaro.org
2019-10-16pinctrl: at91: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: at91 is a little bit special since it registers up to 3 gpio_chips with the same parent handler, but just passing girq->parent_handler and the parent on the first of them should cut it. Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191001130645.8350-1-linus.walleij@linaro.org
2019-10-14pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-4-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-3-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-2-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-1-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSRKeiya Nobuta
This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR. When assigning function to pin, GPSR should be set to peripheral function. For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to peripheral function. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: rzn1: Make array reg_drive static, makes object smallerColin Ian King
Don't populate the array reg_drive on the stack but instead make it static. Makes the object code smaller by 32 bytes. Before: text data bss dec hex filename 31991 15696 0 47687 ba47 drivers/pinctrl/pinctrl-rzn1.o After: text data bss dec hex filename 31863 15792 0 47655 ba27 drivers/pinctrl/pinctrl-rzn1.o (gcc version 9.2.1, amd64) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20191007140559.11840-1-colin.king@canonical.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-11Merge tag 'intel-pinctrl-fixes-v5.4' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl fixes for v5.4 This includes two fixes for Intel pinctrl drivers: - Fix warning about shared irqchip - Restore Strago DMI workaround for all versions
2019-10-09pinctrl: armada-37xx: swap polarity on LED groupPatrick Williams
The configuration registers for the LED group have inverted polarity, which puts the GPIO into open-drain state when used in GPIO mode. Switch to '0' for GPIO and '1' for LED modes. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Patrick Williams <alpawi@amazon.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20191001155154.99710-1-alpawi@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-07pinctrl: rza2: Fix gpio name typosChris Brandt
Fix apparent copy/paste errors that were overlooked in the original driver. "P0_4" -> "PF_4" "P0_3" -> "PG_3" Fixes: b59d0e782706 ("pinctrl: Add RZ/A2 pin and gpio controller") Cc: <stable@vger.kernel.org> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Link: https://lore.kernel.org/r/20190930145804.30497-1-chris.brandt@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-05pinctrl: stmfx: fix null pointer on removeAmelie Delaunay
dev_get_platdata(&pdev->dev) returns a pointer on struct stmfx_pinctrl, not on struct stmfx (platform_set_drvdata(pdev, pctl); in probe). Pointer on struct stmfx is stored in driver data of pdev parent (in probe: struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);). Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20191004122342.22018-1-amelie.delaunay@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05pinctrl: iproc: allow for error from platform_get_irq()Chris Packham
platform_get_irq() can return an error code. Allow for this when getting the irq. Fixes: 6f265e5d4da7 ("pinctrl: bcm-iproc: Pass irqchip when adding gpiochip") Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20191003000310.17099-2-chris.packham@alliedtelesis.co.nz Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05pinctrl: iproc: use unique name for irq chipChris Packham
Use the dev_name(dev) for the irqc->name so that we get unique names when we have multiple instances of this driver. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Link: https://lore.kernel.org/r/20191003000310.17099-3-chris.packham@alliedtelesis.co.nz Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable()Dan Carpenter
The pinctrl->functions[] array has pinctrl->num_functions elements and the pinctrl->groups[] array is the same way. These are set in ns2_pinmux_probe(). So the > comparisons should be >= so that we don't read one element beyond the end of the array. Fixes: b5aa1006e4a9 ("pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20190926081426.GB2332@mwanda Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05pinctrl: bcm-iproc: Use SPDX headerLinus Walleij
This convert the BCM IPROC driver to use the SPDX header for indicating GPL v2.0 only licensing. Cc: Pramod Kumar <pramodku@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Scott Branden <scott.branden@broadcom.com> Link: https://lore.kernel.org/r/20191002130217.4491-1-linus.walleij@linaro.org
2019-10-04pinctrl: armada-37xx: fix control of pins 32 and upPatrick Williams
The 37xx configuration registers are only 32 bits long, so pins 32-35 spill over into the next register. The calculation for the register address was done, but the bitmask was not, so any configuration to pin 32 or above resulted in a bitmask that overflowed and performed no action. Fix the register / offset calculation to also adjust the offset. Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support") Signed-off-by: Patrick Williams <alpawi@amazon.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20191001154634.96165-1-alpawi@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04pinctrl: devicetree.c: remove orphan pinctrl_dt_has_hogs()Rasmus Villemoes
The helper pinctrl_dt_has_hogs() was introduced in 99e4f67508e1 (pinctrl: core: Use delayed work for hogs), but the sole use then got removed shortly after in 950b0d91dc10 (pinctrl: core: Fix regression caused by delayed work for hogs). Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Link: https://lore.kernel.org/r/20190923142005.5632-1-linux@rasmusvillemoes.dk Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04pinctrl: tegra: xusb: Add note about legacy statusThierry Reding
Add a comment about why the call to of_match_node() cannot be replaced by of_device_get_match_data(). This will hopefully prevent people from attempting to clean this up in the future. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04pinctl: ti: iodelay: fix error checking on pinctrl_count_index_with_args callColin Ian King
The call to pinctrl_count_index_with_args checks for a -EINVAL return however this function calls pinctrl_get_list_and_count and this can return -ENOENT. Rather than check for a specific error, fix this by checking for any error return to catch the -ENOENT case. Addresses-Coverity: ("Improper use of negative") Fixes: 003910ebc83b ("pinctrl: Introduce TI IOdelay configuration driver") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20190920122030.14340-1-colin.king@canonical.com Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio coreBrian Masney
Now that the GPIO core has support for hierarchical IRQ chips, convert Qualcomm's ssbi-gpio over to use these new helpers to reduce duplicated code across drivers. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20190914111010.24384-1-masneyb@onstation.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03pinctrl: devicetree: Avoid taking direct reference to device name stringWill Deacon
When populating the pinctrl mapping table entries for a device, the 'dev_name' field for each entry is initialised to point directly at the string returned by 'dev_name()' for the device and subsequently used by 'create_pinctrl()' when looking up the mappings for the device being probed. This is unreliable in the presence of calls to 'dev_set_name()', which may reallocate the device name string leaving the pinctrl mappings with a dangling reference. This then leads to a use-after-free every time the name is dereferenced by a device probe: | BUG: KASAN: invalid-access in strcmp+0x20/0x64 | Read of size 1 at addr 13ffffc153494b00 by task modprobe/590 | Pointer tag: [13], memory tag: [fe] | | Call trace: | __kasan_report+0x16c/0x1dc | kasan_report+0x10/0x18 | check_memory_region | __hwasan_load1_noabort+0x4c/0x54 | strcmp+0x20/0x64 | create_pinctrl+0x18c/0x7f4 | pinctrl_get+0x90/0x114 | devm_pinctrl_get+0x44/0x98 | pinctrl_bind_pins+0x5c/0x450 | really_probe+0x1c8/0x9a4 | driver_probe_device+0x120/0x1d8 Follow the example of sysfs, and duplicate the device name string before stashing it away in the pinctrl mapping entries. Cc: Linus Walleij <linus.walleij@linaro.org> Reported-by: Elena Petrova <lenaptr@google.com> Tested-by: Elena Petrova <lenaptr@google.com> Signed-off-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20191002124206.22928-1-will@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03pinctrl: at91-pio4: implement .get_multiple and .set_multipleAlexandre Belloni
Implement .get_multiple and .set_multiple to allow reading or setting multiple pins simultaneously. Pins in the same bank will all be switched at the same time, improving synchronization and performances. Keep the driver future proof by allowing its use on 64bits platforms if they ever appear with this IP and we end up with a mismatch between ATMEL_PIO_NPINS_PER_BANK and BITS_PER_LONG. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20190918113657.25998-1-alexandre.belloni@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-01pinctrl: samsung: Fix device node refcount leaks in init codeKrzysztof Kozlowski
Several functions use for_each_child_of_node() loop with a break to find a matching child node. Although each iteration of for_each_child_of_node puts the previous node, but early exit from loop misses it. This leads to leak of device node. Cc: <stable@vger.kernel.org> Fixes: 9a2c1c3b91aa ("pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01pinctrl: samsung: Fix device node refcount leaks in S3C64xx wakeup ↵Krzysztof Kozlowski
controller init In s3c64xx_eint_eint0_init() the for_each_child_of_node() loop is used with a break to find a matching child node. Although each iteration of for_each_child_of_node puts the previous node, but early exit from loop misses it. This leads to leak of device node. Cc: <stable@vger.kernel.org> Fixes: 61dd72613177 ("pinctrl: Add pinctrl-s3c64xx driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01pinctrl: samsung: Fix device node refcount leaks in S3C24xx wakeup ↵Krzysztof Kozlowski
controller init In s3c24xx_eint_init() the for_each_child_of_node() loop is used with a break to find a matching child node. Although each iteration of for_each_child_of_node puts the previous node, but early exit from loop misses it. This leads to leak of device node. Cc: <stable@vger.kernel.org> Fixes: af99a7507469 ("pinctrl: Add pinctrl-s3c24xx driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01pinctrl: samsung: Fix device node refcount leaks in Exynos wakeup controller ↵Krzysztof Kozlowski
init In exynos_eint_wkup_init() the for_each_child_of_node() loop is used with a break to find a matching child node. Although each iteration of for_each_child_of_node puts the previous node, but early exit from loop misses it. This leads to leak of device node. Cc: <stable@vger.kernel.org> Fixes: 43b169db1841 ("pinctrl: add exynos4210 specific extensions for samsung pinctrl driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01pinctrl: samsung: Add of_node_put() before return in error pathNishka Dasgupta
Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return of exynos_eint_wkup_init() error path. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Cc: <stable@vger.kernel.org> Fixes: 14c255d35b25 ("pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01pinctrl: cherryview: restore Strago DMI workaround for all versionsDmitry Torokhov
This is essentially a revert of: e3f72b749da2 pinctrl: cherryview: fix Strago DMI workaround 86c5dd6860a6 pinctrl: cherryview: limit Strago DMI workarounds to version 1.0 because even with 1.1 versions of BIOS there are some pins that are configured as interrupts but not claimed by any driver, and they sometimes fire up and result in interrupt storms that cause touchpad stop functioning and other issues. Given that we are unlikely to qualify another firmware version for a while it is better to keep the workaround active on all Strago boards. Reported-by: Alex Levin <levinale@chromium.org> Fixes: 86c5dd6860a6 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Alex Levin <levinale@chromium.org> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-01pinctrl: intel: Allocate IRQ chip dynamicAndy Shevchenko
Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. Fixes: ee1a6ca43dba ("pinctrl: intel: Add Intel Broxton pin controller support") Depends-on: 5ff56b015e85 ("pinctrl: intel: Disable GPIO pin interrupts in suspend") Reported-by: Federico Ricchiuto <fed.ricchiuto@gmail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-01pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC supportBiju Das
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-9-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"Geert Uytterhoeven
This reverts commit e167d723e1a472d252e5c4baf823b77ce5543b05. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SIMCARD_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-4-geert+renesas@glider.be
2019-10-01Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 ↵Geert Uytterhoeven
and SSI_WS2" This reverts commit e87882eb9be10b2b9e28156922c2a47d877f5db4. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SSI2_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-3-geert+renesas@glider.be
2019-10-01pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functionsTakeshi Kihara
The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2 register bit[23:20] value H'3 and register bit[27:24] value H'3 from AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp. AVB_AVTP_CAPTURE. Update the R-Car E3 pin control driver to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword, reference errata] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-2-geert+renesas@glider.be
2019-09-30pinctrl: sirf/atlas7: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Barry Song <baohua@kernel.org> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-6-linus.walleij@linaro.org
2019-09-30pinctrl: sirf: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Barry Song <baohua@kernel.org> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-5-linus.walleij@linaro.org
2019-09-30pinctrl: nuvoton: npcm7xx: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Tomer Maimon <tmaimon77@gmail.com> Cc: Kun Yi <kunyi@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-4-linus.walleij@linaro.org
2019-09-30pinctrl: spear/plgpio: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-3-linus.walleij@linaro.org
2019-09-30pinctrl: pic32: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Joshua Henderson <joshua.henderson@microchip.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-2-linus.walleij@linaro.org
2019-09-30pinctrl: coh901: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190913113530.5536-1-linus.walleij@linaro.org
2019-09-19Merge tag 'pinctrl-v5.4-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.4 kernel cycle: Core changes: - Fix errors in example code in the documentation. New drivers: - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the Ingenic driver. - Support Cirrus Logic Madera CS47L92 and CS47L15. - Support Allwinner Sunxi V3S. - Support Aspeed 2600 BMC. - Support Qualcomm SC7180. - Support Marvell MVEBU CS115. Driver improvements: - Clean up a few drivers to use the devm_platform_ioremap_resource() helper. - Pass the irqchip when registering the gpio_chip in some pin controllers that are also GPIO controllers. - Support suspend/resume in the Tegra driver. - Support pull-up on the Broadcom BCM2711. - The Intel driver can now request locked pads. - Fix the UFS reset pin in the Qualcomm SDM845 driver" * tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux() pinctrl: bcm: remove redundant assignment to pointer log pinctrl: iproc: Add 'get_direction' support pinctrl: iproc-gpio: Handle interrupts for multiple instances pinctrl: iproc-gpio: Fix incorrect pinconf configurations pinctrl: intel: mark intel_pin_to_gpio __maybe_unused pinctrl: qcom: sdm845: Fix UFS_RESET pin pinctrl: mvebu: add additional variant for standalone CP115 pinctrl: mvebu: Add CP110 missing pin functionality dt-bindings: cp110: document the new CP115 pinctrl compatible pinctrl: bcm2835: Pass irqchip when adding gpiochip pinctrl: meson: meson: Add of_node_put() before return pinctrl/gpio: Take MUX usage into account dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support pinctrl: amd: disable spurious-firing GPIO IRQs pinctrl: rza2: Include the appropriate headers pinctrl: rza2: Drop driver use of consumer flags ...
2019-09-16Merge tag 'gpio-v5.4-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of changes in the GPIO subsystem for the v5.4 kernel cycle. Core changes: - Support hierarchical GPIO irqchips. We now have three consumers that can use this: Intel IXP4xx, ThunderX and Qualcomm SPMI GPIO (in the pinctrl subsystem). The support code has been long in the making and hashed out so it should be easily adaptable for all hierarchical irqchip parents. The code only gets compiled in if hierarchical irqchip is used at the topmost irq controller at least, as the hierarchical irqchip requires strict hierarchy all the way up in the system. - Determine the need for a "valid_mask" for GPIO lines on the gpio_chip and conversely for the "valid_mask" for the GPIO interrupt chip interrupt lines by looking for a .init_valid_mask() callback in the main chip or GPIO interrupt chip respectively. Allocate it with bitmap_alloc(). - Isolate the device tree/open firmware GPIO description code out in its own file properly. - Isolate the ACPI GPIO description code out in its own file properly. - Drop a whole lot of #ifdef:s in the main includes: it does not hurt to keep the include items around, and we get quicker and clearer compile failures if the appropriate kernel symbols are not selected for drivers. New/deleted drivers: - New driver for Aspeed SGPIO. - The KS8695 driver is deleted as the platform gets deleted from arch/arm in this kernel cycle. - The Cirrus Logic Madera driver now supports CS47L92 and CS47L15. - The Freescale MPC8xxx now supports LS1028A and LS1088A. Driver improvements: - We pass the GPIO irqchip intialization by directly filling in the struct instead of using set-up functions (the new way) for Intel MID, Lynxpoint, Merrifield, XLP, HLWD, Aspeed, ZX, VF610, TQMX86, MT7621, Zynq and EP93xx. Out-of-band changes: - Fix a GPIO header inclusion in Unicore - no response from maintainer. - Drop FMC subsystem from MAINTAINERS - was deleted in the GPIO tree last cycle so let's mop up the shards" * tag 'gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (82 commits) gpiolib: of: add a fallback for wlf,reset GPIO name gpio: htc-egpio: Remove unused exported htc_egpio_get_wakeup_irq() gpio: remove explicit comparison with 0 gpio: creg-snps: use devm_platform_ioremap_resource() to simplify code gpio: devres: Switch to EXPORT_SYMBOL_GPL() gpio: of: Switch to EXPORT_SYMBOL_GPL() gpio: of: Make of_gpio_simple_xlate() private gpio: of: Make of_get_named_gpiod_flags() private gpio: aspeed: Add in ast2600 details to Aspeed driver gpio: aspeed: Use ngpio property from device tree if available gpio: aspeed: Setup irqchip dynamically gpio/aspeed: Fix incorrect number of banks gpio: aspeed: Update documentation with ast2600 controllers gpio: Initialize the irqchip valid_mask with a callback gpiolib: acpi: make acpi_can_fallback_to_crs() static gpio: Fix further merge errors gpio: Fix up merge collision in include file gpio: of: Normalize return code variable name gpio: gpiolib: Normalize return code variable name gpio: ep93xx: Pass irqchip when adding gpiochip ...
2019-09-13pinctrl: meson-gxbb: Fix wrong pinning definition for uart_cOtto Meier
Hi i tried to use the uart_C of the the odroid-c2. I enabled it in the dts file. During boot it crashed when the the sdcard slot is addressed. After long search in the net i found this: https://forum.odroid.com/viewtopic.php?f=139&t=25371&p=194370&hilit=uart_C#p177856 After changing the pin definitions accordingly erverything works. Uart_c is functioning and sdcard ist working. Fixes: 6db0f3a8a04e46 ("pinctrl: amlogic: gxbb: add more UART pins") Signed-off-by: Otto Meier <gf435@gmx.net> Link: https://lore.kernel.org/r/1cc32a18-464d-5531-7a1c-084390e2ecb1@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()Dan Carpenter
We need to unlock and enable IRQs before we return on this error path. Fixes: 8a0cc47ccc7c ("pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20190827093927.GB8443@mwanda Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12Merge tag 'intel-pinctrl-v5.4-2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.4 part 2 Just a single fix for build warning introduced in the previous pull.
2019-09-12pinctrl: bcm: remove redundant assignment to pointer logColin Ian King
The pointer log is being initialized with a value that is never read and is being re-assigned a little later on. The assignment is redundant and hence can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20190905140919.29283-1-colin.king@canonical.com Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12pinctrl: iproc: Add 'get_direction' supportRayagonda Kokatanur
Add 'get_direction' support to the iProc GPIO driver. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Link: https://lore.kernel.org/r/1568178685-30738-1-git-send-email-rayagonda.kokatanur@broadcom.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12pinctrl: aspeed: Fix spurious mux failures on the AST2500Andrew Jeffery
Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") was determined to be a partial fix to the problem of acquiring the LPC Host Controller and GFX regmaps: The AST2500 pin controller may need to fetch syscon regmaps during expression evaluation as well as when setting mux state. For example, this case is hit by attempting to export pins exposing the LPC Host Controller as GPIOs. An optional eval() hook is added to the Aspeed pinmux operation struct and called from aspeed_sig_expr_eval() if the pointer is set by the SoC-specific driver. This enables the AST2500 to perform the custom action of acquiring its regmap dependencies as required. John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based) where the issue was found, and I've booted the fix on Witherspoon (AST2500) and Palmetto (AST2400) machines, and poked at relevant pins under QEMU by forcing mux configurations via devmem before exporting GPIOs to exercise the driver. Fixes: 7d29ed88acbb ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers") Fixes: 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") Reported-by: John Wang <wangzqbj@inspur.com> Tested-by: John Wang <wangzqbj@inspur.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11pinctrl: iproc-gpio: Handle interrupts for multiple instancesRayagonda Kokatanur
When multiple instance of iproc-gpio chips are present, a fix up message[1] is printed during the probe of second and later instances. This issue is because driver sharing same irq_chip data structure among multiple instances of driver. Fix this by allocating irq_chip data structure per instance of iproc-gpio. [1] fix up message addressed by this patch [ 7.862208] gpio gpiochip2: (689d0000.gpio): detected irqchip that is shared with multiple gpiochips: please fix the driver. Fixes: 616043d58a89 ("pinctrl: Rename gpio driver from cygnus to iproc") Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Link: https://lore.kernel.org/r/1567054348-19685-3-git-send-email-srinath.mannam@broadcom.com [Rebased on top of new irq chip set-up code] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-12 07:09:30 +0000