// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2025 PHYTEC Messtechnik GmbH */ #include #include /dts-v1/; /plugin/; &backlight_lvds0 { brightness-levels = <0 8 16 32 64 128 255>; default-brightness-level = <8>; enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; num-interpolated-steps = <2>; pwms = <&pwm1 0 66667 0>; status = "okay"; }; &lcdif2 { status = "okay"; }; &lvds_bridge { assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; /* * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout * engine can reach accurate pixel clock of exactly 72.4 MHz. */ assigned-clock-rates = <0>, <506800000>; status = "okay"; }; &panel0_lvds { compatible = "edt,etml1010g3dra"; status = "okay"; }; &pwm1 { status = "okay"; };