// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2024-2025 NXP
 */

/dts-v1/;

#include "imx943.dtsi"

/ {
	compatible = "fsl,imx943-evk", "fsl,imx94";
	model = "NXP i.MX943 EVK board";

	aliases {
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &lpuart1;
	};

	chosen {
		stdout-path = &lpuart1;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		off-on-delay-us = <12000>;
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		pinctrl-names = "default";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "VDD_SD2_3V3";
		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x80000000 0 0x7f000000>;
			reusable;
			size = <0 0x10000000>;
			linux,cma-default;
		};
	};

	memory@80000000 {
		reg = <0x0 0x80000000 0x0 0x80000000>;
		device_type = "memory";
	};
};

&lpuart1 {
	pinctrl-0 = <&pinctrl_uart1>;
	pinctrl-names = "default";
	status = "okay";
};

&scmi_iomuxc {
	pinctrl_uart1: uart1grp {
		fsl,pins = <
			IMX94_PAD_UART1_TXD__LPUART1_TX		0x31e
			IMX94_PAD_UART1_RXD__LPUART1_RX		0x31e
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e
			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e
			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x15fe
			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x13fe
			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX94_PAD_SD1_CLK__USDHC1_CLK		0x158e
			IMX94_PAD_SD1_CMD__USDHC1_CMD		0x138e
			IMX94_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
			IMX94_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
			IMX94_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
			IMX94_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
			IMX94_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
			IMX94_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
			IMX94_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
			IMX94_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
			IMX94_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e
			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e
			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x15fe
			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x13fe
			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			IMX94_PAD_SD2_CD_B__GPIO4_IO20		0x31e
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX94_PAD_SD2_CLK__USDHC2_CLK		0x158e
			IMX94_PAD_SD2_CMD__USDHC2_CMD		0x138e
			IMX94_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
			IMX94_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
			IMX94_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
			IMX94_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
			IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
		>;
	};

	pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp {
		fsl,pins = <
			IMX94_PAD_SD2_RESET_B__GPIO4_IO27	0x31e
		>;
	};
};

&usdhc1 {
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	bus-width = <8>;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
};

&usdhc2 {
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	bus-width = <4>;
	no-mmc;
	no-sdio;
	cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&wdog3 {
	fsl,ext-reset-output;
	status = "okay";
};