// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/V2N SoC
 *
 * Copyright (C) 2025 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

/* RZV2N_Px = Offset address of PFC_P_mn  - 0x20 */
#define RZV2N_P0	0
#define RZV2N_P1	1
#define RZV2N_P2	2
#define RZV2N_P3	3
#define RZV2N_P4	4
#define RZV2N_P5	5
#define RZV2N_P6	6
#define RZV2N_P7	7
#define RZV2N_P8	8
#define RZV2N_P9	9
#define RZV2N_PA	10
#define RZV2N_PB	11

#define RZV2N_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
#define RZV2N_GPIO(port, pin)		RZG2L_GPIO(RZV2N_P##port, pin)

/ {
	compatible = "renesas,r9a09g056";
	#address-cells = <2>;
	#size-cells = <2>;

	audio_extal_clk: audio-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	/*
	 * The default cluster table is based on the assumption that the PLLCA55 clock
	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
	 * clocked to 1.8GHz as well). The table below should be overridden in the board
	 * DTS based on the PLLCA55 clock frequency.
	 */
	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp-1700000000 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};
		opp-850000000 {
			opp-hz = /bits/ 64 <850000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};
		opp-212500000 {
			opp-hz = /bits/ 64 <212500000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
			opp-suspend;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			device_type = "cpu";
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
			operating-points-v2 = <&cluster0_opp>;
		};

		L3_CA55: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-level = <3>;
		};
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	qextal_clk: qextal-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	rtxin_clk: rtxin-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		pinctrl: pinctrl@10410000 {
			compatible = "renesas,r9a09g056-pinctrl";
			reg = <0 0x10410000 0 0x10000>;
			clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 96>;
			power-domains = <&cpg>;
			resets = <&cpg 0xa5>, <&cpg 0xa6>;
		};

		cpg: clock-controller@10420000 {
			compatible = "renesas,r9a09g056-cpg";
			reg = <0 0x10420000 0 0x10000>;
			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
			clock-names = "audio_extal", "rtxin", "qextal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		sys: system-controller@10430000 {
			compatible = "renesas,r9a09g056-sys";
			reg = <0 0x10430000 0 0x10000>;
			clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>;
			resets = <&cpg 0x30>;
		};

		scif: serial@11c01400 {
			compatible = "renesas,scif-r9a09g056",
				     "renesas,scif-r9a09g057";
			reg = <0 0x11c01400 0 0x400>;
			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
					  "tei", "tei-dri", "rxi-edge", "txi-edge";
			clocks = <&cpg CPG_MOD 0x8f>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg 0x95>;
			status = "disabled";
		};

		gic: interrupt-controller@14900000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x14900000 0 0x20000>,
			      <0x0 0x14940000 0 0x80000>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};

		sdhi0: mmc@15c00000  {
			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c00000 0 0x10000>;
			interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
				 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa7>;
			power-domains = <&cpg>;
			status = "disabled";

			sdhi0_vqmmc: vqmmc-regulator {
				regulator-name = "SDHI0-VQMMC";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				status = "disabled";
			};
		};

		sdhi1: mmc@15c10000 {
			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c10000 0 0x10000>;
			interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
				 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa8>;
			power-domains = <&cpg>;
			status = "disabled";

			sdhi1_vqmmc: vqmmc-regulator {
				regulator-name = "SDHI1-VQMMC";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				status = "disabled";
			};
		};

		sdhi2: mmc@15c20000 {
			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
			reg = <0x0 0x15c20000 0 0x10000>;
			interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
				 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg 0xa9>;
			power-domains = <&cpg>;
			status = "disabled";

			sdhi2_vqmmc: vqmmc-regulator {
				regulator-name = "SDHI2-VQMMC";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				status = "disabled";
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
	};
};