summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/intel/e1000e/hw.h
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2013-01-18 14:12:11 -0500
committerDavid S. Miller <davem@davemloft.net>2013-01-18 14:12:11 -0500
commita16af2ffa2f640f094a3ad3543996a37b588a3cc (patch)
treedc9a5126db710cbfa0cada18f20acec42495b7b7 /drivers/net/ethernet/intel/e1000e/hw.h
parent887c95cc1da53f66a5890fdeab13414613010097 (diff)
parentba59814b39b7ec674f604b0f9b35f1773f2fbf1a (diff)
Merge branch 'intel'
Jeff Kirsher says: ==================== This series contains updates to e1000e and igb. Most notably is the added timestamp support in e1000e and additional software timestamp support in igb. As well as, the added thermal data support and SR-IOV configuration support in igb. v2- dropped the following patches from the previous 14 patch series because changes were requested from the community: e1000e: add support for IEEE-1588 PTP igb: Report L4 Rx hash via skb->l4_rxhash ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/hw.h')
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 06239fe47db1..8e7e80345a60 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -60,8 +60,10 @@ enum e1e_registers {
E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
+ E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
+ E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
E1000_RCTL = 0x00100, /* Rx Control - RW */
E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
@@ -240,6 +242,15 @@ enum e1e_registers {
#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
E1000_HICR = 0x08F00, /* Host Interface Control */
+ E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
+ E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
+ E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
+ E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
+ E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
+ E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
+ E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
+ E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
+ E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
};
#define E1000_MAX_PHY_ADDR 4