diff options
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index a2bd808bb330..6f17fb7975fe 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3303,21 +3303,27 @@ compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>; clock-names = "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; + "edp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; |