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path: root/drivers/phy/samsung/phy-gs101-ufs.c
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Diffstat (limited to 'drivers/phy/samsung/phy-gs101-ufs.c')
-rw-r--r--drivers/phy/samsung/phy-gs101-ufs.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-gs101-ufs.c
index 17b798da5b57..a15e1f453f7f 100644
--- a/drivers/phy/samsung/phy-gs101-ufs.c
+++ b/drivers/phy/samsung/phy-gs101-ufs.c
@@ -108,12 +108,39 @@ static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {
END_UFS_PHY_CFG,
};
+static const struct samsung_ufs_phy_cfg tensor_gs101_post_h8_enter[] = {
+ PHY_TRSV_REG_CFG_GS101(0x262, 0x08, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x265, 0x0A, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x1, 0x8, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x0, 0x86, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_h8_exit[] = {
+ PHY_COMN_REG_CFG(0x0, 0xC6, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x1, 0x0C, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x262, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x265, 0x00, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x8, 0xE0, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_HS_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x18, PWR_MODE_HS_ANY),
+ END_UFS_PHY_CFG,
+};
+
static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {
[CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
[CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
[CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
};
+static const struct samsung_ufs_phy_cfg *tensor_gs101_hibern8_cfgs[] = {
+ [CFG_POST_HIBERN8_ENTER] = tensor_gs101_post_h8_enter,
+ [CFG_PRE_HIBERN8_EXIT] = tensor_gs101_pre_h8_exit,
+};
+
static const char * const tensor_gs101_ufs_phy_clks[] = {
"ref_clk",
};
@@ -170,6 +197,7 @@ static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane)
const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy = {
.cfgs = tensor_gs101_ufs_phy_cfgs,
+ .cfgs_hibern8 = tensor_gs101_hibern8_cfgs,
.isol = {
.offset = TENSOR_GS101_PHY_CTRL,
.mask = TENSOR_GS101_PHY_CTRL_MASK,