| Age | Commit message (Collapse) | Author |
|---|
|
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Pull "dt-bindings: Tegra changes for v4.17-rc1" from Thierry Reding:
Mostly cleanup of existing bindings and initial support for Tegra194.
* tag 'tegra-for-4.17-dt-bindings' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt/bindings: Fix binding examples for Tegra GMI controller
dt-bindings: phy: Clarify ULPI PHY source clock
dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc
dt-bindings: tegra: Add missing chips and NVIDIA boards
|
|
This reverts commit 4e017f1419397473cf3db6e9fa020013998b1aa4.
As explained by Rob Herring:
"This "fix" is wrong. Memory controllers with chip selects should have
the chip select in the unit-address. The correct fix here is you should drop
"simple-bus"."
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
This reverts commit f81d7af7957539b7808961f929f945381530acb9.
As explained by Rob Herring:
"This "fix" is wrong. Memory controllers with chip selects should have
the chip select in the unit-address. The correct fix here is you should
drop "simple-bus"."
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Fixes the warning "GIC: PPI13 is secure or misconfigured" by
changing the interrupt type from level_low to edge_raising
Signed-off-by: Philipp Puschmann <pp@emlix.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|
|
Disable the USB overcurrent condition that is falsely detected on the
devkit.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|
|
Enables the watchdog0 timer on the Stratix10 devkit.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
|
|
For consistency with all other serial pins, add this pullup. It also
prevents the signal from floating and so consuming a useless extra amount
of power in crowbarred state if nothing is connected to RX.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
For consistency with all other serial pins, add this pullup. It also
prevents the signal from floating and so consuming a useless extra amount
of power in crowbarred state if nothing is connected to RX.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
Remove pullup on uart TX signals, they are push-pull outputs thus
pullups are pointless.
Add pullup on uart RX signals, they prevent the RX signals to be left
floating and so consuming a useless extra amount of power in crowbarred
state if nothing is connected to RX.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
There are only 19 PIOB pins having primary names PB0-PB18. Not all of them
have a 'C' function. So the pinctrl property mask ends up being the same as the
other SoC of the at91sam9x5 series.
Reported-by: Marek Sieranski <marek.sieranski@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
Update the "gpio-ranges" property of the CBUS GPIO controller on Meson8b
because it only provides 83 GPIOs.
The GPIO definitions in include/dt-bindings/gpio/meson8b-gpio.h
inherited all GPIOs from Meson8 until recently. However, Meson8b does
not support all GPIOs which are supported by Meson8 (Meson8b doesn't
have a GPIOZ bank, most of the pins from the GPIODV bank are missing on
Meson8b - just to name a few differences).
The actual number of GPIOs is only 83, instead of 120 from Meson8 plus
the 10 GPIOs from the DIF bank on Meson8b.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
|
|
The Odroid C1 features a microSD slot. This patch adds the necessary
DT bindings to support it.
Signed-off-by: Linus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
|
|
These are needed to use the n_gsm driver for TS 27.010 UART
multiplexing. Note that support for the OOB wake gpio is still
missing so the UART is not yet usable for n_gsm.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
Configure MDM6600 USB PHY.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
We have a USB OCHI PHY on port 1 for mdm6600. Port 2 is using transceiverless
logic (TLL) for USB EHCI for w3glte modem.
Let's also fix the node name to use usb-phy while at it.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
This patch adds syscon property for specifying soc-glue core into
device-tree of PXs2 SoC.
Currently, soc-glue core is used for changing the state of S/PDIF
signal output pin to signal output state or Hi-Z state.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
This patch adds syscon property for specifying soc-glue core into
device-tree of LD11/LD20 SoC.
Currently, soc-glue core is used for changing the state of S/PDIF
signal output pin to signal output state or Hi-Z state.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
The xref_xtal clock is used by twl6040 as mclk. It is needed for the HPPLL
internally.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The clock is directly sourced from sys_clkin, and provides an external
output clock for (typically) TWL6040 chip.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The pad configuration area under control module wkup has some miscellaneous
config registers, that are not pinmux related. Add a separate area for
these, and add support for syscon / clocks under this new area.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The pad configuration area under control module wkup has some miscellaneous
config registers, that are not pinmux related.
Add new compatible string for this section of control module.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
USB1 port is micro-AB type and can function as peripheral
as well as host. Enable dual-role mode for USB1.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
|
The Xunlong Orange Pi Zero Plus is single board computer.
- H5 Quad-core 64-bit Cortex-A53
- 512MB DDR3
- microSD slot
- Debug TTL UART
- 1000M/100M/10M Ethernet RJ45
- Realtek RTL8189FTV
- Spi flash (2MB)
- One USB 2.0 HOST, One USB 2.0 OTG
This is based on a patch from armbian:
https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
This adds the actual VGA DAC bridge that is used in the
Versatile AB, and sets the mode to 640x480 VGA.
The "clcd" clock was incorrectly named, the proper name
(from bindings) is "clcdclk". So far drivers survived
by just getting the first clock, but future drivers will
use named clocks.
We add the panel connector to the
"arm,versatile-tft-panel" as well, the signals actually
fork on the board, reaching both the VGA DAC and the
display connector.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The Versatile board can be equipped with a interface board
just named "IB2". This was created in the early 2000s for
prototyping GSM candybar phone form factor products.
The IB2 board contains:
- Cascaded interrupt controller
- Enfora Enabler GSM0308 quad-band module with antenna and
separate audio jack
- Keypad with joystick
- Sanyo 2.5" color display
- A 28-pin connector for mounting a camera
This adds a DTS file for the combination of the Versatile AB
with an IB2 daughterboard mounted, making the LED blink and
making the system controller available for drivers, such as
the panel driver.
The device tree bindings already exist in
Documentation/devicetree/bindings/arm/arm-boards.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The PL111 in the ARM reference platforms are connected to
"panels" that are actually dumb VGA DAC connector bridges.
Now that we can support the proper bridges in the DRM driver,
fix this up.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The PL111 in the ARM reference platforms are connected to
"panels" that are actually dumb VGA DAC connector bridges.
Now that we can support the proper bridges in the DRM driver,
fix this up.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The PL111 in the ARM reference platforms are connected to
"panels" that are actually dumb VGA DAC connector bridges.
Now that we can support the proper bridges in the DRM driver,
fix this up.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The PL111 in the ARM reference platforms are connected to
"panels" that are actually dumb VGA DAC connector bridges.
Now that we can support the proper bridges in the DRM driver,
fix this up.
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
efuse is one time programmable, so it is safer to deny write request
to this memory, unless the user is savvy enough to remove the read-only
flag from DTB
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
|
|
The Mali-450 IP can run up to 744MHz, bump the frequency using
the GP0 PLL clock.
Cc: Michal Lazo <michal.lazo@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
|
|
The Cubieboard4 has a dumb VGA DAC connected to the output of LCD0,
providing VGA output through the onboard VGA connector. The DDC lines
are connected to i2c3.
The VGA DAC is a GM7123, which is compatible with Analog Devices'
ADV7123, except it only takes 3.3V power, and has a lower standby power
consumption. The datasheet found online lists "Chengdu GoldTel Electronical
Technology Co., Ltd." as its designer. The company changed its name in
2014 to "Chengdu Corpro Technology Co., Ltd.". Their website lists similar
ICs, but not actually the GM7123.
Enable the display pipeline with the VGA DAC and connector, and i2c3
for DDC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
The A80 supports RGB888 with H/V sync from LCD0. Add a pinmux setting
for the needed pins.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
The Allwinner A80 SoC has 3 display pipelines, of which some parts are
documented:
- 3x display front ends (FE), documented
- 2x display enhancement units (DEU), undocumented
- 3x display back ends (BE), documented
- 2x dynamic range controller (DRC), undocumented
- 2x LCDC/TCONs, documented
- 1x LCDC/TCON, undocumented, and probably not useable
- 1x HDMI transmitter, undocumented but DesignWare compatible
- 1x MERGE block, function unknown
This patch adds device nodes for the first 2 documented pipelines:
FE0 - DEU0 - - BE0 - DRC0 - TCON0
x
FE1 - DEU1 - - BE1 - DRC1 - TCON1
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
The TERES-I is an open hardware laptop built by Olimex using the
Allwinner A64 SoC.
Add the board specific .dts file, which includes the A64 .dtsi and
enables the peripherals that we support so far.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for the LCD output. Tested on Teres I.
This patch was inspired by work of Icenowy Zheng.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Add a watchdog node for the A64, automatically enabled on all boards.
Since the device is compatible with an existing driver, we only reserve
a new compatible string to be used together with the fall back.
Tested on Olimex Teres-I.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Add the proper pin group node to reference in board files.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Pine H64 is an Allwinner H6-based SBC from Pine64, with the following
features:
- 1GiB/2GiB/4GiB LPDDR3 DRAM (in 4GiB situation only 3GiB is
accessible)
- AXP805 PMIC
- Raspberry-Pi-compatible GPIO header, "Euler" GPIO header (not
compatible with the "Euler" on Pine A64) and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
|
The schematic of the espressobin is publicly available, add a comment
where to find it.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "mtd: nand: marvell: Fix clock resource by adding
a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "crypto: inside-secure - fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "hwrng: omap - Fix clock resource by adding a
register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
This extra clock is needed to access the registers of the USB host
controller used on Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "usb: host: xhci-plat: Fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
Add auxadc device node for MT2712.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
|
This patch adds some device nodes for the PCIe function block and updates
related pinmux.
Moreover, we add interrupt-map properties in both parent and children as
the chip only has one IRQ per slot that is connected to all INTx and get
propagated through the bridges and it also represents the root ports own
interrupts.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
|
The H3 has an ARM Mali 400 GPU, so add binding to our DT.
Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
|
