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2019-02-11ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boardsVokáč Michal
These are i.MX6S/DL based SBCs embedded in various Y Soft products. All share the same board design but have slightly different HW configuration. Ursa - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 1x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) Draco - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 2x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) Hydra - i.MX6DL SoC, 2GB RAM DDR3, 4GB eMMC, microSD - I2C OLED display, capacitive matrix keys - 2x Eth (QCA8334 switch) - USB OTG - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) - HDMI - miniPCIe slot Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11ARM: dts: imx7ulp: add sim nodeAnson Huang
i.MX7ULP SoC revision info is inside the SIM mode's JTAG_ID register, add sim node to support SoC revision check. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhcBOUGH CHEN
i.MX6ULL has errata ERR010450, there is I/O timing limitation, for SDR mode, SD card clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. This patch change to use the new compatible "fsl,imx6ull-usdhc" to follow this limitation. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatibleStefan Wahren
Since imx6ulz.dtsi includes imx6ull.dtsi, we only need to fix the compatible string here to achieve the correct OTP size for both SoCs. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11ARM: dts: imx6sx: Add DISPLAY power domain supportLeonard Crestez
This was implemented in the driver but not actually defined and referenced in dts. This makes it always on. From reference manual in section "10.4.1.4.1 Power Distribution": "Display domain - The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. Handle this by adding the pcie node in both power domains. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-08arm64: dts: marvell: armada-37xx: link USB hosts with their PHYsMiquel Raynal
Reference the PHY nodes from the USB controller nodes. The USB3 host controller is wired to: * the first PHY of the COMPHY IP * the OTG-capable UTMI PHY The USB2 host controller is wired to: * the host-only UTMI PHY Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY propertyMiquel Raynal
The SATA node is wired to the third PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHYMiquel Raynal
The PCIe node is wired to the second PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: armada-37xx: declare the COMPHY nodeMiquel Raynal
Describe the A3700 COMPHY node. It has three PHYs that can be configured as follow: * PCIe or GbE * USB3 or GbE * SATA or USB3 Each of them has its own memory area. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashesGregory CLEMENT
By using the new binding for the partitions for the flashes we don't need anymore to use #size-cells and #address-cells at the flash node level. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-IDRemi Pommarel
The mv88e6341 ethernet switch needs the cpu port control register to be set with TX and RX internal delay in order to work. This fixes ethernet support on system booted via a bootloader that has not already configured this register (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pinsRemi Pommarel
In order to be able to communicate with the 88e6341 switch some pins have to be repurposed as RGMII and SMI pins. This fixes ethernet support on system booted via a bootloader that has not already configured those pins (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: meson: add g12a x96 max boardKevin Hilman
Add the G12a (S905X2) based X96 Max board[1]. There is no branding for the manufacturer anywhere on the product, so it took some digging[2] to find the manufacturer. But since there's nothing about the maker on the product I've left it out of the DT name because 1) nobody will know that name and 2) keeps the DT filename shorter. [1] https://www.cnx-software.com/2018/09/25/x96-max-amlogic-s905x2-tv-box/ [2] https://fccid.io/2AI6D-X96MAX Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-08dt-bindings: arm: amlogic: add amediatech x96-max bindingsKevin Hilman
Add new vendor for amediatech, and initial board: x96-max Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-08arm64: dts: meson: g12a: add peripheral clock controllerJerome Brunet
Add the peripheral clock controller to the g12a SoC DT Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-08arch: arm: dts: Remove disabled marvell,dsa propertiesAndrew Lunn
These have been disable since the change to probe Marvell Ethernet switches as MDIO devices. Remove the properties now that the code to suppport them will also be removed soon. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08arm64: dts: marvell: Add device tree for uDPU boardVladimir Vid
This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC. micro-DPU is the single-port FTTdp distribution point unit made by Methode Electronics which offers complete modularity with replaceable SFP modules both for uplink and downlink (G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable). On-board features: - 512 MiB DDR3 - 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC - USB 2.0 Type-C connector - 4GB eMMC - ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type) Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Luis Torres <luis.torres@methode.com> Cc: Scott Roberts <scott.roberts@telus.com> Cc: Paul Arola <paul.arola@telus.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-08dt-bindings: interrupt-controller: update bindings for MT7623Ryder Lee
This adds missing bindings for MT7623 sysirq. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-08arm64: dts: renesas: cat875: Enable PCIe supportBiju Das
This patch enables PCIEC0 PCI express controller on the sub board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0-cat874: Add pciec0 supportBiju Das
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the CAT874 main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add TMU device nodesBiju Das
This patch adds TMU{0|1|2|3|4} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add CMT device nodesBiju Das
This patch adds CMT{0|1|2|3} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devicesFabrizio Castro
This patch defines OOP tables for all CPUs, similarly to what done by Takeshi Kihara and Yoshihiro Kaneko for the R8A77990. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a77990: Add OPPs table for cpu devicesTakeshi Kihara
This patch define OOP tables for all CPUs. This allows CPUFreq to function. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: enable HS400 on R-Car Gen3Niklas Söderlund
Successfully tested on H3 ES2.0 and M3-N ES1.0. Transfer rates where >160MB/s for H3 and >200MB/s for M3-N. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08ARM: dts: r8a7744: Add LVDS supportBiju Das
Add LVDS encoder node to r8a7744 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08ARM: dts: r8a7744: Add DU supportBiju Das
Add du node to r8a7744 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-07arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN nodeDouglas Anderson
When commit 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") was posted upstream no clocks were specified. However, when the pack was picked into the Chrome OS kernel tree (allegedly directly from the mailing list post) it had clock properties. I presume that the clock should be there, so let's add it. Fixes: 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> [bjorn: Add also the required iommus property] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-07arm64: dts: meson: g12a: add clk measure supportJerome Brunet
Add the clock measure device to the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-07arm64: dts: meson: axg: add clk measure supportJerome Brunet
Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-07arm64: tegra: Update compatible for Tegra186 I2CSowjanya Komatineni
Update I2C Device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Update compatible for Tegra210 I2CSowjanya Komatineni
Update I2C device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Support 200 MHz for SDMMC on Tegra194Sowjanya Komatineni
Change the SDMMC clock source to support a maximum frequency of 200 MHz on Tegra194. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CQE Support for SDMMC4Sowjanya Komatineni
Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add SDMMC auto-calibration settingsSowjanya Komatineni
Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths for Tegra210, Tegra186 and Tegra194 which are used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888Mikko Perttunen
The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add nodes for TCU on Tegra194Mikko Perttunen
Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Enable DFLL clock on SmaugJoseph Lo
Enable DFLL clock for Smaug board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CPU power rail regulator on SmaugJoseph Lo
Add CPU power rail regulator for Smaug board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Enable DFLL clock on Jetson TX1Joseph Lo
Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add pinmux for PWM-based DFLL support on P2597Joseph Lo
Add pinmux for PWM-based DFLL support. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CPU clocks on Tegra210Joseph Lo
Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add DFLL clock on Tegra210Joseph Lo
Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07ARM: dts: gta04: add gps supportAndreas Kemnade
The GTA04 has a w2sg0004 or w2sg0084 gps chip. Not detectable which one is mounted so use the compatibility entry for w2sg0004 for all which will work for both. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: gta04: add ldo 3v3 regulatorAndreas Kemnade
Required for completeness sake to be able to specify a regulator for devices having a non-optional regulator property. It corresponds to the "3V3" net in the schematics. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: gta04: add pinctrl settings for wkup domainAndreas Kemnade
There is one button and a notifier for incoming phone calls/text messages for which we should wakeup from suspend. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: omap3-gta04a5: Replace LXR reference with a local oneJonathan Neuschäfer
There's no need to use an external link when the file is already here. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFBRyder Lee
Update binding document for MT7622 BPI-R64 and MT7629 reference board. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-07dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a"Ryder Lee
As we fallback to use "mediatek,mt7623" for MT7623a, remove unused root node property "mediatek,mt7623a" in the document. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-07ARM: dts: sun8i: a83t: Enable PMIC power supplies on various boardsChen-Yu Tsai
On the Bananapi M3 and Cubietruck Plus, the DC input jacks are wired to the ACIN pins, which is represented by the AC power supply. Both boards have connectors for LiPo batteries, which are represented by the battery power supply. The H8 Homlet is a set-top box design. The DC input jack is wired to the ACIN pins, but there are no battery connectors. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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