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2023-05-29arm64: dts: qcom: msm8916/39: Rename &blsp1_uartN -> &blsp_uartNStephan Gerhold
For some reason the BLSP UART controllers have a label with a number behind blsp (&blsp1_uartN) while I2C/SPI are named without (&blsp_i2cN). This is confusing, especially for proper node ordering in board DTs. Right now all board DTs are ordered as if the number behind blsp does not exist (&blsp_i2cN comes before &blsp1_uartN). Strictly speaking correct ordering would be the other way around ('1' comes before '_'). End this confusion by giving the UART controllers consistent labels. There is just one BLSP on MSM8916/39 so the number is redundant. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-2-bec0f5fb46fb@gerhold.net
2023-05-29arm64: dts: qcom: msm8916: Rename &msmgpio -> &tlmmStephan Gerhold
MSM8916 is the only ARM64 Qualcomm SoC that is still using the old &msmgpio name. Change this to &tlmm to avoid confusion. Note that the node ordering does not change because the MSM8916 device trees have pinctrl separated at the bottom (similar to sc7180). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-1-bec0f5fb46fb@gerhold.net
2023-05-29arm64: dts: qcom: qrb4210-rb2: Enable USB nodeBhupesh Sharma
Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516150511.2346357-5-bhupesh.sharma@linaro.org
2023-05-29arm64: dts: qcom: sm6115: Add USB SS qmp phy nodeBhupesh Sharma
Add USB superspeed qmp phy node to dtsi. Make sure that the various board dts files (which include sm4250.dtsi file) continue to work as intended. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516150511.2346357-4-bhupesh.sharma@linaro.org
2023-05-27arm64: dts: qcom: ipq5332: add support for the RDP442 variantKathiravan T
Add the initial device tree support for the Reference Design Platform(RDP) 442 based on IPQ5332 family of SoC. This patch carries the support for Console UART, SPI NOR, eMMC and I2C. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230509160133.3794-3-quic_kathirav@quicinc.com
2023-05-27dt-bindings: arm: qcom: document MI01.3 board based on IPQ5332 familyKathiravan T
Document the MI01.3 (Reference Design Platform 442) board based on IPQ5332 family of SoCs. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230509160133.3794-2-quic_kathirav@quicinc.com
2023-05-27ARM: dts: vf610: ZII: Add missing phy-mode and fixed linksAndrew Lunn
The DSA framework has got more picky about always having a phy-mode for the CPU port. The Vybrid FEC is a Fast Ethrnet using RMII. Additionally, the cpu label has never actually been used in the binding, so remove it. Lastly, for DSA links between switches, add a fixed-link node indicating the expected speed/duplex of the link. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6qdl-icore-rqs: Use the 'vmmc-supply' propertyFabio Estevam
'vmcc-supply' is not a valid property. Use 'vmmc-supply' supply instead. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: vfxxx: Remove invalid wdog propertyFabio Estevam
The 'clock-names' property is not a valid property for wdog. Remove it to fix the following DT check warning: vf610-zii-ssmb-dtu.dtb: watchdog@4003e000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: /Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx35: Remove invalid wdog propertyFabio Estevam
The 'clock-names' property is not a valid property for wdog. Remove it to fix the following DT check warning: watchdog@53fdc000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx7d-flex-concentrator: Remove invalid ecspi propertyFabio Estevam
The 'num-chipselects' property is not a valid property for ecspi. Remove it to fix the following DT check warning: spi@30630000: Unevaluated properties are not allowed ('num-chipselects' was unexpected) From schema: Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6ull-phytec-tauri: Remove invalid propertyFabio Estevam
The 'rs485-rts-active-high' property is not a valid property and is not documented anywhere. Remove it to fix the following DT schema warning: serial@21f0000: Unevaluated properties are not allowed ('rs485-rts-active-high' was unexpected) Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx93: add fsl,stop-mode property to support WOLWei Fang
Add fsl,stop-mode property for FEC to support Wake-on-LAN (WOL) feature. Otherwise, the WOL feature of FEC does not work. Signed-off-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx7d-smegw01: Pass Ethernet aliasesFabio Estevam
Pass Ethernet aliases, so that the bootloader can properly pass MAC address to Linux. This fixes the problem of getting a random MAC address for eth1 in Linux. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx7d-smegw01: Use pinctrl-0 for pinctrl_rfkillFabio Estevam
Use pinctrl-0 for pinctrl_rfkill to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: regulator-wlan-rfkill: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx7d-smegw01: Pass 'gpr' to the pinctrl groupsFabio Estevam
Pass 'gpr' to the pinctrl groups to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: pinctrl@30330000: 'rfkillrp', 'usbotg1', 'usbotg1-pwr', 'usbotg1-pwr-gpio' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx7d-smegw01: Remove unneeded #address-cells/#size-cellsFabio Estevam
Remove the unneeded #address-cells/#size-cells from sram@0 to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: sram@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) From schema: Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Enable SAI audio on MX8MP DHCOM PDK2 and PDK3Marek Vasut
Add SAI I2S and audio bindings on MX8MP DHCOM PDK2 and PDK3. The VDDA is supplied from on-carrier-board regulator, the VDDIO is supplied from always-on on-SoM regulator. Except for different I2C bus used to connect the codec, the implementation is virtually identical on both carrier boards. Align regulator-avdd name to regulator-3p3vdd on PDK3, since this is the VDDA supply and it is the same on both carrier boards. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mm-venice-gw700x: remove invalid props from fan-controllerTim Harvey
Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6qdl-gw5912: remove invalid nodes from fan-controllerTim Harvey
Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6qdl-gw54xx: remove invalid nodes from fan-controllerTim Harvey
Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6sx: Add LDB supportFabio Estevam
i.MX6SX has an LVDS controller that is connected to the eLCDIF. Add support for it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6sll-evk: avoid underscores in node nameHaibo Chen
usdhc1 and usdhc3 node name contain underscores, so replace the '_' by '-'. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6sll-evk: add eMMC node supportHaibo Chen
On imx6sll-evk board, eMMC is connect on the usdhc2. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: freescale: Add imx8mp-venice-gw7905-2xTim Harvey
The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - RGMII PHY (eQoS) - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOMMarek Vasut
Add TC9595 DSI-to-DPI and DSI-to-(e)DP bridge to DH electronics i.MX8M Plus DHCOM SoM . The bridge is populated on the SoM, but disabled by default unless used for display output. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6qdl: Add HDMI to TQMa6x/MBa6Alexander Stein
This adds support for a COTS monitor connected to X17. 4k monitors can be used, but are limited to 1080p. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27dt-bindings: arm: Add Gateworks i.MX8M GW7905-2x boardTim Harvey
Add DT compatible string for a Gateworks GW7905-2x board based on the i.MX8MPlus from NXP. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: rockchip: add PMIC to rk3588-evb1Sebastian Reichel
This adds PMIC support for the RK3588 EVB. Co-developed-by: shengfei Xu <xsf@rock-chips.com> Signed-off-by: shengfei Xu <xsf@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230526172255.68236-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-05-27arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B IOJagan Teki
Neural Compute Module 6B(Neu6B) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. General features: - microSD slot - 1x HDMI Out - 1x HDMI In - 2x DP - 1x eDP - 2x MIPI DSI connector - 4x MIPI CSI2 connector - 2x USB Host - 2x USB 3.0 OTG/Host - 1x SATA - 1x 2.5Gbps Ethernet - 1x 4G/5G mini PCIe - 1x M.2 E-Key slot - 1x Onboard PoE - 1x RS485, RS232, CAN - 1x Audio, MIC port - RTC battery slot - 40-pin GPIO expansion Neu6B needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. Add support for Edgeble Neu6 Model B IO Board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230516163454.997736-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-05-27arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B SoMJagan Teki
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. General features: - Rockchip RK3588J - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neu6B needs to mount on top of associated Edgeble Neu6B IO boards for creating complete platform solutions. Enable eMMC for now to boot Linux successfully. Add support for Edgeble Neu6 Model B SoM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230516163454.997736-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-05-27dt-bindings: arm: fsl: Fix syntax errorMarek Vasut
Fix the following error by replacing tab indent with spaces. " Documentation/devicetree/bindings/arm/fsl.yaml:930:46: [error] syntax error: found character '\t' that cannot start any token (syntax) " Fixes: d2bf7abfd235 ("dt-bindings: arm: fsl: Add Emtop SoM & Baseboard") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Add DeWarp Engine DT nodeMarek Vasut
Add DT node for the DeWarp Engine of the i.MX8MP. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Sort AIPS4 nodesMarek Vasut
Sort AIPS4 nodes by node unit-address . No functional change . Suggested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Add analog audio output on i.MX8MP TQMa8MPxL/MBa8MPxLAlexander Stein
Enable SAI3, add the codec and pinctrl nodes to enable audio support on MBa8MPxL. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: move noc node to correct positionAlexander Stein
The base address of NOC is bigger than aips5, but smaller than aips4. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27arm64: dts: imx8mp: Describe PCIe clock generator on DH electronics i.MX8M ↵Marek Vasut
Plus DHCOM on PDK3 The PDK3 carrier board contains a PCIe clock generator which is used to supply the PCIe clock lanes. This generator is always on, unless external CLKREQ signal toggles an output off, but this is handled in hardware. The generator does however have I2C interface, describe it in DT. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-27ARM: dts: imx6qdl-mba6: add mac address for USB ethernet controllerAlexander Stein
The mac address is stored in mainboard eeprom. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-05-26arm64: dts: qcom: sm8550: Add graphics clock controllerJagadeesh Kona
Add device node for graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524181800.28717-4-quic_jkona@quicinc.com
2023-05-26Merge branch 'sm8450-sm8550-gpucc-binding' into arm64-for-6.5Bjorn Andersson
Introduce DeviceTree bindings for SM8450 and SM8550 GPU clock controller, to introduce the constants necessary to referr to these clocks.
2023-05-26dt-bindings: clock: qcom: Add SM8550 graphics clock controllerJagadeesh Kona
Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
2023-05-26dt-bindings: clock: Add Qcom SM8450 GPUCCKonrad Dybcio
Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
2023-05-26arm64: dts: qcom: sa8775p-ride: enable i2c11Shazad Hussain
This enables the i2c11 node on sa8775p-ride board for A2B controller and audio port expander. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-6-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add uart5 and uart9 nodesShazad Hussain
Add remaining uart5 and uart9 nodes for UART bus present on sa8775p SoC. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-5-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add missing spi nodesShazad Hussain
Add the missing nodes of the SPI buses present on sa8775p platform. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-4-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add missing i2c nodesShazad Hussain
Add the missing nodes for the i2c buses present on sa8775p Soc. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 nodeShazad Hussain
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com
2023-05-26arm64: dts: qcom: apq8096: fix fixed regulator name propertyKrzysztof Kozlowski
Correct the typo in 'regulator-name' property. apq8096-ifc6640.dtb: v1p05-regulator: 'regulator-name' is a required property apq8096-ifc6640.dtb: v1p05-regulator: Unevaluated properties are not allowed ('reglator-name' was unexpected) Fixes: 6cbdec2d3ca6 ("arm64: dts: qcom: msm8996: Introduce IFC6640") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507174516.264936-3-krzysztof.kozlowski@linaro.org
2023-05-26arm64: dts: qcom: msm8996: correct MMCC clocks orderKrzysztof Kozlowski
Re-order the clocks for MMCC clock controller node to match the bindings (Linux driver takes by name): msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507174516.264936-2-krzysztof.kozlowski@linaro.org
2023-05-26arm64: dts: qcom: msm8916: correct LPASS CPU clocks orderKrzysztof Kozlowski
Re-order the clocks for LPASS CPU node to match the bindings (Linux driver takes by name): msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:1: 'mi2s-bit-clk0' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:2: 'mi2s-bit-clk1' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:3: 'mi2s-bit-clk2' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:4: 'mi2s-bit-clk3' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:5: 'pcnoc-mport-clk' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:6: 'pcnoc-sway-clk' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507174516.264936-1-krzysztof.kozlowski@linaro.org
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