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2024-05-27arm64: dts: qcom: sdm850-lenovo-yoga-c630: fix IPA firmware pathDmitry Baryshkov
Specify firmware path for the IPA network controller on the Lenovo Yoga C630 laptop. Without this property IPA tries to load firmware from the default location, which likely will fail. Fixes: 2e01e0c21459 ("arm64: dts: qcom: sdm850-yoga: Enable IPA") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-yoga-ipa-fw-v1-1-99ac1f5db283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: Enable download mode register writeMukesh Ojha
Enable download mode setting for sm8650 which can help collect ramdump for this SoC. Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com> Reviewed-by: Elliot Berman <quic_eberman@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/1715888133-2810-1-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: qru1000-idp: enable USB nodesKomal Bajaj
Enable both USB controllers and associated hsphy and qmp phy nodes on QRU1000 IDP. Co-developed-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Link: https://lore.kernel.org/r/20240502090326.21489-4-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: qdu1000-idp: enable USB nodesKomal Bajaj
Enable both USB controllers and associated hsphy and qmp phy nodes on QDU1000 IDP. Co-developed-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Link: https://lore.kernel.org/r/20240502090326.21489-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: qdu1000: Add USB3 and PHY supportKomal Bajaj
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on QDU1000/QRU1000 SoCs. Also add required pins for USB, so that the interface can work reliably. Co-developed-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Link: https://lore.kernel.org/r/20240502090326.21489-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: msm8996-xiaomi-common: drop excton from the USB PHYDmitry Baryshkov
The USB PHYs don't use extcon connectors, drop the extcon property from the hsusb_phy1 node. Fixes: 46680fe9ba61 ("arm64: dts: qcom: msm8996: Add support for the Xiaomi MSM8996 platform") Cc: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-13-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sda660-ifc6560: document missing USB PHY suppliesDmitry Baryshkov
On the IFC6560 one of the USB PHY supplies is the L10A power supply. However this regulator also supplies VDDA_APC1_CS, VDD_PLL2 and VDD_P11 consumers. Touching the supply causes the board to be reset. Document the supply as a fixed always-on regulator. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-12-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-11-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8350: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-10-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8250: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-9-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm6350: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-8-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm6115: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-7-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sdm845: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: cc16687fbd74 ("arm64: dts: qcom: sdm845: add UFS controller") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-6-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sc8180x: add power-domain to UFS PHYDmitry Baryshkov
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-5-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sc7180: drop extra UFS PHY compatDmitry Baryshkov
The DT schema doesn't have a fallback compatible for qcom,sc7180-qmp-ufs-phy. Drop it from the dtsi too. Fixes: 858536d9dc94 ("arm64: dts: qcom: sc7180: Add UFS nodes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-4-f1fd15c33fb3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sa8775p: Add ep pcie1 controller nodeMrinmay Sarkar
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform. It supports gen4 and x4 link width. Limiting the speed to Gen3 due to stability issue with Gen4. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1714494089-7917-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sa8775p: Add ep pcie0 controller nodeMrinmay Sarkar
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1714492540-15419-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qocm: sdx75: align smem node name with coding styleKrzysztof Kozlowski
Node names should not have vendor prefixes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240426123101.500676-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sdx75: Add modem SMP2P nodeKaushal Kumar
Add SMP2P node for the SDX75 platform to communicate with the modem. Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Link: https://lore.kernel.org/r/20240426112837.17478-1-quic_kaushalk@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sdx75: Add AOSS nodeRohit Agarwal
Add AOSS channel devicetree node for Qcom's SDX75 SoC. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/20240426055326.3141727-7-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sdx75: Add TCSR register spaceRohit Agarwal
Add TCSR register space devicetree node for accessing different status registers. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/20240426055326.3141727-6-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sdx75: Add IPCC nodeRohit Agarwal
Add IPCC devicetree node to Qcom's SDX75 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/20240426055326.3141727-5-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650-hdk: enable GPUNeil Armstrong
Add path of the GPU firmware for the SM8650-HDK board Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240425-topic-sm8650-upstream-hdk-gpu-v1-1-465a11af7441@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add connector for MUICRaymond Hackley
Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240424144922.28189-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: msm8916/39-samsung-a2015: Add PMIC and chargerRaymond Hackley
The phones listed below have Richtek RT5033 PMIC and charger. Add them to the device trees. - Samsung Galaxy A3/A5/A7 2015 - Samsung Galaxy E5/E7 - Samsung Galaxy Grand Max Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240424143158.24358-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm4450: Add cpufreq supportTengfei Fan
Add a description of a SM4450 cpufreq-epss controller,add references to it from CPU nodes and make EPSS a supplyer of clocks for the CPUs. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240424101503.635364-3-quic_tengfan@quicinc.com Link: https://lore.kernel.org/r/20240424101503.635364-4-quic_tengfan@quicinc.com [bjorn: Squashed the two changes, and updated commit message] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sc7280: Remove CTS/RTS configurationViken Dadhaniya
For IDP variant, GPIO 20/21 is used by camera use case and camera driver is not able acquire these GPIOs as it is acquired by UART5 driver as RTS/CTS pin. UART5 is designed for debug UART for all the board variants of the sc7280 chipset and RTS/CTS configuration is not required for debug uart usecase. Remove CTS/RTS configuration for UART5 instance and change compatible string to debug UART. Remove overwriting compatible property from individual target specific file as it is not required. Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20240424075853.11445-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: qcm6490-rb3: Enable gpi-dma and qup nodeViken Dadhaniya
Enable gpi-dma0, gpi-dma1 and qupv3_id_1 nodes for buses usecase on RB3gen2. Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240424054602.5731-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: add support for the SM8650-HDK boardNeil Armstrong
The SM8650-HDK is an embedded development platforms for the Snapdragon 8 Gen 3 SoC aka SM8650, with the following features: - Qualcomm SM8650 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Product Page: [3] [1] https://www.96boards.org/specifications/ [2] https://git.codelinaro.org/linaro/qcomlt/debugboard [3] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240422-topic-sm8650-upstream-hdk-v4-2-b33993eaa2e8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26dt-bindings: arm: qcom: Document the HDK8650 boardNeil Armstrong
Document the Qualcomm SM8650 based HDK (Hardware Development Kit) embedded development platform designed by Qualcomm and sold by Lantronix [1]. [1] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240422-topic-sm8650-upstream-hdk-v4-1-b33993eaa2e8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"Manivannan Sadhasivam
Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct node name for the controller instances. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-21-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy ↵Neil Armstrong
pcie1_phy_aux_clk The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-3-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy ↵Neil Armstrong
pcie1_phy_aux_clk The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gccNeil Armstrong
The PCIe Gen4x2 PHY found in the SM8450 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Now the pcie1_phy exposes 2 clocks, properly add the pcie1_phy provided clocks to the Global Clock Controller (GCC) node clocks inputs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-1-10c650cfeade@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: x1e80100: drop wrong usb-role-switch propertiesDmitry Baryshkov
The usb-role-switch property doesn't make sense for the USB hosts which are fixed to the host USB data mode. Delete usb-role-switch property from these hosts. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-12-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: delete wrong usb-role-switch propertiesDmitry Baryshkov
The usb-role-switch property doesn't make sense for the USB hosts which are fixed to either host or peripheral USB data mode. Delete usb-role-switch property being present in SoC dtsi. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-11-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650-mtp: connect USB-C SS port to QMP PHYDmitry Baryshkov
The lanes from the USB-C SS port are connected to the combo USB+DP QMP PHY rather than the SS port of the USB controller. Move the connection endpoint to the QMP PHY out port. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-10-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsiDmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-9-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsiDmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-8-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: move PHY's orientation-switch to SoC dtsiDmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-7-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8350: move PHY's orientation-switch to SoC dtsiDmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the board, it is a design property of the QMP PHY itself. Move the property from board DTS to SoC DTSI. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-6-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8650: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-5-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8550: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-4-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8450: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-3-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8350: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-2-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sm8150: move USB graph to the SoC dtsiDmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to the SoC dtsi file. They are linked in hardware in this way. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240429-usb-link-dtsi-v1-1-87c341b55cdf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: x1e80100-*: Allocate some CMA buffersKonrad Dybcio
In a fashion identical to commit 5f84c7c35d49 ("arm64: dts: qcom: sc8280xp: Define CMA region for CRD and X13s"), there exists a need for more than the default 32 MiB of CMA, namely for the ath12k_pci device. Reserve a 128MiB chunk to make boot-time failures like: cma: cma_alloc: reserved: alloc failed, req-size: 128 pages, ret: -12 go away. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240522-topic-x1e_cma-v1-1-b69e3b467452@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sc8180x: Fix LLCC reg property againBjorn Andersson
Commit '74cf6675c35e ("arm64: dts: qcom: sc8180x: Fix LLCC reg property")' transitioned the SC8180X LLCC node to describe each memory region individually, but did not include all the regions. The result is that Linux fails to find the last regions, so extend the definition to cover all the blocks. This also corrects the related DeviceTree validation error. Fixes: 74cf6675c35e ("arm64: dts: qcom: sc8180x: Fix LLCC reg property") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-sc8180x-llcc-reg-fixup-v1-1-0c13d4ea94f2@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: msm8996: add reset for display subsystemBarnabás Czémán
Add reset for display subsystem, make sure it gets properly reset. Signed-off-by: Barnabás Czémán <trabarni@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-mdss-reset-v1-1-c0489e8be0d0@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-26arm64: dts: qcom: sc8180x: Correct PCIe slave portsBjorn Andersson
The interconnects property was clearly copy-pasted between the 4 PCIe controllers, giving all four the cpu-pcie path destination of SLAVE_0. The four ports are all associated with CN0, but update the property for correctness sake. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-sc8180x-pcie-interconnect-port-fix-v1-1-f86affa02392@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-19 15:02:57 +0000