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2018-12-04drm/i915: Move register white-listing to the common workaround frameworkTvrtko Ursulin
Instead of having a separate list of white-listed registers we can trivially move this to the common workarounds framework. This brings us one step closer to the goal of driving all workaround classes using the same code. v2: * Use GEM_DEBUG_WARN_ON for the sanity check. (Chris Wilson) v3: * API rename. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203125014.3219-6-tvrtko.ursulin@linux.intel.com
2018-12-04drm/i915/selftests: Add tests for GT and engine workaround verificationTvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is not affecting workarounds not belonging to itself.) v2: * Rebase for series refactoring. * Add spinner for actual engine reset! * Add idle reset test as well. (Chris Wilson) * Share existing global_reset_lock. (Chris Wilson) v3: * intel_engine_verify_workarounds can be static. * API rename. (Chris Wilson) * Move global reset lock out of the loop. (Chris Wilson) v4: * Add missing rpm puts. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203125014.3219-5-tvrtko.ursulin@linux.intel.com
2018-12-04drm/i915: Verify GT workaround state after GPU initTvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver. Initially we only do this after GPU initialization. v2: Chris Wilson: * Simplify verification by realizing it's a simple xor and and. * Remove verification from engine reset path. * Return bool straight away from the verify API. v3: * API rename. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203125014.3219-4-tvrtko.ursulin@linux.intel.com
2018-12-04drm/i915: Introduce per-engine workaroundsTvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far the registers in 0x2xxx and 0xbxxx address range have been identified to be affected. This losing of applied workarounds has obvious negative effects and can even lead to hard system hangs (see the linked Bugzilla). Rather than just restoring this re-application, because we have also observed that it is not safe to just re-write all GT workarounds after engine resets (GPU might be live and weird hardware states can happen), we introduce a new class of per-engine workarounds and move only the affected GT workarounds over. Using the framework introduced in the previous patch, we therefore after engine reset, re-apply only the workarounds living in the affected MMIO address ranges. v2: * Move Wa_1406609255:icl to engine workarounds as well. * Rename API. (Chris Wilson) * Drop redundant IS_KABYLAKE. (Chris Wilson) * Re-order engine wa/ init so latest platforms are first. (Rodrigo Vivi) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945 Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203133341.10258-1-tvrtko.ursulin@linux.intel.com
2018-12-04drm/i915: Record GT workarounds in a listTvrtko Ursulin
To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied. The added data structure is a simple array of register, mask and value items, which is allocated on demand as workarounds are added to the list. This is a temporary implementation which later in the series gets fused with the existing per context workaround list handling. It is separated at this stage since the following patch fixes a bug which needs to be as easy to backport as possible. Also, since in the following patch we will be adding a new class of workarounds (per engine) which can be applied from interrupt context, we straight away make the provision for safe read-modify-write cycle. v2: * Change dev_priv to i915 along the init path. (Chris Wilson) * API rename. (Chris Wilson) v3: * Remove explicit list size tracking in favour of growing the allocation in power of two chunks. (Chris Wilson) v4: Chris Wilson: * Change wa_list_finish to early return. * Copy workarounds using the compiler for static checking. * Do not bother zeroing unused entries. * Re-order struct i915_wa_list. v5: * kmalloc_array. * Whitespace cleanup. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203133319.10174-1-tvrtko.ursulin@linux.intel.com
2018-12-04drm/i915: change i915_sw_fence license to MITJonathan Gray
Change the license of the i915_sw_fence files to MIT matching most of the other i915 files. This makes it possible to use them in a new port of i915 to OpenBSD. Besides some mechanical tree wide changes Chris Wilson is the sole author of these files with Intel holding the copyright. Intel's legal team have given permission to change the license according to Joonas Lahtinen. v2: expand commit message and note permission from Intel legal Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181129013051.17525-1-jsg@jsg.id.au
2018-12-04drm/i915: Complete the fences as they are cancelled due to wedgingChris Wilson
We inspect the requests under the assumption that they will be marked as completed when they are removed from the queue. Currently however, in the process of wedging the requests will be removed from the queue before they are completed, so rearrange the code to complete the fences before the locks are dropped. <1>[ 354.473346] BUG: unable to handle kernel NULL pointer dereference at 0000000000000250 <6>[ 354.473363] PGD 0 P4D 0 <4>[ 354.473370] Oops: 0000 [#1] PREEMPT SMP PTI <4>[ 354.473380] CPU: 0 PID: 4470 Comm: gem_eio Tainted: G U 4.20.0-rc4-CI-CI_DRM_5216+ #1 <4>[ 354.473393] Hardware name: Intel Corporation NUC7CJYH/NUC7JYB, BIOS JYGLKCPX.86A.0027.2018.0125.1347 01/25/2018 <4>[ 354.473480] RIP: 0010:__i915_schedule+0x311/0x5e0 [i915] <4>[ 354.473490] Code: 49 89 44 24 20 4d 89 4c 24 28 4d 89 29 44 39 b3 a0 04 00 00 7d 3a 41 8b 44 24 78 85 c0 74 13 48 8b 93 78 04 00 00 48 83 e2 fc <39> 82 50 02 00 00 79 1e 44 89 b3 a0 04 00 00 48 8d bb d0 03 00 00 <4>[ 354.473515] RSP: 0018:ffffc900001bba90 EFLAGS: 00010046 <4>[ 354.473524] RAX: 0000000000000003 RBX: ffff8882624c8008 RCX: f34a737800000000 <4>[ 354.473535] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff8882624c8048 <4>[ 354.473545] RBP: ffffc900001bbab0 R08: 000000005963f1f1 R09: 0000000000000000 <4>[ 354.473556] R10: ffffc900001bba10 R11: ffff8882624c8060 R12: ffff88824fdd7b98 <4>[ 354.473567] R13: ffff88824fdd7bb8 R14: 0000000000000001 R15: ffff88824fdd7750 <4>[ 354.473578] FS: 00007f44b4b5b980(0000) GS:ffff888277e00000(0000) knlGS:0000000000000000 <4>[ 354.473590] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 354.473599] CR2: 0000000000000250 CR3: 000000026976e000 CR4: 0000000000340ef0 <4>[ 354.473611] Call Trace: <4>[ 354.473622] ? lock_acquire+0xa6/0x1c0 <4>[ 354.473677] ? i915_schedule_bump_priority+0x57/0xd0 [i915] <4>[ 354.473736] i915_schedule_bump_priority+0x72/0xd0 [i915] <4>[ 354.473792] i915_request_wait+0x4db/0x840 [i915] <4>[ 354.473804] ? get_pwq.isra.4+0x2c/0x50 <4>[ 354.473813] ? ___preempt_schedule+0x16/0x18 <4>[ 354.473824] ? wake_up_q+0x70/0x70 <4>[ 354.473831] ? wake_up_q+0x70/0x70 <4>[ 354.473882] ? gen6_rps_boost+0x118/0x120 [i915] <4>[ 354.473936] i915_gem_object_wait_fence+0x8a/0x110 [i915] <4>[ 354.473991] i915_gem_object_wait+0x113/0x500 [i915] <4>[ 354.474047] i915_gem_wait_ioctl+0x11c/0x2f0 [i915] <4>[ 354.474101] ? i915_gem_unset_wedged+0x210/0x210 [i915] <4>[ 354.474113] drm_ioctl_kernel+0x81/0xf0 <4>[ 354.474123] drm_ioctl+0x2de/0x390 <4>[ 354.474175] ? i915_gem_unset_wedged+0x210/0x210 [i915] <4>[ 354.474187] ? finish_task_switch+0x95/0x260 <4>[ 354.474197] ? lock_acquire+0xa6/0x1c0 <4>[ 354.474207] do_vfs_ioctl+0xa0/0x6e0 <4>[ 354.474217] ? __fget+0xfc/0x1e0 <4>[ 354.474225] ksys_ioctl+0x35/0x60 <4>[ 354.474233] __x64_sys_ioctl+0x11/0x20 <4>[ 354.474241] do_syscall_64+0x55/0x190 <4>[ 354.474251] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4>[ 354.474260] RIP: 0033:0x7f44b3de65d7 <4>[ 354.474267] Code: b3 66 90 48 8b 05 b1 48 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 81 48 2d 00 f7 d8 64 89 01 48 <4>[ 354.474293] RSP: 002b:00007fff974948e8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 <4>[ 354.474305] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f44b3de65d7 <4>[ 354.474316] RDX: 00007fff97494940 RSI: 00000000c010646c RDI: 0000000000000007 <4>[ 354.474327] RBP: 00007fff97494940 R08: 0000000000000000 R09: 00007f44b40bbc40 <4>[ 354.474337] R10: 0000000000000000 R11: 0000000000000246 R12: 00000000c010646c <4>[ 354.474348] R13: 0000000000000007 R14: 0000000000000000 R15: 0000000000000000 v2: Avoid floating requests. v3: Can't call dma_fence_signal() under the timeline lock! v4: Can't call dma_fence_signal() from inside another fence either. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-2-chris@chris-wilson.co.uk
2018-12-04drm/vkms: Remove set but not used variable 'vkms_obj'YueHaibing
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/vkms/vkms_plane.c: In function 'vkms_prepare_fb': drivers/gpu/drm/vkms/vkms_plane.c:144:26: warning: variable 'vkms_obj' set but not used [-Wunused-but-set-variable] It never used since introduction in commit 8ce1bb0b5337 ("drm/vkms: map/unmap buffers in [prepare/cleanup]_fb hooks") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1543634444-186448-1-git-send-email-yuehaibing@huawei.com
2018-12-04drm/i915/dp: Fix inconsistent indentingChris Wilson
Always show the FEC capability as it is initialised to 0 before error. Fixing, drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181120202439.13017-2-chris@chris-wilson.co.uk
2018-12-04drm/sun4i: Add compatible for H6 display engineJernej Skrabec
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-9-jernej.skrabec@siol.net
2018-12-04drm/exynos/iommu: merge IOMMU and DMA codeAndrzej Hajda
As DMA code is the only user of IOMMU code both files can be merged. It allows to remove stub functions, after slight adjustment of exynos_drm_register_dma. Since IOMMU functions are used locally they can be marked static. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-04drm/exynos/iommu: replace preprocessor conditionals with C conditionalsAndrzej Hajda
Using C conditionals is preferred solution - it provides better code coverage, makes code more clear. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-04drm/exynos/iommu: move IOMMU specific stuff into exynos_drm_iommu.cAndrzej Hajda
Since __exynos_iommu* functions are used only in exynos_drm_iommu.c we can move them there. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-04drm/exynos/iommu: integrate IOMMU/DMA internal APIAndrzej Hajda
Exynos DRM drivers should work with and without IOMMU. Providing common API generic to both scenarios should make code cleaner and allow further code improvements. The patch removes including of exynos_drm_iommu.h as the file contains mostly IOMMU specific stuff, instead it exposes exynos_drm_*_dma functions and puts them into exynos_drm_dma.c. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-04drm/exynos/iommu: remove DRM_EXYNOS_IOMMU Kconfig symbolAndrzej Hajda
DRM_EXYNOS_IOMMU symbol is not configurable, it is always equal to EXYNOS_IOMMU. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-04drm/exynos: simplify DMA mappingAndrzej Hajda
Moving DMA mapping creation to drm_iommu_attach_device allows to avoid looping through all components and maintaining DMA device flags. v2: take care of configurations without IOMMU Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-12-03drm/i915: Move display device info capabilities to its own structJosé Roberto de Souza
This helps separate what capabilities are display capabilities. v3: Moving display struct right after flags (Lucas) Cc: Jani Nikula <jani.nikula@linux.intel.com> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-2-jose.souza@intel.com
2018-12-03drm/i915: Add HAS_DISPLAY() and use itJosé Roberto de Souza
Right now it is decided if GEN has display by checking the num_pipes, so lets make it explicit and use a macro. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-1-jose.souza@intel.com
2018-12-03drm/i915/dp: Fix link compute m_n calc for DSCManasi Navare
Fix the intel_link_compute_m_n in case of display stream compression. This patch passes the compressed_bpp to intel_link_compute_m_n if compression is enabled. Fixes: a4a157777c80 ("drm/i915/dp: Compute DSC pipe config in atomic check") Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181201010412.32372-1-manasi.d.navare@intel.com
2018-12-03drm/v3d: Add more tracepoints for V3D GPU rendering.Eric Anholt
The core scheduler tells us when the job is pushed to the scheduler's queue, and I had the job_run functions saying when they actually queue the job to the hardware. By adding tracepoints for the very top of the ioctls and the IRQs signaling job completion, "perf record -a -e v3d:.\* -e gpu_scheduler:.\* <job>; perf script" gets you a pretty decent timeline. Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20181201005759.28093-5-eric@anholt.net Reviewed-by: Dave Emett <david.emett@broadcom.com>
2018-12-03drm/v3d: Add missing fence timeline name for TFU.Eric Anholt
We shouldn't be returning v3d-render for our new queue. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 83d5139982db ("drm/v3d: Add support for submitting jobs to the TFU.") Link: https://patchwork.freedesktop.org/patch/msgid/20181201005759.28093-6-eric@anholt.net Reviewed-by: Dave Emett <david.emett@broadcom.com>
2018-12-03drm/syncobj: use dma_fence_get_stubChristian König
Extract of useful code from the timeline work. Let's use just a single stub fence instance instead of allocating a new one all the time. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Link: https://patchwork.freedesktop.org/patch/265248/
2018-12-03dma-buf: add dma_fence_get_stubChristian König
Extract of useful code from the timeline work. This provides a function to return a stub or dummy fence which is always signaled. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Link: https://patchwork.freedesktop.org/patch/265248/
2018-12-03drm/i915/sysfs: make attrs arrays constJani Nikula
They don't need to be modified. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181004143750.30880-2-jani.nikula@intel.com
2018-12-03sysfs: constify sysfs create/remove files harderJani Nikula
Let the passed in array be const (and thus placed in rodata) instead of a mutable array of const pointers. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181004143750.30880-1-jani.nikula@intel.com
2018-12-03drm/amdgpu: Implement concurrent asic reset for XGMI.Andrey Grodzovsky
Use per hive wq to concurrently send reset commands to all nodes in the hive. v2: Switch to system_highpri_wq after dropping dedicated queue. Fix non XGMI code path KASAN error. Stop the hive reset for each node loop if there is a reset failure on any of the nodes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/amdgpu: Handle xgmi device removal.Andrey Grodzovsky
XGMI hive has some resources allocted on device init which needs to be deallocated when the device is unregistered. v2: Remove creation of dedicated wq for XGMI hive reset. v3: Use the gmc.xgmi.supported flag Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/amdgpu/psp: Update waiting in psp mode1 reset.Andrey Grodzovsky
No point in use mdelay unless running from interrupt context (which we are not) This is busy wait which will block the CPU for the entirety of the wait time. Also, reduce wait time to 500ms as it is done in refernce code because 1s might cause PSP FW TO issues during XGMI hive reset. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/amdgpu: add missing error handlingChristian König
We ignored the return code here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/amdgpu: remove amdgpu_bo_backup_to_shadowChristian König
It is unused. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/amdgpu: add a xgmi supported flagAlex Deucher
Use this to track whether an asic supports xgmi rather than checking the asic type everywhere. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-12-03drm/i915/vgpu: Disallow loading on old vGPU hostsChris Wilson
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we actually broke the force-mmio mode for our execlists implementation. No one noticed, so ergo no one is actually using an old vGPU host (where we required the older method) and so can simply remove the broken support. v2: csb_read can go as well (Mika) Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181130125954.11924-1-chris@chris-wilson.co.uk
2018-12-03drm/panel: simple: Add AUO G101EVN010 panel supportAlex Gonzalez
The change adds support for the AU Optronics G101EVN010 10.1" TFT LCD panel. Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com> Reviewed-by: Rob Herring <robh@kernel.org> [treding@nvidia.com: sort new entry alphabetically] Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/1540480173-12009-2-git-send-email-alex.gonzalez@digi.com
2018-12-03drm/tegra: sor: Support for audio over HDMIThierry Reding
This code is very similar to the audio over HDMI support on older chips. Interoperation with the audio codec is done via a pair of codec scratch registers and an interrupt that is raised at the SOR when the codec has written those registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-12-03drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rateChris Wilson
Change the on-cpu check to on-runqueue to catch if the waiter has been woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to perform the seqno check) but is sleeping due to being preempted off the cpu. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-1-chris@chris-wilson.co.uk
2018-12-03drm/i915/icl: add pll mapping for DSIJani Nikula
Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function. v2: add posting read (Madhav) Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203094326.28294-1-jani.nikula@intel.com
2018-12-03drm/i915/icl: Ungate DSI clocksMadhav Chauhan
Ungate the clocks on the selected port. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2a01b3158feda624f98581b780854fe3df8c328d.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Gate clocks for DSIMadhav Chauhan
As per BSPEC, depending on the DSI transcoder being used, DDI clock for the associated port should be gated. This patch does the same. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e032bc3d8fff91b8c2631c73121268214615a7e8.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: add dummy DSI GPIO element execution functionJani Nikula
Add dummy debug logging GPIO element execution function for ICL. Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f59009ea0a0ebc489a5ec66f387d9dcf7264141f.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define display GPIO pins for DSIMadhav Chauhan
Display Pins are the only GPIOs that need to be used by driver for DSI panels. So driver should now have its own implementation to toggle these pins based on GPIO info received from VBT sequences. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e7e3bb05d4f48b1876169a69f495bcf6d511fda5.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan
There are two panel power sequencers. Each register has two addressable instances. This patch defines both the instances of Panel power control register Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/99bb687b17a9165527a6210a79271c8175c8a4e3.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan
This patch define missing bitfield for shortplug ctl ddi register which will be used for ICL DSI GPIO programming. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4b9feb75eb6c303556b91c8a23c505a4593a99a1.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get pipe timings for DSIMadhav Chauhan
Transcoder timings for Gen11 DSI encoder is available at pipe level unlike in older platform where port specific registers need to be accessed. v2 by Jani: - get timings for (!dsi || icl) instead of (dsi && icl). Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f60e0c1aee08248e758da3219d3239898b43ba41.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Consider DSI for getting transcoder stateMadhav Chauhan
For Gen11 DSI, we use similar registers like for eDP to find if DSI encoder is connected or not to a pipe. This patch refactors existing hsw_get_transcoder_state() to handle this. v2 by Jani: - Add WARN_ON(dsi && edp) (Ville) Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2e10b977dfc7aa985a8559d6cd59ed0981848e95.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan
This patch configures DSI video mode dual link by programming DSS_CTL registers. v2: Use new bitfield definitions from Anusha's patch Correct register to be programmed and use max depth buffer value (James) v3 by Jani: - checkpatch fixes Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d8962f4e1beffc2099b8bef8cb5a5191aa1d9efd.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan
This patch implements compute config for Gen11 DSI encoder which is required at the time of modeset. For DSI 8X clock is AFE clock which is 5 times port clock. v2 by Jani: - drop the enable nop hook - fixed_mode is always true - HAS_GMCH_DISPLAY() is always false v3 by Jani: - set encoder->compute_config dropped during rebase v4 by Jani: - squash Vandita's port clock patch - remove todo comment Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a21574173caa5e2932d9e3c537b0931097ab5ac2.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan
This patch read out the current hw state for DSI and return true if encoder is active. v2 by Jani: - Squash connector get hw state hook here - Squash encode get hw state fix here v3 by Jani: - Add encoder->get_power_domains() (Imre) v4 by Jani: - Make encoder->get_power_domains() sensible... (Imre) v5 by Jani: - Power domains are bit positions, not bits (Stan, Imre) Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec6da32a55b9fb045527f14e41ed3dce86d46a97.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add get config functionality for DSIVandita Kulkarni
This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Use the same method to get port clock like other DDI encoders. Used during the atomic modeset. v2 by Jani: - Squash Madhav's and Vandita's get config bits together - Move cnl_calc_wrpll_link() to intel_drv.h - Drop extra temp variables - Use enc_to_intel_dsi() instead of open coding Co-developed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f21fa4258068d04582f2bf30735e5536a8043bdf.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan
Allocate DSI host structure for each DSI port available on gen11 and register them with DSI fwk of DRM. Some of the DSI host operations are also registered as part of this. Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI exported functions. A wrapper function is also added as "DSI host transfer" for sending DSI data/cmd. Add DSI packet payload to command payload queue using credit based mechanism for *long* packets. v2 by Jani: - indentation - Use the new credit available helper - Use int for free_credits - Add intel_dsi local variable for better code flow - Use the new credit available helper - Use int for free_credits, i, and j v3 by Jani: - Squash DSI host allocation and transfer patches together Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/af4f168ed8737d44687d8b6f21ecaa7e805eb695.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Fill DSI ports infoMadhav Chauhan
This patch fills backlight, CABC and general port info for Gen11 DSI. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/48c9f867d61a60dc7c2ce744ac2325655652c55f.1543500286.git.jani.nikula@intel.com
generated by cgit (git 2.34.1) at 2025-09-13 16:22:51 +0000