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2021-12-16arm64: tegra: Rename TCU node to "serial"Thierry Reding
The TCU is basically a serial port (albeit a fancy one), so it should be named "serial". Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clockThierry Reding
The "core_m" clock is not documented in the Tegra194 PCIe device tree bindings, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unused properties for Tegra194 PCIeThierry Reding
The num-viewport property is never used and can be dropped, whereas the "iommus" property is not needed since we use "iommu-map-mask" and "iommu-map" already. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra194 HSP compatible stringThierry Reding
The HSP instances on Tegra194 are not fully compatible with the version found on Tegra186, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unsupported nvidia,lpdr propertyThierry Reding
The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property, so drop them from the device trees that have listed them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chipsThierry Reding
The standard "jedec," vendor prefix should be used for SPI NOR flash chips. This allows the right DT schema to be picked for validation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unit-address for audio card graph endpointsThierry Reding
Audio graph endpoints don't have a "reg" property, so they shouldn't have a unit-address either. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Adjust length of CCPLEX cluster MMIO regionThierry Reding
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra186 compatible string listThierry Reding
The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename power-monitor input nodesThierry Reding
Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename thermal zones nodesThierry Reding
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Sort Tegra132 XUSB clocks correctlyThierry Reding
Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unused AHCI clocks on Tegra132Thierry Reding
The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra132 I2C compatible string listThierry Reding
The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add OPP tables on Tegra132Thierry Reding
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix compatible string for Tegra132 timerThierry Reding
The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Remove unsupported properties on NorrinThierry Reding
The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix unit-addresses on NorrinThierry Reding
The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add native timer support on Tegra186Thierry Reding
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename top-level regulatorsThierry Reding
Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename top-level clocksThierry Reding
Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add ISO SMMU controller for Tegra194Jon Hunter
The display controllers are attached to a separate ARM SMMU instance that is dedicated to servicing isochronous memory clients. Add this ISO instance of the ARM SMMU to device tree. Please note that the display controllers are not hooked up to this SMMU yet, because we are still missing a means to transition framebuffers used by the bootloader to the kernel. This based upon an initial patch by Thierry Reding <treding@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194Jon Hunter
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add support to enumerate SD in UHS modePrathamesh Shete
Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit supportMikko Perttunen
The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Describe Tegra234 CPU hierarchyThierry Reding
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add main and AON GPIO controllers on Tegra234Thierry Reding
These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add Tegra234 TCU deviceMikko Perttunen
Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fill in properties for Tegra234 eMMCMikko Perttunen
Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Update Tegra234 BPMP channel addressesMikko Perttunen
On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add clock for Tegra234 RTCMikko Perttunen
The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fixup SYSRAM referencesThierry Reding
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dtThierry Reding
dt-bindings: memory: Add Tegra234 support This stable tag contains the addition of the EMC clock ID and an initial list of memory client IDs for Tegra234 and will be shared between the memory and ARM SoC trees.
2021-12-16dt-bindings: misc: Convert Tegra MISC to json-schemaThierry Reding
Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: memory: tegra: Add Tegra234 supportThierry Reding
Document the variant of the memory controller and external memory controllers found on Tegra234 and add some memory client and SMMU stream ID definitions for use in device tree files. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: Add YAML bindings for NVENC and NVJPGJon Hunter
Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: memory: tegra: Update for Tegra194Thierry Reding
The #interconnect-cells properties are required to hook up memory clients to the MC/EMC in interconnects properties. Add a description for these properties. For the nested EMC controller, the list of required properties was missing. Add it so that the validation can be more strict. Also, allow multiple reg entries required by Tegra194 and later. While at it, also remove the dummy BPMP node from the example because it is incomplete and fails validation. It's also not necessary for this file and the BPMP DT schema already has a full example. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: sram: Document NVIDIA Tegra SYSRAMThierry Reding
Tegra SoCs have extra on-chip RAM that can be used for inter-processor communication. Tegra186 and later make use of it to establish a two-way channel between the CCPLEX and BPMP. Add missing compatible strings for Tegra186 and Tegra194 as well as a new compatible string for Tegra234. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: Update headers for Tegra234Mikko Perttunen
Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: tegra: Document Jetson AGX Orin (and devkit)Thierry Reding
Add the compatible strings for the Jetson AGX Orin and the corresponding developer kit. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: tegra: Describe recent developer kits consistentlyThierry Reding
Add descriptions to entries that were missing one and don't try to combine multiple entries into one to avoid confusion. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulatorBiju Das
Add vdd core regulator (1.1 V). This patch add regulator support for gpu. The H/W manual mentions nothing about a gpu regulator. So using vdd core regulator for gpu. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-16arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU nodeBiju Das
Add Mali-G31 GPU node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-16Merge tag 'omap-for-v5.17/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.17 merge window These changes are mostly minor non-urgent fixes for typos and binding checks. The system-power-controller gets configured for more am3 devices as it's not am335x-boneblack speicif. For for am437x we add magnetic card reader support. Note that the asahi-kasei,ak8975 binding changes may produce a new binding check warning as the binding related change is merged separately. * tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value ARM: dts: am437x-gp-evm: enable ADC1 ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module ARM: dts: am437x-cm-t43: Use a correctly spelled DT property ARM: dts: am335x-icev2: Add system-power-controller to RTC node ARM: dts: am335x-boneblack-common: move system-power-controller ARM: dts: elpida_ecb240abacn: Change Elpida compatible Link: https://lore.kernel.org/r/pull-1639659798-679261@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16Merge tag 'socfpga_dts_update_for_v5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v5.17 - Update N5X to include qspi, usb and ethernet - Adjust NAND partition size for Agilex and Stratix10 * tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: Update NAND MTD partition for Agilex and Stratix 10 arm64: dts: n5x: add qspi, usb, and ethernet support Link: https://lore.kernel.org/r/20211215164545.300273-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16arm64: dts: allwinner: h6: Add Hantro G2 nodeJernej Skrabec
H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com
2021-12-15Merge tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux into ↵Arnd Bergmann
arm/dt Apple SoC DT updates for 5.17, round 2: - Various cleanups (removing useless props, sorting nodes, renaming things) - Add PMGR min-state binding & props (see PMGR pull for driver change) - Initial compatibles for t600x machines (M1 Pro/Max). This covers the bindings that just need compatible bumps & minor tweaks, no driver changes. - Add watchdog node (driver not merged yet, hopefully will be; binding went in the previous pull) - Add missing power-domains property to the mailbox binding * tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux: dt-bindings: mailbox: apple,mailbox: Add power-domains property arm64: dts: apple: t8103: Sort nodes by address arm64: dts: apple: t8103: Rename clk24 to clkref arm64: dts: apple: t8103: Add watchdog node dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible dt-bindings: pci: apple,pcie: Add t6000 support dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles arm64: dts: apple: t8103: Add apple,min-state to DCP PMGR nodes dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop arm64: dts: apple: t8103: Remove PCIe max-link-speed properties Link: https://lore.kernel.org/r/a24faafd-f2ae-c3a7-5327-b27da7d9e34b@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-15Merge tag 'stm32-dt-for-v5.17-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT for v5.17, round 1 Highlights: ---------- -MCU: - fix ili9341 for dtbs_check warnings on stm32f429 disco. - MPU: - ST boards: - tune HS USB phys on stm32mp15 EV1 and DKx boards. - add pull-up on USART3/UART7 RX pins on STM32MP15 DKx boards. - use correct pinctrl setting for STUSB1600 on STM32MP15 DK boards. - ENGICAM: - enable LVDS pannel on i.Core STM32MP1 EDIMM2.2. - add "i.Core STM32MP1 C.TOUCH 2.0 10.1" OF" support: EDIMM compliant general purpose carrier board with ETH 10/100, WIFI/BT, CAN, ... * tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco Link: https://lore.kernel.org/r/dfe942db-5af7-bb82-22b6-3bd866c9017d@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-15dt-bindings: mailbox: apple,mailbox: Add power-domains propertyHector Martin
This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Reviewed-by: Sven Peter <sven@svenpeter.dev> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-15arm64: dts: apple: t8103: Sort nodes by addressHector Martin
We decided to keep SoC nodes sorted by address for sanity; fix a couple that slipped into the wrong place. Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
generated by cgit (git 2.34.1) at 2025-09-15 08:28:58 +0000