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2019-02-15arm64: dts: sdm845: Fixup dependency on RPMPD includesAndy Gross
This patch fixes a dependency issue with the RPMPD dt bindings. This temporarily removes the include file and adds hardcoded values for the OPPs until the other changes full land. This will be addressed in 5.2. Fixes: 5b6f186f0abb ("arm64: dts: sdm845: Add rpmh powercontroller node") Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-07arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN nodeDouglas Anderson
When commit 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") was posted upstream no clocks were specified. However, when the pack was picked into the Chrome OS kernel tree (allegedly directly from the mailing list post) it had clock properties. I presume that the clock should be there, so let's add it. Fixes: 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> [bjorn: Add also the required iommus property] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: qcom: sdm845: Define iommus for USB controllersBjorn Andersson
The USB controllers need to be associated with their respective IOMMU bank, so define this on the dwc3 nodes. Also add dma-ranges to the qcom-dwc3 nodes to make the bus' DMA mask propagate to the dwc3 controller instances. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2Bjorn Andersson
With apps_smmu initializing the SMMU we must specify iommus property for the sdhc controller. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: sdm845: wireup the thermal trip points to cpufreqAmit Kucheria
Since all cpus in the big and little clusters, respectively, are in the same frequency domain, use all of them for mitigation in the cooling-map. We end up with two cooling devices - one each for the big and little clusters. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: msm8916: remove bogus argument to the cpu clockNiklas Cassel
The apcs node has #clock-cells = <0>, which means that those who references it should specify 0 arguments. The apcs reference in the cpu node incorrectly specifies an argument, remove this bogus argument. Fixes: 65afdf458360 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: sdm845: Add interconnect provider DT nodesDavid Dai
Add RSC (Resource State Coordinator) provider dictating network-on-chip interconnect bus performance found on SDM845-based platforms. Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8996: Disabled VFE SMMUBjorn Andersson
Initializing the SMMU trips a security violation, so disable the VFE SMMU for now. Fixes: f3442ab97257 ("arm64: dts: qcom: msm8996: Add VFE SMMU node") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: qcs404: Add rpmcc nodeBjorn Andersson
Add the rpm clock controller node, to provide the low-noise baseband clock for the USB PHYs, among other things. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8998: Add rpmcc nodeMarc Gonzalez
Add MSM8998 Resource Power Manager Clock Controller DT node. Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8998: Add USB-related nodesJeffrey Hugo
Add nodes for USB and related PHYs. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: qcs404: Add QUP I2C and SPI nodesBjorn Andersson
Define all six QUP controllers, both as SPI and I2C, allowing boards to enable these as needed. Associated pinmux states are also defined, to require only pinconf states to be specified by the boards, as they are enabled. Note that SPI has not been tested. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: qcs404: Define remaining UARTsBjorn Andersson
Add the BLSP2 BAM and add the remaining four UARTs found on the QCS404 platform. Note that these has not been tested. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: qcs404: Specify pinctrl state for UARTBjorn Andersson
BLSP1 UART2 is used as debug uart on the EVB development board, define pinmux state for the UART in the platform dtsi and pinconf state for it in the board dts. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Fix lpasscc regBjorn Andersson
Fix up the lpasscc address and size, missed during the conversion to address- and size-cells of 2. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Remove the duplicate header inclusionSai Prakash Ranjan
Remove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f8140521 ("arm64: dts: sdm845: add prng-ee node"). Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> [bjorn: Also fix sort order of lpasscc include, while we're there] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add reserve-memory nodesSibi Sankar
Add reserve-memory nodes for mpss and mba required for remoteproc mss pil. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM nodeEvan Green
Add the gpio-ranges property to the TLMM node so that GPIO hogs work. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Extend ranges and describe DMA spaceBjorn Andersson
For devices attached to an IOMMU, translation between IOVA and physical addresses is no longer 1:1 and dma-ranges should be specified to describe the available IOVA address space. On SDM845 the busses are implemented with 36 address bits, so dma-ranges must be defined to reduce the size of the IOVA address space from the 48 bits supported by the SMMU. Without this DMA allocations may end up with IOVAs outside the valid range, that gets truncated by the bus between the device and its translation unit. Also extend ranges to describe the available address space. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Increase address and size cells for socBjorn Andersson
The busses on SDM845 provides 36 address bits, extend the address and size cells to make it possible to describe this in "ranges" and "dma-ranges". While touching all reg properties, addresses are padded to 8 digits. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add rpmh powercontroller nodeRajendra Nayak
Add the DT node for the rpmhpd powercontroller. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: msm8996: Add rpmpd device nodeRajendra Nayak
Add rpmpd device node and its OPP table Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add WCN3990 WLAN module device nodeGovind Singh
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on SDM845 soc. Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add PDC Global reset driver nodeSibi Sankar
This patch adds the node to support PDC Global reset driver on SDM845 SoCs Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add SCM DT nodeSibi Sankar
Add SCM DT node to enable SCM functionality on SDM845. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Fix pcs_misc region address for UNI PHYManu Gautam
Correct address for pcs_misc register region of USB3 QMP UNI PHY. These registers are used during runtime-suspend/resume routines of phy. Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add lpasscc nodeTaniya Das
This adds the low pass audio clock controller node to sdm845 based on the example in the bindings. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [bjorn: Disabled lpasscc node, as it's normally protected] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add videocc nodeTaniya Das
This adds the video clock controller node to sdm845 based on the examples in the bindings. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add gpu clock controller nodeDouglas Anderson
Add the GPU clock controller nodes as per the example. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add qspi (quad SPI) nodeDouglas Anderson
This adds the Quad SPI controller to the main sdm845 device tree file. Boards will be expected to assign the proper pinctrl depending on how many chip selects they have hooked up and how many data lines. This depends on commit 48735597f7bd ("clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header") to add the needed defines. It also shouldn't land until the patch ("dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation") [1] lands. [1] https://lkml.kernel.org/r/20181002214709.162330-1-ryandcase@chromium.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: msm8998: Enumerate i2c controllersJeffrey Hugo
msm8998 has a dozen i2c controllers which can be used to connect to board specific peripherals. Enumerate the controllers so that boards can wire up as needed. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> [bjorn: Renumbered labels on BLSP2 nodes] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: msm8998-mtp: Increase load on l21 for sdcardJeffrey Hugo
l21 is used as sdcard vmmc, and needs the load increased to prevent voltage drop issues with some sdcards. This addresses -84 errors seen during sdcard init with SDR104 cards. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24Merge branch 'arm64-for-5.1' into arm64-for-5.1-2Andy Gross
2019-01-24Merge tag 'qcom-fixes-for-5.0-rc3' into arm64-for-5.1-2Andy Gross
Qualcomm ARM64 Fixes for 5.0-rc3 * Fix irq controller compatible for the MSM8996 platforms
2019-01-24arm64: dts: qcom: sdm845: Add dpu to sdm845 dts fileJeykumar Sankaran
DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. This change adds MDSS and DSI nodes to enable display on the target device. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu (Rob H) - Use assigned-clocks to set initial clock frequency(Rob H) Changes in v3: - added IOMMU node - Fix device naming (remove _phys) - Use correct IRQ_TYPE in interrupt specifiers Changes in v4: - move mdss node to preserve the unit address sort order - remove _clk suffix from dsi clocks (both the comments are from Doug Anderson) Changes in v5: - Keep the device status "disabled" by default (Bjorn Andersson) - Use MDSS_GDSC macro (Jordan) - Fix phy-names (Jordan) - List reg ranges in numerical order (Jordan) Changes in v6: - Separating this patch out of the series - fix phy-names Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: add msm8996 compatible to gicv3Srinivas Kandagatla
Add compatible to gicv3 node to enable quirk required to restrict writing to GICR_WAKER register which is restricted on msm8996 SoC in Hypervisor. With this quirk MSM8996 can at least boot out of mainline, which can help community to work with boards based on MSM8996. Without this patch Qualcomm DB820c board reboots on mainline. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: pm8916: Add PON watchdog nodeLoic Poulain
Add watchdog child node to the PM8916 PON device. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: Correct "gpiio" typo in msm8996-pinsJakob Wuhrer
gpiio5 is missspelt in msm8996-pins.dtsi, fix that. Signed-off-by: Jakob Wuhrer <jakobwuhrer@airmail.cc> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: apq8016-sbc: Increase load on l11 for SDCARDLoic Poulain
In the same way as for msm8974-hammerhead, l11 load, used for SDCARD VMMC, needs to be increased in order to prevent any voltage drop issues (due to limited current) happening with some SDCARDS or during specific operations (e.g. write). Tested on Dragonboard-410c and DART-SD410 boards. Fixes: 4c7d53d16d77 (arm64: dts: apq8016-sbc: add regulators support) Reported-by: Manabu Igusa <migusa@arrowjapan.com> Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: pms405: Export PMIC temperature to thermal frameworkAmit Kucheria
The PMS405 PMIC has an ADC that exposes the on-die temperature that we wire up to spmi-temp-alarm thermal driver. This allows the PMIC temperature to be exposed to Linux through the thermal framework. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: qcs404: Add WCN3990 WLAN module device nodeGovind Singh
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on qcs404 soc. Optional clock and regulator controls are not yet available in upstream, hence add them once available. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: qcs404: sdcc1: enable HS400Jorge Ramirez-Ortiz
The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: sdm845: Add cpufreq device nodeTaniya Das
This change adds the cpufreq node as per the bindings example for SDM845. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add USB PHY lane twoEvan Green
Add the second lane registers for the USB PHY, now that the QMP phy bindings have been updated. This way the driver can stop reaching beyond its register region to get at the second lane. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtpCan Guo
Enable the UFS host controller and PHY on sdm845-mtp. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Can Guo <cang@codeaurora.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: add UFS controllerEvan Green
Add the UFS controller and PHY to SDM845. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> [bjorn: Add iommu context for the host controller] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: sdm845: Add node for arm,mmu-500Vivek Gautam
Add device node for arm,mmu-500 available on sdm845. This MMU-500 with single TCU and multiple TBU architecture is shared among all the peripherals except gpu. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add SD nodes for sdm845-mtpEvan Green
Enable support for one of the micro SD slots on the MTP. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-14arm64: dts: qcom: sdm845: Add SD nodeEvan Green
Add one of the two SD controllers to SDM845. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-06Linux 5.0-rc1v5.0-rc1Linus Torvalds
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