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The T3/R40/V40 using the same sdk and config file in allwinner
sdk, it seem they are the same SOC just with different name, so
compatible with R40.
The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors,
leds, buttons, and sell on:
https://item.taobao.com/item.htm?spm=2013.1.w4023-4203040713.25.62704cce7UCgLS&id=557154455330
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 1/2 GB DDR3 DRAM
- 8 GB eMMC
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- 2 LVDS connectors
- 24 bit RGB LCD connector
- HDMI output
- DVP camera interface (support 500w cmos camera)
- GPIO connectors
- 5 TTL uarts and 2 RS232 uarts
- 1 RS485 connector
- support i2c capacitive tp and usb infrared tp
- boot control, reset and user buttons
- 3.5mm headphone and 3.5mm mic jack
- 100M RJ45
- micro SD card slot
- DC power jack
- RCT power slot
- 1 CVBS TVIN
- 1 CVBS TVOUT
- 2 customer leds
- 1 buzzer
- 1 minipcie
- I2C output
- SPI output
- PCM output
- wifi and bt connector reserved.
Board info can find here:
https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add Allwinner SoC T3 document and fix format.
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The pwm-backlight driver initializes BLON (the enable gpio) to
output-high if the gpio is input on probe. Initializing the gpio
to output-low before the driver probes prevents this action by
the pwm-backlight driver and gets rid of a nasty blink of full
backlight with an uninitialized panel.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch at91sam9rl boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch at91sam9x5 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch at91sam9263 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch at91sam9261 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch at91sam9260 and at91sam9g20 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch sama5d2 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Switch sama5d4 boards to the new PMC clock bindings.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
different clocks for the peripherals in the SoC. The Static Memory
controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the
master clock directly. This clock is then used by the code for the NAND
controller to calculate the timings for the controller, and we end up with
slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The Orange Pi Lite 2 and Orange Pi One Plus both have two LEDs, one red
and one green. These are driven directly by GPIO lines in an active high
arrangement. The red LED is labeled "power", so it is set to be on by
default.
Note that the default drive current for the GPIO lines makes the LEDs
very bright.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design.
This patch enables all the USB 2.0 related device nodes, and sets the
VBUS regulator supplies and OTG ID detection GPIO.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design. This 5V rail also supplies the various inputs to the
PMIC.
This patch adds a board wide 5V regulator and sets it as the input to
the PMIC inputs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The SoC-specific compatible should come before the fallback compatible
string when multiple compatible strings are present, but the sequence is
wrong currently on H6 EMAC node (A64 fallback before H6 compatible).
Fix the sequence.
Fixes: c8ced5516d23 ("arm64: allwinner: h6: add EMAC device nodes")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali" along with reset line.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add sleep state for beeper pins. Without this there was a power
increase during the suspend and standby states on V3_3D domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently uart0 uses pinctrl config set by bootloader so
create default state that can be restored after a suspend
event.
Also, modify uart0 pinctrl to include RTS and CTS pins as by
default these are not in a mode for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add pinctrl data for ddr_vtt_toggle pin so that it is configured
for proper state during DeepSleep0. The pin should enter DS0 off mode
and hold the line low so VTT regulator is kept off while suspended.
It is also important for the PULLUP to be set on this pin so that
on removal of isolation, the VTT line is pulled high as a requirement
for bringing the DDR3 out of self-refresh.
This toggling is dependent on the IO isolation controlled by the
wkup_m3. Without placing the IOs into isolation the DS0 states set for
the pin will not be latched into effect during suspend.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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When compiling the kernel with Clang, the following warning appears:
arch/arm/boot/dts/omap3-gta04.dtsi:385:56: warning: '/*' within block comment [-Wcomment]
/* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp_clks */
^
1 warning generated.
Fixes: 3c10507a39e8 ("ARM: dts: omap3-gta04: add mcbsp (audio subsystem) pinmux")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The EEPROM under I2C2 was put by mistake in the dts.
Remove it as it is not really present on the real hardware.
Fixes: ceef0396f367 ("ARM: dts: imx: add ZII RDU1 board")
Reported-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This patch adds PCI express channel 0 device node to the R8A77990 SoC
and enables PCIEC0 PCI express controller on the Ebisu board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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PMS405 also features PON block, so add PON and PWRKEY nodes
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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We can use BAM DAM for serial UART data transfers, so add it
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the BAM DMA instance found in BLSP1 node of the QCS404
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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RNG hardware in QCS404 features (Execution Environment) EE for
HLOS to use, add the node for prng-ee for QCS404.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the TrustZone based remoteproc nodes and their glink edges for
adsp, cdsp and wcss. Enable them for EVB common DTS.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the scm firmware node to QCS404
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the GPIOs present on PMS405 chip.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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RTC is found on PMIC PMS405 and is same as other PMIC used, so add the
rtc node with compatible as qcom,pm8941-rtc
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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PMS405 is used in QCS405-EVB so include that with SPMI nodes
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the pms405 DT file with spmi node.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the sdcc1 node and enable it for the QCS404-EVB.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the QCS404 TLMM pinctrl node with its three tiles.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the RPM regulators found in PMS405 which is used in qcs404-evb
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global
and smem nodes it depends on.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the reserved memory regions in QCS404
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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QCS404 has two EVBs, EVB-1000 and EVB-4000. These boards are mostly
similar with few differences in the peripherals used.
So use a common qcs404-evb.dtsi which contains the common parts and use
qcs404-evb-1000.dts and qcs404-evb-4000.dts for diffs
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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