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2013-10-11Merge tag 'keystone-soc-for-arm-soc' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/soc From Santosh Shilimkar: SOC updates for Keystone II devices: - Clock tree support - Clock management support using PM core - Keystone config update for EMDA with ack from Vinod - Enable SPI and I2C drivers * tag 'keystone-soc-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: (510 commits) ARM: keystone: Enable I2C and SPI bus support ARM: keystone: Select TI_EDMA to be able to enable SPI driver dma: Allow TI_EDMA selectable for ARCH_KEYSTONE ARM: dts: keystone: Add the SPI nodes ARM: dts: keystone: Add i2c device nodes ARM: keystone: add PM domain support for clock management ARM: keystone: Enable clock drivers ARM: dts: keystone: Add clock phandle to UART nodes ARM: dts: keystone: Add clock tree data to devicetree +Linux 3.12-rc4 Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-10-11Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard
That documentation was mostly useful when we didn't have any documentation for those SoCs, which is not the case anymore. Remove this, since it should live in the DT anyway. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mark Rutland <mark.rutland@arm.com>
2013-10-11Documentation: dt: Remove interrupt sources list for Allwinner SoCsMaxime Ripard
That documentation was mostly useful when we didn't have any documentation for those SoCs, which is not the case anymore. Remove this, since it should live in the DT anyway. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mark Rutland <mark.rutland@arm.com>
2013-10-11Documentation: sunxi: Update Allwinner SoC documentationMaxime Ripard
Since that document was first submitted, some new SoCs have been announced/released by Allwinner. Update the documentation to mention those and the related documents. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-11Documentation: sunxi: Update A13 user manual dead linkMaxime Ripard
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-11Merge tag 'for-v3.13/hwmod' of ↵Tony Lindgren
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod Some OMAP hwmod changes for 3.13. Significant changes here include: - support for moving some of the hwmod flags to DT data - support for the SSI, hardware spinlock, USB host/TLL, and RNG IP blocks for various OMAPs - a fix that again decouples hwmod data changes from unrelated DT data patchsets Basic test logs are available at: http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/ The summary reports that the 4460varsomom boots are failing, but this looks incorrect - it's probably a bug in the validation scripts here.
2013-10-10ARM: keystone: Enable I2C and SPI bus supportSantosh Shilimkar
Keystone I2C dnd SPI driver updates are already merged so lets enable them in config. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10ARM: keystone: Select TI_EDMA to be able to enable SPI driverSantosh Shilimkar
Select the TI EDMA to be able to enable SPI driver on Keystone SOCs. Keystone SOCs share the EDMA IP with other TI SOCs. Note that EDMA support hasn't been added and tested yet for Keystone SOC data(device tree), but building it, is harmless since driver like SPI already takes care of supporting non-dma mode in the absence of such data. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10dma: Allow TI_EDMA selectable for ARCH_KEYSTONESantosh Shilimkar
Allow the TI_EDMA to be built for ARCH_KEYSTONE which also supports the EDMA IP. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10ARM: dts: keystone: Add the SPI nodesSantosh Shilimkar
Keystone2 based SOCs supports 3 instances of SPI controllers. Add the device nodes for them. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10ARM: dts: keystone: Add i2c device nodesSantosh Shilimkar
Keystone2 based SOCs supports 3 instances of i2c controllers. Add the device nodes for them. The i2c0 child device AT24C1024 EEPROM node is also added. When different board variants are added in future, it can be moved to the supported boards from common SOC file. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10ARM: keystone: add PM domain support for clock managementSantosh Shilimkar
Add runtime PM core support to Keystone SOCs by using the pm_clk infrastructure of the PM core. Patch is based on Kevin's pm_domain work on DaVinci SOCs. Keystone SOC doesn't have depedency to enable clocks in early in the boot and hence the clock and PM domain initialisation is done at subsys_init() level. Cc: Kevin Hilman <khilman@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-10Merge tag 'renesas-soc2-for-v3.13' of ↵Kevin Hilman
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Second Round of Renesas ARM based SoC updates for v3.13 * SMP support for r8a7791 SoC * r8a7779_init_irq_extpin() for DT for r8a7779 and r8a7778 SoCs * Add HPB-DMAC to r8a7779 and r8a7778 SoCs * Add r7s72100 SoC * Make use of ARCH timer workaround on r8a7791 SoC * Add IRQC platform device support to r8a7791 SoC * Add I2C clocks and aliases for the DT mode for r8a7790 SoC * Add MAC platform device to r8a73a4 SoC * tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7791 SMP support ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DT ARM: shmobile: r7s72100 SCIF support ARM: shmobile: Initial r7s72100 SoC support ARM: shmobile: r8a7791 Arch timer workaround ARM: shmobile: r8a7791 IRQC platform device support ARM: shmobile: Introduce r8a7791_add_standard_devices() ARM: shmobile: Break out R-Car Gen2 setup code ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT mode ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT mode ARM: shmobile: r8a7779: add HPB-DMAC support ARM: shmobile: r8a7778: add HPB-DMAC support ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it ARM: shmobile: Remove #gpio-ranges-cells DT property gpio: rcar: Remove #gpio-range-cells DT property usage ARM: shmobile: armadillo: fixup ether pinctrl naming ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> format Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-10-10ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ registerR Sricharan
The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. Cc: Nishanth Menon <nm@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-09ARM: AM33xx: hwmod: Add RNG module dataLokesh Vutla
Add RNG hwmod data for AM33xx SoC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-09ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DTRajendra Nayak
Now that we have DT bindings to specify which devices should not be reset and idled during init, make hwmod extract the information (and store them in internal flags) from Device tree. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-09ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usageRajendra Nayak
For modules/IPs/hwmods which do not have -1- sys->class->reset() and -2- hardreset lines and -3- No way to do an ocp reset (no sysc control) the flag 'HWMOD_INIT_NO_RESET' is not much useful. Cleanup all such instances across various hwmod data files. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-09ARM: AM33xx: hwmod_data: add the sysc configuration for spinlockSuman Anna
Add the missing sysc configuration to the AM335 spinlock hwmod data. This ensures that smart-idle is enabled whenever the module is enabled by the driver. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-09ARM: OMAP5: hwmod data: Add spinlock dataSuman Anna
Add the hwmod data for the spinlock IP in OMAP5 SoC. This is needed to be able to enable the OMAP spinlock support for OMAP5. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-08ARM: OMAP5: hwmod data: Add USB Host and TLL modulesRoger Quadros
Add hwmod data for High Speed USB host and TLL modules CC: Paul Walmsley <paul@pwsan.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-08ARM: OMAP2+: hwmod data: Add SSI informationSebastian Reichel
This patch adds Synchronous Serial Interface (SSI) hwmod support for OMAP34xx SoCs. Signed-off-by: Sebastian Reichel <sre@debian.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-08ARM: OMAP2+: hwmod: check for module address space during initSuman Anna
The hwmod init sequence involves initializing and idling all the hwmods during bootup. If a module class has sysconfig, the init sequence utilizes the module register base for performing any sysc configuration. The module address space is being removed from hwmod database and retrieved from the <reg> property of the corresponding DT node. If a hwmod does not have its corresponding DT node defined and the memory address space is not defined in the corresponding omap_hwmod_ocp_if, then the module register target address space would be NULL and any sysc programming would result in a NULL pointer dereference and a kernel boot hang. Handle this scenario by checking for a valid module address space during the _init of each hwmod, and leaving it in the registered state if no module register address base is defined in either of the hwmod data or the DT data. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> [paul@pwsan.com: use -ENXIO rather than -ENOMEM to indicate a missing address space error; fixed checkpatch.pl problem] Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-08ARM: OMAP5: id: Remove ES1.0 supportNishanth Menon
OMAP5 ES1.0 was intended as a test chip and has major register level differences w.r.t ES2.0 revision of the chip. All register defines, dts support has been solely added for ES2.0 version of the chip. Further, all ES1.0 chips and platforms are supposed to have been removed from circulation. Hence, there is no need to further retain any resemblence of ES1.0 support in id detection code. Remove the omap_revision handling and BUG() instead to prevent folks who mistakenly try an older unsupported chip and report bogus errors. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-08ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk ↵Sricharan R
frequency The real time counter also called master counter, is a free-running counter. It produces the count used by the CPU local timer peripherals in the MPU cluster. The timer counts at a rate of 6.144 MHz. The ratio registers are missing for a sys-clk of 20MHZ which is used by DRA7 socs. So because of this, the counter was getting wrongly programmed for a sys-clk of 38.4Mhz(default). So adding the ratio registers for 20MHZ sys-clk. Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-08ARM: keystone: Enable clock driversSantosh Shilimkar
Enable common clock drivers on Keystone 2 based SOCs. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-08ARM: dts: keystone: Add clock phandle to UART nodesSantosh Shilimkar
Now since the clock tree is added, update UART dt nodes with clock data and remove the hard coded clock frequency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-08ARM: dts: keystone: Add clock tree data to devicetreeSantosh Shilimkar
Add clock tree for Keystone 2 based SOCs. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-10-08Documentation: arm/Marvell: clarify Armada SoCs that match 78xx0 patternKevin Hilman
New users of Marvell SoCs will potentially be confused by the MVEBU SoCs that match the 78xx0 pattern and thus which defconfig and mach-* directory to be looking at. Add a bit of clarification to README for this. Signed-off-by: Kevin Hilman <khilman@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: kirkwood: retain MAC address for DT ethernetSebastian Hesselbarth
Ethernet IP on Kirkwood SoCs loose their MAC address register content if clock gated. To allow modular ethernet driver setups and gated clocks also on non-DT capable bootloaders, we fixup port device nodes with no valid MAC address property. This patch copies MAC address register contents set up by bootloaders early, notably before ethernet clocks are gated. While at it, also reorder call sequence in _dt_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: kirkwood: Remove unneeded PCIe clock addingEzequiel Garcia
Since the PCIe devices is properly initialized from the DT, the clocks are now referenced in the device tree nodes, and it's not needed to have this hack to add them explicitly. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Tested-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: kirkwood: Remove unneeded MBus initializationEzequiel Garcia
Since the MBus is initialized from the DT, it's not necessary to call the legacy initialization. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: kirkwood: Add standby supportEzequiel Garcia
Implements standby support for Kirkwood SoC. When the SoC enters standby state the memory PM units are disabled, the DDR is set in self-refresh mode, and the CPU is set in WFI. At this point there's no clock gating, as that is considered each driver's task. Signed-off-by: Simon Guinot <sguinot@lacie.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-08ARM: shmobile: r8a7791 SMP supportMagnus Damm
Tie in the APMU SMP code on r8a7791. When used together with the secondary CPU device node and smp_ops in the board specific code then this will allow use of the two Cortex-A15 cores in the r8a7791 SoC. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DTKuninori Morimoto
r8a7779 INTC needs IRL pin mode settings to determine behavior of IRQ0 - IRQ3, and r8a7779_init_irq_extpin() is controlling it via irlm parameter. But this function registers renesas_intc_irqpin driver if irlm was set, and this value depends on platform. This is not good for DT. This patch splits r8a7779_init_irq_extpin() function into "mode settings" and "funtion register" parts Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DTKuninori Morimoto
r8a7778 INTC needs IRL pin mode settings to determine behavior of IRQ0 - IRQ3, and r8a7778_init_irq_extpin() is controlling it via irlm parameter. But this function registers renesas_intc_irqpin driver if irlm was set, and this value depends on platform. This is not good for DT. This patch splits r8a7778_init_irq_extpin() function into "mode settings" and "funtion register" parts. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r7s72100 SCIF supportMagnus Damm
Add SCIF serial port support to the r7s72100 SoC by adding platform devices for SCIF0 -> SCIF7 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: Initial r7s72100 SoC supportMagnus Damm
Add initial support for the r7272100 SoC including: - Single Cortex-A9 CPU Core - GIC No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7791 Arch timer workaroundMagnus Damm
Make use of the R-Car Gen2 arch timer workaround on r8a7791. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7791 IRQC platform device supportMagnus Damm
Add a platform device for the r8a7791 IRQC hardware driving IRQ pins IRQ0 to IRQ9. The Linux interrupt number is statically assigned to allow board code written in C to make use of static interrupt numbers. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: Introduce r8a7791_add_standard_devices()Magnus Damm
Introduce the function r8a7791_add_standard_devices() that follows the same style as other mach-shmobile SoC code and allows C version of board code to add on-chip devices. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: Break out R-Car Gen2 setup codeMagnus Damm
Move arch timer workaround code and boot mode pin handling from setup-r8a7790.c to setup-rcar-gen2.c. With this in place the same code can be used on other R-Car Generation 2 devices such as r8a7791. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au trivial rebase of board-lager.c for introduction of lager_add_standard_devices()] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT modeGuennadi Liakhovetski
Devices, initialised from the Device Tree and from platform code usually have different names. This patch adds a clock alias for DMAC on r8a73a4 in DT mode. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT modeGuennadi Liakhovetski
This patch adds clock definitions for the 4 I2C interfaces on r8a7790 and clock aliases, suitable for the DT mode. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7779: add HPB-DMAC supportMax Filippov
Add HPB-DMAC platform device on R8A7779 SoC along with its slave and channel configurations (only for SDHI0 so far). Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> to <mach/r8a7779.h>, removed #include <mach/dma.h> from setup-r8a7779.c, removed SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and hpb_dmae_channels[], added ASYNCMDR.ASBTMD{20|24|43} and ASYNCMDR.ASMD{20|24|43} fields/values, fixed comments to ASYNCMDR.ASBTMD2[123] and ASYNCMDR.ASMD2[123] fields/values, renamed all the bit/field/value #define's to include 'HBP_DMAE_' prefix to match the driver, moved comments after the element initializers of hpb_dmae_channels[].] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a7778: add HPB-DMAC supportMax Filippov
Add HPB-DMAC platform device on R8A7778 SoC along with its slave and channel configurations (only for SDHI0 so far). Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> to <mach/r8a7778.h>, removed #include <mach/dma.h> from setup-r8a7778.c, removed SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and hpb_dmae_channels[], moved the comments after the element initializers of hpb_dmae_channels[].] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08ARM: shmobile: r8a73a4: add a DMAC platform device and clock for itGuennadi Liakhovetski
Add a DMAC platform device and clock definitions for it on r8a73a4. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-10-08Merge tag 'renesas-fixes4-for-v3.12' into soc2-baseSimon Horman
Fourth Round of Renesas ARM based SoC fixes for v3.12 * Remove unused #gpio-ranges-cells DT property * Remove usage of deprecated #gpio-range-cells DT property from GPIO R-Car Property was deprecated in v3.11-rc2 * Correct ether pinctl naming for armadillo800eva board Regression introduced in v3.10-rc5 * Add Micrel KSZ8041 PHY fixup to lager board This resolves a problem that has been present since 3.11-rc2 * Update SDHI DT compatibility string to the <unit>-<soc> format This makes compatibility strings consistent across all renesas hardware which currently supports DT. The bindings which are being updated where intorodiced on a per-SoC basis starting in v3.8-rc7. They may have been internally consistent when originally added.
2013-10-08Merge tag 'renesas-smp-for-v3.13' into soc2-baseSimon Horman
Renesas ARM based SoC SMP updates for v3.13 * Add CPU notifier based SCU boot vector code - Use on emev2, r8a7779 and sh73a0 SoCs - Remove now unused shmobile_smp_scu_boot_secondary() * Add shared APMU SMP support code - Use to add SMP support for r8a7790 SoC * Introduce shmobile_boot_size * Expose shmobile_invalidate_start() * Introduce shmobile_smp_cpu_disable() - Use on sh73a0 SoC - Remove now unused shmobile_smp_init_cpus()
2013-10-07ARM: tegra: fix ARCH_TEGRA_114_SOC select sort orderStephen Warren
All the other select statements are alphabetically sorted. Fix the one remaining escape. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-07Merge tag 'renesas-smp-for-v3.13' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Renesas ARM based SoC SMP updates for v3.13 * Add CPU notifier based SCU boot vector code - Use on emev2, r8a7779 and sh73a0 SoCs - Remove now unused shmobile_smp_scu_boot_secondary() * Add shared APMU SMP support code - Use to add SMP support for r8a7790 SoC * Introduce shmobile_boot_size * Expose shmobile_invalidate_start() * Introduce shmobile_smp_cpu_disable() - Use on sh73a0 SoC - Remove now unused shmobile_smp_init_cpus() * tag 'renesas-smp-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Include CA7 cores in APMU table ARM: shmobile: Extend APMU code to allow single cluster only ARM: shmobile: Remove shmobile_smp_scu_boot_secondary() ARM: shmobile: Let r8a7779 rely on SCU CPU notifier ARM: shmobile: Let EMEV2 rely on SCU CPU notifier ARM: shmobile: Let sh73a0 rely on SCU CPU notifier ARM: shmobile: Add CPU notifier based SCU boot vector code ARM: shmobile: Add r8a7790 SMP support using APMU code ARM: shmobile: Shared APMU SMP support code without DT ARM: shmobile: Introduce shmobile_boot_size ARM: shmobile: Expose shmobile_invalidate_start() ARM: shmobile: Remove unused shmobile_smp_init_cpus() ARM: shmobile: Use shmobile_smp_cpu_disable() on sh73a0 ARM: shmobile: Introduce shmobile_smp_cpu_disable() ARM: shmobile: r8a7790: Constify platform data and resources ARM: shmobile: Rename to r8a7790_init_early() ARM: shmobile: Rename to r8a73a4_init_early() Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit (git 2.34.1) at 2025-09-22 13:01:06 +0000