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2017-10-12ARM: dts: gr-peach: Enable ostm0 and ostm1 timersJacopo Mondi
Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: gr-peach: Add ETHER pin groupJacopo Mondi
Add pin configuration subnode for ETHER pin group. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Enable DMA for HSUSBBiju Das
This patch adds DMA properties to the HSUSB node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Add USB-DMAC device nodesBiju Das
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg20d-q7: Enable HS-USBBiju Das
Enable HS-USB device for the iWave G20D-Q7 carrier board based on RZ/G1M. Also disable the host mode support on usb otg port by default to avoid pin conflicts. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7743: Add HS-USB device nodeBiju Das
Define the R8A7743 generic part of the HS-USB device node. It is up to the board file to enable the device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg22d-sodimm: Enable USB PHYBiju Das
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: iwg22d-sodimm: Enable internal PCIBiju Das
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Link PCI USB devices to USB PHYBiju Das
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Add USB PHY DT supportBiju Das
Define the r8a7745 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7745: Add internal PCI bridge nodesBiju Das
Add device nodes for the r8a7745 internal PCI bridge devices. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-12ARM: dts: r8a7790: add cpu capacity-dmips-mhz informationDietmar Eggemann
The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-09ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DBFabrizio Castro
This patch adds a .dtsi that describes the camera daughter board and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's RZ/G1M/G1N Qseven carrier board, and the camera daughter board. The camera daughter board .dtsi adds support for ttySC[14]. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-09ARM: dts: iwg20d-q7: Rework DT architectureFabrizio Castro
Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides: * iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more. * r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties. The final DT architecture to describe the board is now: r8a7743-iwg20d-q7.dts # Carrier Board + SoM ├── r8a7743-iwg20m.dtsi # SoM │   └── r8a7743.dtsi # SoC └── iwg20d-q7-common.dtsi # Carrier Board and maximizes the reuse of the definitions for the carrier board and for the SoM. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-06ARM: dts: r8a7794: Use generic node name for VSP1 nodesGeert Uytterhoeven
Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-06ARM: dts: r8a7792: Use generic node name for VSP1 nodesGeert Uytterhoeven
Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-06ARM: dts: r8a7791: Use generic node name for VSP1 nodesGeert Uytterhoeven
Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-06ARM: dts: r8a7790: Use generic node name for VSP1 nodesGeert Uytterhoeven
Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-05ARM: dts: gr-peach: Enable MTU2 timer pulse unitJacopo Mondi
MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-05ARM: dts: gr-peach: Fix 'leds' node name indentJacopo Mondi
Fix 'leds' node name indent as it was wrongly aligned. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-28ARM: dts: r8a7743: Add MSIOF[012] supportFabrizio Castro
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-28ARM: dts: r8a7745: Add MSIOF[012] supportFabrizio Castro
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-25ARM: dts: iwg22d: Enable SDHI0 controllerFabrizio Castro
Enable the SDHI0 controller on iWave RZ/G1E carrier board. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-21ARM: dts: iwg22m: Add SPI NOR supportFabrizio Castro
Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-21ARM: dts: r8a7745: Add QSPI supportFabrizio Castro
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-21ARM: dts: iwg20m: Add SPI NOR supportFabrizio Castro
Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-21ARM: dts: r8a7743: Add QSPI supportFabrizio Castro
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-21ARM: dts: iwg22m: Enable SDHI1 controllerFabrizio Castro
Enable the SDHI1 controller on iWave RZ/G1E SoM. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7745: Add SDHI controllersFabrizio Castro
Add the SDHI controllers to the r8a7745 device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7794: Add reset control propertiesGeert Uytterhoeven
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7793: Add reset control propertiesGeert Uytterhoeven
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7792: Add reset control propertiesGeert Uytterhoeven
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, but audio is not yet enabled in r8a7792.dtsi, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7791: Add reset control propertiesGeert Uytterhoeven
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7790: Add reset control propertiesGeert Uytterhoeven
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7743: Add IIC cores to dtsiBiju Das
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: alt: use correct logic for SD WP pinsWolfram Sang
The WP pins are ACTIVE_HIGH, fix it in the DTS. Fixes: 2b41091b896b ("ARM: dts: alt: add SDHI0 and 1 support") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg20d-q7: Enable USB PHYBiju Das
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg20d-q7: Enable internal PCIBiju Das
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7743: Link PCI USB devices to USB PHYBiju Das
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7743: Add USB PHY DT supportBiju Das
Define the r8a7743 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7743: Add internal PCI bridge nodesBiju Das
Add device nodes for the r8a7743 internal PCI bridge devices. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg22d-sodimm: Add Ethernet AVB supportBiju Das
Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node. On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg22d-sodimm: Add pinctl support for scif4Biju Das
Adding pinctrl support for scif4 interface. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg20d-q7: Add RTC supportBiju Das
Define the iWave RainboW-G20D-Qseven board dependent part of the RTC device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: iwg20d-q7: Add chosen nodeBiju Das
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7745: Add Ethernet AVB supportBiju Das
Add Ethernet AVB support for r8a7745 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Add user led device nodesJacopo Mondi
Add device nodes for user leds on gr-peach board. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Add SCIF2 pin groupJacopo Mondi
Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: gr-peach: Remove empty lineJacopo Mondi
Remove an empty line in gr-peach device tree source file. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7791: Stop grouping clocks under a "clocks" subnodeGeert Uytterhoeven
The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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