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2021-02-04Merge tag 'clk-imx-5.12' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clk driver updates from Shawn Guo: - Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk reparenting - A couple of W=1 build warning fixes from Lee Jones - A series from Liu Ying that adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems - A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ, and clkout1/2 support for i.MX8MM/MN * tag 'clk-imx-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
2021-02-04Merge tag 'sunxi-clk-for-5.12' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Maxime Ripard: "Our usual PR for the Allwinner SoCs, this time adding support for the Allwinner H616 SoC, and a few H6 fixes." * tag 'sunxi-clk-for-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add support for the Allwinner H616 CCU clk: sunxi-ng: Add support for the Allwinner H616 R-CCU dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: h6: Fix clock divider range on some clocks clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers clk: sunxi-ng: h6: Fix CEC clock clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
2021-02-04Merge tag 'renesas-clk-for-v5.12-tag2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add I2c and Ethernet (RAVB) clocks on R-Car V3U - Fix a kerneldoc issue - Add timer (TMU) clocks on most R-Car Gen3 SoCs - Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial (HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA (SYS-DMAC) clocks on R-Car V3U - Add support for the USB 2.0 clock selector on RZ/G2 SoCs - Minor fixes and improvements * tag 'renesas-clk-for-v5.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (21 commits) clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation clk: renesas: r8a779a0: Add RAVB clocks clk: renesas: r8a779a0: Add I2C clocks dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H clk: renesas: r8a779a0: Add SYS-DMAC clocks clk: renesas: r8a779a0: Add SDHI support clk: renesas: rcar-gen3: Factor out CPG library clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock clk: renesas: r8a779a0: Add MSIOF clocks clk: renesas: r8a779a0: Add PFC/GPIO clocks clk: renesas: r8a779a0: Fix parent of CBFUSA clock clk: renesas: r8a779a0: Remove non-existent S2 clock clk: renesas: r8a779a0: Add HSCIF support clk: renesas: r8a779a0: Add RWDT clocks clk: renesas: r8a779a0: Add VSPX clock support clk: renesas: r8a779a0: Add VSPD clock support clk: renesas: r8a779a0: Add FCPVD clock support clk: renesas: r8a77995: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks ...
2021-01-30clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible headerLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/imx/clk-imx6sl.c:156:6: warning: no previous prototype for ‘imx6sl_set_wait_clk’ [-Wmissing-prototypes] Cc: Russell King <linux@armlinux.org.uk> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30clk: imx8mn: add clkout1/2 supportLucas Stach
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30clk: imx8mm: add clkout1/2 supportLucas Stach
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30clk: imx8mq: add PLL monitor outputLucas Stach
The PLL monitor is mentioned as a debug feature in the reference manual, but there are some boards that use this clock output as a reference clock for board level components. Add support for those clocks in the clock driver, so this clock output can be used properly. Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the description in the reference manual. The order in this patch has been empirically validated. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-29clk: imx: clk-imx31: Remove unused static const table 'uart_clks'Lee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/imx/clk-imx31.c:54:28: warning: ‘uart_clks’ defined but not used [-Wunused-const-variable=] Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-29clk: imx6q: demote warning about pre-boot ldb_di_clk reparentingAhmad Fatoum
Since 5d283b083800 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK"), the clock driver warns if ldb_di\d_sel is changed from reset value on system boot. This warning is printed even if the bootloader (or a previous kernel that did kexec) followed the correct procedure for glitch-free reparenting. As such systems are doing everything correctly, a warning is too harsh. Demote to a notice, so users are still alerted, but without cluttering a loglevel=5 boot. While at it, add the words "possible glitch" into the log message, to make it more user-friendly. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 CCUAndre Przywara
While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 R-CCUAndre Przywara
The clocks itself are identical to the H6 R-CCU, it's just that the H616 has not all of them implemented (or connected). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-3-andre.przywara@arm.com
2021-01-28dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616Andre Przywara
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-2-andre.przywara@arm.com
2021-01-28clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentationLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/renesas/renesas-cpg-mssr.c:168: warning: Function parameter or member 'smstpcr_saved' not described in 'cpg_mssr_priv' Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-12-lee.jones@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-26clk: rockchip: Demote non-conformant kernel-doc header in half-dividerLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'name' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'parent_names' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'num_parents' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'base' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'muxdiv_offset' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_shift' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_width' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_flags' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_shift' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_width' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_flags' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_offset' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_shift' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_flags' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'flags' not described in 'rockchip_clk_register_halfdiv' drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'lock' not described in 'rockchip_clk_register_halfdiv' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-5-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26clk: rockchip: Demote kernel-doc abuses to standard comment blocks in pllsLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk-pll.c:104: warning: Function parameter or member 'i' not described in 'RK3036_PLLCON' drivers/clk/rockchip/clk-pll.c:365: warning: Function parameter or member 'nr' not described in 'RK3066_PLL_RESET_DELAY' drivers/clk/rockchip/clk-pll.c:584: warning: Function parameter or member 'i' not described in 'RK3399_PLLCON' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Xing Zheng <zhengxing@rock-chips.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-4-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26clk: rockchip: Remove unused/undocumented struct members from clk-cpuLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux' not described in 'rockchip_cpuclk' drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux_ops' not described in 'rockchip_cpuclk' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-3-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26clk: rockchip: Demote non-conformant kernel-doc headers in main clock codeLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'name' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'parent_names' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'num_parents' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'base' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'muxdiv_offset' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_shift' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_width' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_flags' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_offset' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_shift' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_width' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_flags' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_table' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_offset' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_shift' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_flags' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'flags' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'lock' not described in 'rockchip_clk_register_branch' drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'hw' not described in 'rockchip_fractional_approximation' drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'rate' not described in 'rockchip_fractional_approximation' drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'parent_rate' not described in 'rockchip_fractional_approximation' drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'm' not described in 'rockchip_fractional_approximation' drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'n' not described in 'rockchip_fractional_approximation' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Xing Zheng <zhengxing@rock-chips.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-2-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-25clk: renesas: r8a779a0: Add RAVB clocksWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-25clk: renesas: r8a779a0: Add I2C clocksWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210121095420.5023-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-20clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara
While comparing clocks between the H6 and H616, some of the M factor ranges were found to be wrong: the manual says they are only covering two bits [1:0], but our code had "5" in the number-of-bits field. By writing 0xff into that register in U-Boot and via FEL, it could be confirmed that bits [4:2] are indeed masked off, so the manual is right. Change to number of bits in the affected clock's description. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@arm.com
2021-01-20clk: sunxi: clk-mod0: Demote non-conformant kernel-doc headerLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/sunxi/clk-mod0.c:24: warning: Function parameter or member 'req' not described in 'sun4i_a10_get_mod0_factors' Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@siol.net> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210120093040.1719407-19-lee.jones@linaro.org
2021-01-20clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuseLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/sunxi/clk-a10-ve.c:27: warning: cannot understand function prototype: 'struct ve_reset_data ' Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@siol.net> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210120093040.1719407-18-lee.jones@linaro.org
2021-01-20clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headersLee Jones
Fixes the following W=1 kernel build warning(s): drivers/clk/sunxi/clk-sunxi.c:34: warning: Function parameter or member 'req' not described in 'sun4i_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:81: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:158: warning: Function parameter or member 'req' not described in 'sun8i_a23_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:202: warning: Function parameter or member 'req' not described in 'sun4i_get_pll5_factors' drivers/clk/sunxi/clk-sunxi.c:229: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll6_factors' drivers/clk/sunxi/clk-sunxi.c:250: warning: Function parameter or member 'req' not described in 'sun5i_a13_get_ahb_factors' drivers/clk/sunxi/clk-sunxi.c:289: warning: Function parameter or member 'req' not described in 'sun6i_get_ahb1_factors' drivers/clk/sunxi/clk-sunxi.c:328: warning: Function parameter or member 'req' not described in 'sun6i_ahb1_recalc' drivers/clk/sunxi/clk-sunxi.c:346: warning: Function parameter or member 'req' not described in 'sun4i_get_apb1_factors' drivers/clk/sunxi/clk-sunxi.c:385: warning: Function parameter or member 'req' not described in 'sun7i_a20_get_out_factors' drivers/clk/sunxi/clk-sunxi.c:415: warning: cannot understand function prototype: 'const struct clk_factors_config sun4i_pll1_config = ' drivers/clk/sunxi/clk-sunxi.c:724: warning: cannot understand function prototype: 'struct div_data ' drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'node' not described in 'sunxi_divs_clk_setup' drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'data' not described in 'sunxi_divs_clk_setup' Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@siol.net> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210120093040.1719407-15-lee.jones@linaro.org
2021-01-12linux/clk.h: use correct kernel-doc notation for 2 functionsRandy Dunlap
Fix kernel-doc notation for 2 functions so that the generated html is correct. Currently it skips all text between the ':' and the '-', so "[un]register a clock rate" is missing. Fixes: 86bcfa2e87c4 ("clk: add pr_debug & kerneldoc around clk notifiers") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@armlinux.org.uk> Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20210107023304.24442-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/HAdam Ford
The datasheet for the RZ/G2 Series show the bit for choosing between a crystal oscillator and an external oscillator is present. Add the bindings for r8a774a1 (RZ/G2M), r8a774b1 (RZ/G2N), and r8a774e1 (RZ/G2H) Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201228202221.2327468-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: r8a779a0: Add SYS-DMAC clocksGeert Uytterhoeven
Add the module clocks used by the Direct Memory Access Controller for System (SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210107180109.1946475-1-geert+renesas@glider.be
2021-01-12clk: renesas: r8a779a0: Add SDHI supportWolfram Sang
We use the shiny new CPG library for that. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: rcar-gen3: Factor out CPG libraryWolfram Sang
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock handling and hook it to the generic Gen3 CPG driver so we have an equal state. V3U will make use of it in the next patch then. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clockWolfram Sang
We want to reuse SD clock handling for other SoCs and, thus, need to generalize it. So, don't access cpg_quirks in that realm. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12clk: renesas: r8a779a0: Add MSIOF clocksGeert Uytterhoeven
Add the module clocks used by the Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201117090329.2128904-3-geert+renesas@glider.be
2021-01-12clk: renesas: r8a779a0: Add PFC/GPIO clocksGeert Uytterhoeven
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks, and their parent clock CP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-4-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Fix parent of CBFUSA clockGeert Uytterhoeven
According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock is EXTAL. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-3-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Remove non-existent S2 clockGeert Uytterhoeven
The S2 internal core clock does not exist on R-Car V3U. Remove it. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201019120614.22149-2-geert+renesas@glider.be
2021-01-07clk: renesas: r8a779a0: Add HSCIF supportWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201228112715.14947-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-06clk: sunxi-ng: h6: Fix CEC clockAndre Przywara
The CEC clock on the H6 SoC is a bit special, since it uses a fixed pre-dividier for one source clock (the PLL), but conveys the other clock (32K OSC) directly. We are using a fixed predivider array for that, but fail to use the right flag to actually activate that. Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Reported-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210106143246.11255-1-andre.przywara@arm.com
2021-01-06clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and resetSamuel Holland
While no information about the H6 RSB controller is included in the datasheet or manual, the vendor BSP and power management blob both reference the RSB clock parent and register address. These values were verified by experimentation. Since this clock/reset are added late, the specifier is added at the end to maintain the existing DT binding. The code is kept in register order. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-05clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystemsLiu Ying
This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()Liu Ying
This patch corrects display clocks for i.MX8qxp DC0 subsystem by calling imx_clk_scu2() to register them, instead of calling imx_clk_scu(). The reason is that the clocks can source from various parents. The clock source selection is controlled by Distributed Slave System Controller(DSC). According to the DSC spec, the below table describes the generic source selections for clocks with the same type in various subsystems. And, the display controller subsystem spec says the display clocks can source from PLL1, PLL2 or bypass clock, thus we may specify the correct parents for imx_clk_scu2(). The bypass clock's parent is determined by the SCU firmware. Currently, the parent is 'pixel_link_clk_in' from HW point of view. To be more specific, the parent is dummy for i.MX8qxp DC0, while HDMI TX PHY PLL for i.MX8qm DC0. In practice, the display clocks source from the bypass clock only when driving i.MX8qm HDMI TX. So, for the both display clocks, we simply specify 'dc0_bypass0_clk' bypass clock as a valid parent. ----------------------------------------- | src_sel[28:26] | | ----------------------------------------- | 0x0 | xtal24M | | 0x1 | PLL0 | | 0x2 | PLL1 | | 0x3 | PLL2 | | 0x4 | bypass reference clock | | 0x5 to 0x7 | reserved | ----------------------------------------- Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocksLiu Ying
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocksLiu Ying
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-04dt-bindings: clock: meson8b: remove non-existing clock macrosMartin Blumenstingl
CLKID_UNUSED and CLKID_XTAL aren't valid clocks. Remove them since there are no consumers of this anymore. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-3-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl
The XTAL clock is provided via .dts since Linux 5.6. Remove compatibility code for .dtbs which are older than that. The switch to the HHI syscon has been done with Linux 5.1. Also remove any code needed to support .dtbs that have not switched to the HHI syscon yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-2-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl
Popagate the error code from meson_clk_pll_set_rate() when the PLL does not lock with the new settings. Fixes: 722825dcd54b2e ("clk: meson: migrate plls clocks to clk_regmap") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-4-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl
The error codes returned by meson_clk_get_pll_settings() are all negative. Make "ret" a signed integer in meson_clk_pll_set_rate() to make it match with the clk_ops.set_rate API as well as the data type returned by meson_clk_get_pll_settings(). Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-3-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate. Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try to switch from the new rate to the same rate again. Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com
2020-12-28clk: renesas: r8a779a0: Add RWDT clocksWolfram Sang
And introduce critical clocks, too, because RWDT is one. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201218173731.12839-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add VSPX clock supportKieran Bingham
Add clocks for the VSPX. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-4-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add VSPD clock supportKieran Bingham
Add clocks for the VSPD modules on the V3U. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-3-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a779a0: Add FCPVD clock supportKieran Bingham
Add clocks for the FCP for VSP-D module. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20201216151931.851547-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28clk: renesas: r8a77995: Add TMU clocksNiklas Söderlund
This patch adds TMU{0,1,2,3,4} clocks. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20201209195343.803120-6-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-09-29 23:59:19 +0000