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2021-02-16Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and ↵Stephen Boyd
'clk-rohm' into clk-next - Support crystal load capacitance for Versaclock VC5 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot * clk-vc5: clk: vc5: Add support for optional load capacitance dt-bindings: clk: versaclock5: Add optional load capacitance property * clk-silabs: clk: si570: Skip NVM to RAM recall operation if an optional property is set dt-bindings: clock: si570: Add 'silabs,skip-recall' property * clk-aspeed: clk: aspeed: Fix APLL calculate formula from ast2600-A2 * clk-qoriq: clk: qoriq: use macros to generate pll_mask * clk-rohm: clk: BD718x7: Do not depend on parent driver data
2021-02-16Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into ↵Stephen Boyd
clk-next * clk-mediatek: clk: mediatek: mux: Update parent at enable time clk: mediatek: mux: Drop unused clock ops clk: mediatek: Select all the MT8183 clocks by default * clk-imx: dt-bindings: clock: imx: Switch to my personal address MAINTAINERS: Add section for NXP i.MX clock drivers clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks * clk-amlogic: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL * clk-at91: clk: at91: Fix the declaration of the clocks
2021-02-16Merge branch 'clk-unused' into clk-nextStephen Boyd
- Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver * clk-unused: clk: remove u300 driver clk: remove sirf prima2/atlas drivers clk: remove zte zx driver clk: remove tango4 driver clk: Drop unused efm32gg driver
2021-02-16Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and ↵Stephen Boyd
'clk-xilinx' into clk-next - Convert Xilinx VCU clk driver to a proper clk provider driver - Expose Xilinx ZynqMP clk driver to more platforms * clk-doc: linux/clk.h: use correct kernel-doc notation for 2 functions * clk-renesas: (21 commits) clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation clk: renesas: r8a779a0: Add RAVB clocks clk: renesas: r8a779a0: Add I2C clocks dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H clk: renesas: r8a779a0: Add SYS-DMAC clocks clk: renesas: r8a779a0: Add SDHI support clk: renesas: rcar-gen3: Factor out CPG library clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock clk: renesas: r8a779a0: Add MSIOF clocks clk: renesas: r8a779a0: Add PFC/GPIO clocks clk: renesas: r8a779a0: Fix parent of CBFUSA clock clk: renesas: r8a779a0: Remove non-existent S2 clock clk: renesas: r8a779a0: Add HSCIF support clk: renesas: r8a779a0: Add RWDT clocks clk: renesas: r8a779a0: Add VSPX clock support clk: renesas: r8a779a0: Add VSPD clock support clk: renesas: r8a779a0: Add FCPVD clock support clk: renesas: r8a77995: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks ... * clk-allwinner: clk: sunxi-ng: Add support for the Allwinner H616 CCU clk: sunxi-ng: Add support for the Allwinner H616 R-CCU dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: h6: Fix clock divider range on some clocks clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers clk: sunxi-ng: h6: Fix CEC clock clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset * clk-rockchip: clk: rockchip: fix DPHY gate locations on rk3368 clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: Demote non-conformant kernel-doc header in half-divider clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls clk: rockchip: Remove unused/undocumented struct members from clk-cpu clk: rockchip: Demote non-conformant kernel-doc headers in main clock code * clk-xilinx: clk: xilinx: move xlnx_vcu clock driver from soc soc: xilinx: vcu: fix alignment to open parenthesis soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: drop coreclk from struct xlnx_vcu clk: divider: fix initialization with parent_hw ARM: dts: vcu: define indexes for output clocks clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support clk: clk-axiclkgen: add ZynqMP PFD and VCO limits clk: axi-clkgen: replace ARCH dependencies with driver deps
2021-02-14clk: qoriq: use macros to generate pll_maskWasim Khan
Use macros to generate pll_mask to make code more readable. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Link: https://lore.kernel.org/r/20210125142513.3919014-1-wasim.khan@oss.nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: BD718x7: Do not depend on parent driver dataMatti Vaittinen
The bd718x7 only needs a regmap from parent device. This can be obtained by call to dev_get_regmap. Do not require parent to populate the driver data for this. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Link: https://lore.kernel.org/r/20210105123028.GA3409663@localhost.localdomain Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen
Starting from A2, the A-PLL calculation has changed. Use the existing formula for A0/A1 and the new formula for A2 onwards. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: si570: Skip NVM to RAM recall operation if an optional property is setSaeed Nowshadi
Recalling NVM data into RAM during probe() initiates a re-calibration of the clock. If the clock is already in-use, the recall operation can cause a glitch on the frequency out. At power on, the factory data are loaded from NVM into RAM by default. If the clock frequency has been changed since power on, the recall operation can be used to re-initialize the clock to factory setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Link: https://lore.kernel.org/r/1612496104-3437-3-git-send-email-saeed.nowshadi@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11dt-bindings: clock: si570: Add 'silabs,skip-recall' propertySaeed Nowshadi
Add an optional property so the driver can skip calling the NVM->RAM recall operation during probe(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Link: https://lore.kernel.org/r/1612496104-3437-2-git-send-email-saeed.nowshadi@xilinx.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: vc5: Add support for optional load capacitanceAdam Ford
There are two registers which can set the load capacitance for XTAL1 and XTAL2. These are optional registers when using an external crystal. Parse the device tree and set the corresponding registers accordingly. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20210207185140.3653350-2-aford173@gmail.com Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11dt-bindings: clk: versaclock5: Add optional load capacitance propertyAdam Ford
There are two registers which can set the load capacitance for XTAL1 and XTAL2. These are optional registers when using an external crystal. Since XTAL1 and XTAL2 will set to the same value, update the binding to support a single property called xtal-load-femtofarads. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20210207185140.3653350-1-aford173@gmail.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09clk: at91: Fix the declaration of the clocksTudor Ambarus
These are all "early clocks" that require initialization just at of_clk_init() time. Use CLK_OF_DECLARE() to declare them. This also fixes a problem that was spotted when fw_devlink was set to 'on' by default: the boards failed to boot. The reason is that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes the consumers of the clock to be postponed by fw_devlink until the second initialization routine of the clock has been completed. One of the consumers of the clock is the timer, which is used as a clocksource, and needs the clock initialized early. Postponing the timers caused the fail at boot. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com Acked-by: Saravana Kannan <saravanak@google.com> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09Merge tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson ↵Stephen Boyd
into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - pll driver fixup - meson8b clock controller dt support clean up - remove mipi clk from the axg clock controller * tag 'clk-meson-v5.12-1-fixed' of https://github.com/BayLibre/clk-meson: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY region and is not related to clock one and can be removed from it. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2021-02-09clk: meson-axg: remove CLKID_MIPI_ENABLERemi Pommarel
CLKID_MIPI_ENABLE is not handled by the AXG clock driver anymore but by the MIPI/PCIe PHY driver. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2021-02-09dt-bindings: clock: imx: Switch to my personal addressFabio Estevam
My nxp account will expire soon, so switch to my personal e-mail address. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210130144558.133534-1-festevam@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09clk: mediatek: mux: Update parent at enable timeLaurent Pinchart
The mux clocks don't always correctly take the new parent into account when the parent is updated while the clock is disabled. Set the update bit when enabling the clock to force an update of the mux. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09clk: mediatek: mux: Drop unused clock opsLaurent Pinchart
Three out of the four defined clock ops are unused. Drop them. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210125170819.26130-2-laurent.pinchart@ideasonboard.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: mediatek: Select all the MT8183 clocks by defaultEnric Balletbo i Serra
If MT8183 SoC support is enabled, almost all machines will use topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks, so it feels wrong to require each one to select that symbols manually. Instead, enable it whenever COMMON_CLK_MT8183_* is disabled as a simplification. This would add few KB in the kernel image size but will make the life a bit easier to the users, anyway you'll need to probably enable all of them if you want to have proper support for that SoC. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210203105423.682960-1-enric.balletbo@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: remove u300 driverArnd Bergmann
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-5-arnd@kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: remove sirf prima2/atlas driversArnd Bergmann
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org Acked-by: Barry Song <baohua@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: remove zte zx driverArnd Bergmann
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: remove tango4 driverArnd Bergmann
The tango platform is getting removed, so the driver is no longer needed. Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Cc: Mans Rullgard <mans@mansr.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-2-arnd@kernel.org Acked-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: xilinx: move xlnx_vcu clock driver from socMichael Tretter
The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: fix alignment to open parenthesisMichael Tretter
Fixes the following checkpatch check: CHECK: Alignment should match open parenthesis #610: FILE: drivers/soc/xilinx/xlnx_vcu.c:610: + xvcu->vcu_slcr_ba = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-15-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: fix repeated word the in commentMichael Tretter
Fixes the following checkpatch warning: WARNING: Possible repeated word: 'the' #703: FILE: drivers/soc/xilinx/xlnx_vcu.c:703: + /* Add the the Gasket isolation and put the VCU in reset. */ Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-14-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: use bitfields for register definitionMichael Tretter
This makes the register accesses more readable and is closer to what is usually used in the kernel. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-13-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: remove calculation of PLL configurationMichael Tretter
As the consumers are now responsible for setting the clock rate via clock framework, the clock rate is now calculated using round_rate and the driver does not need to calculate the clock rate beforehand. Remove the code that calculates the PLL configuration. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-12-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: make the PLL configurableMichael Tretter
Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-11-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: make pll post divider explicitMichael Tretter
According to the downstream driver documentation due to timing constraints the output divider of the PLL has to be set to 1/2. Add a helper function for that check instead of burying the code in one large setup function. The bit is undocumented and marked as reserved in the register reference. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-10-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: implement clock provider for output clocksMichael Tretter
The VCU System-Level Control uses an internal PLL to drive the core and MCU clock for the allegro encoder and decoder based on an external PL clock. In order be able to ensure that the clocks are enabled and to get their rate from other drivers, the module must implement a clock provider and register the clocks at the common clock framework. Other drivers are then able to access the clock via devicetree bindings. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-9-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: register PLL as fixed rate clockMichael Tretter
Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is pre-calculated when probing the driver. To still make the clock framework aware of the PLL and to allow to configure other clocks based on the PLL rate, register the PLL as a fixed rate clock. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-8-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: implement PLL disableMichael Tretter
The disabling of the PLL is not fully implemented, because according to the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to be set to bring the PLL into reset. Set the bits to disable the PLL. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-7-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: add helpers for configuring PLLMichael Tretter
The xvcu_set_vcu_pll_info function sets the rate of the PLL and enables it, which makes it difficult to cleanly convert the driver to the common clock framework. Split the function and add separate functions for setting the rate, enabling the clock and disabling the clock. Also move the enable of the reference clock from probe to the helper that enables the PLL. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-6-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: add helper to wait for PLL lockedMichael Tretter
Extract a helper function to wait until the PLL is locked. Also, disabling the bypass was buried in the exit path on the wait loop. Separate the different steps and add a helper function to make the code more readable. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-5-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08soc: xilinx: vcu: drop coreclk from struct xlnx_vcuMichael Tretter
The coreclk field is newer read after being written to xlnx_vcu. Remove the coreclk field from the xlnx_vcu and use a function local variable instead. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-4-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: divider: fix initialization with parent_hwMichael Tretter
If a driver registers a divider clock with a parent_hw instead of the parent_name, the parent_hw is ignored and the clock does not have a parent. Fix this by initializing the parents the same way they are initialized for clock gates. Fixes: ff258817137a ("clk: divider: Add support for specifying parents via DT/pointers") Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-3-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08ARM: dts: vcu: define indexes for output clocksMichael Tretter
The VCU System-Level Control has 4 output clocks. Define indexes for these clocks to allow to reference them in the device tree. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-2-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: axi-clkgen: use devm_platform_ioremap_resource() short-handAlexandru Ardelean
No major functional change. Noticed while checking the driver code that this could be used. Saves two lines. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-5-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP supportAlexandru Ardelean
The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the driver needs to use different PFD & VCO limits. For ZynqMP, these needs to be selected by using the 'adi,zynqmp-axi-clkgen-2.00.a' string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-4-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: clk-axiclkgen: add ZynqMP PFD and VCO limitsAlexandru Ardelean
For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to support these, this change adds a compatible string (i.e. 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these limits and apply them. Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Mathias Tausen <mta@gomspace.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-3-alexandru.ardelean@analog.com Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: axi-clkgen: replace ARCH dependencies with driver depsAlexandru Ardelean
The intent is to be able to run this driver to access the IP core in setups where FPGA board is also connected via a PCIe bus. In such cases the number of combinations explodes, where the host system can be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe. Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe. To accommodate for these cases, this change removes the limitation for this driver to be compilable only on Zynq/Microblaze architectures. And adds dependencies on the mechanisms required by the driver to work (OF and HAS_IOMEM). Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-2-alexandru.ardelean@analog.com Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08Merge tag 'v5.12-rockchip-clk1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Kerneldoc fixes - some new rk3368 clock ids related to camera input * tag 'v5.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix DPHY gate locations on rk3368 clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: Demote non-conformant kernel-doc header in half-divider clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls clk: rockchip: Remove unused/undocumented struct members from clk-cpu clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
2021-02-08clk: Drop unused efm32gg driverUwe Kleine-König
Support for this machine was just removed, so drop the now unused clk driver, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210114151630.128830-3-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08MAINTAINERS: Add section for NXP i.MX clock driversAbel Vesa
Add a section for NXP i.MX clock drivers and list myself as the maintainer. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1610542388-12078-1-git-send-email-abel.vesa@nxp.com Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-06clk: rockchip: fix DPHY gate locations on rk3368Heiko Stuebner
Fix the register and bits of the DPHY gate locations. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-5-heiko@sntech.de
2021-02-06clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner
Export the vip-out clock via the newly added clock-id. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-4-heiko@sntech.de
2021-02-06clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner
Needed to provide clocks for cameras. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-3-heiko@sntech.de
2021-02-06clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner
Export the clocks via the newly added clock-ids. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-2-heiko@sntech.de
2021-02-06clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner
Needed by the mipi dphys. The naming follows the clock names in the manual. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-1-heiko@sntech.de
generated by cgit (git 2.34.1) at 2025-09-29 16:17:22 +0000