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2020-12-07x86/platform/uv: Add deprecated messages to /proc info leavesMike Travis
Add "deprecated" message to any access to old /proc/sgi_uv/* leaves. [ bp: Do not have a trailing function opening brace and the arguments continuing on the next line and align them on the opening brace. ] Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Link: https://lkml.kernel.org/r/20201128034227.120869-5-mike.travis@hpe.com
2020-12-07x86/platform/uv: Add sysfs hubless leavesMike Travis
Add uv_sysfs hubless leaves for UV hubless systems. Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Link: https://lkml.kernel.org/r/20201128034227.120869-4-mike.travis@hpe.com
2020-12-07x86/platform/uv: Add sysfs leaves to replace those in procfsMike Travis
Add uv_sysfs leaves to display the info. Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Link: https://lkml.kernel.org/r/20201128034227.120869-3-mike.travis@hpe.com
2020-12-07x86/platform/uv: Add kernel interfaces for obtaining system infoMike Travis
Add kernel interfaces used to obtain info for the uv_sysfs driver to display. Signed-off-by: Mike Travis <mike.travis@hpe.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Steve Wahl <steve.wahl@hpe.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Link: https://lkml.kernel.org/r/20201128034227.120869-2-mike.travis@hpe.com
2020-12-07media: ccs: Add support for obtaining C-PHY configuration from firmwareSakari Ailus
Try parsing the firmware also as C-PHY. Do this only after D-PHY as older firmware may not explicitly specify bus-type in which case D-PHY is the default. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Print pixel ratesSakari Ailus
Print pixel rates on CSI-2 bus as well as in pixel array as the variation allowed in PLL capabilities makes this non-trivial to figure out otherwise. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Print written register valuesSakari Ailus
This helps debugging register writes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Add support for DDR OP SYS and OP PIX clocksSakari Ailus
Support dual data rate operational system and pixel clocks by conveying the flags to the PLL calculator and updating how the link rate is calculated. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for DDR OP system and pixel clocksSakari Ailus
Add support for dual data rate operational system and pixel clocks. This is implemented using two PLL flags. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07io_uring: fix mis-seting personality's credsPavel Begunkov
After io_identity_cow() copies an work.identity it wants to copy creds to the new just allocated id, not the old one. Otherwise it's akin to req->work.identity->creds = req->work.identity->creds. Signed-off-by: Pavel Begunkov <asml.silence@gmail.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2020-12-07docs: nios2: add missing ReST fileMauro Carvalho Chehab
changeset ed13a92d0fde ("docs: archis: add a per-architecture features list") besides having a typo on its title, it was missing the feature file. Add it. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: ed13a92d0fde ("docs: archis: add a per-architecture features list") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/e51c4692c4420d28bca35f553a9a3f3d78404d99.1607331056.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2020-12-07media: ccs: Dual PLL supportSakari Ailus
Add support for sensors that either require dual PLL or support single or dual PLL but use dual PLL as default. Use sensor default configuration for sensors that support both modes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus
Add support for sensors that have separate VT and OP domain PLLs. This support is trivial in the sense that it aims for the same VT pixel rate than that on the CSI-2 bus. The vast majority of sensors is better supported by higher frequencies in VT domain in binned and possibly scaled configurations. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus
Separate VT divisor limit calculation from the rest of the VT PLL branch calculation. This way it can be used for dual PLL support as well. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus
The PLL calculator only searched even total divisor values apart from one, but this is wrong: the total divisor is odd in cases where system divisor is one. Fix this by including odd total PLL values where system divisor is one to the search. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus
Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after all. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus
Refactor bounds checks so that the caller can decide what to check. This allows doing the checks early, when the values are available. This also adds front OP PLL configuration and limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus
Print information on PLL tree configuration based on the flags. This also adds support for printing dual PLL trees, and better separates between OP and VT PLL trees. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus
Better separate OP PLL branch calculation from VT branch calculation. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus
Some sensors support derating (VT domain speed faster than OP) or overrating (VT domain speed slower than OP). While this was supported for the driver, the hardware support for the feature was never verified. Do that now, and for those devices without that support, VT and OP speeds have to match. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus
Split off the VT sub clock tree calculation from the rest, into its own function. Also call the op_pll_fr argument pll_fr, since soon these may not be OP tree values. This paves way for additional features in the future such as dual PLL support. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus
Add C-PHY support for the CCS PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus
Add sanity checks for fields that could cause division by zero. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus
Flexible OP PLL pixel clock divider allows a higher OP pixel clock than what the bus can transfer. This generally makes it easier to select pixel clock dividers. This changes how the pixel rate on the bus and minimum VT divisor are calculated, as the pixel rate is no longer directly determined by the OP pixel clock and the number of the lanes. Also add a sanity check for sensors that do not support flexible OP PLL pixel clock divider. This could have caused the PLL calculator to come up with an invalid configuration for those devices. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus
The l parameter defines the number of clock cycles to process a single pixel per OP lane. It is calculated based on a new register op_bits_per_lane. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus
CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus
Add support for decoupled OP domain clock calculation. This means that the number of VT and OP domain clocks are no longer dependent on the number of CSI-2 lanes in the lane speed mode. The support also replaces the existing quirk flag to calculate OP domain clocks per lane. Also support decoupled OP domain calculation in the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus
Convey the relevant PLL flags to the PLL calculator. Also the lane speed model affects how the link rate is calculated on the CSI-2 bus, as the rate is total of all lanes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus
CCS PLL includes a capability to calculate the VT clocks on per-lane basis. Add support for this feature. Move calculation of the pixel rate on the CSI-2 bus early in the function as everything needed to calculate it is already available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus
Use uint32_t instead of unsigned int for a variable that contains explicitly 32-bit numbers. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus
The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus
The comment is about minimum PLL multiplier but the related check really deals with the maximum PLL multiplier. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus
The external clock frequency times the PLL multiplier may exceed the value range of 32-bit unsigned integers. Instead perform the same calculation y using two divisions. The result has some potential to be different, but that's ok: this number is used to limit the range of pre-PLL divisors to find optimal values. So the effect of the rare case of a different result here would mean an invalid pre-PLL divisor is tried. That will be found out a little later in any case. Also guard against dividing by zero if the external clock frequency is higher than the maximum OP PLL output clock --- a rather improbable case. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus
The lower bound of the pre-PLL divider was calculated based on OP SYS clock frequency which is also affected by the OP SYS clock divider. This is wrong. The right clock frequency is that of the PLL output clock. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus
The OP system clock frequency defines the CSI-2 bus clock frequency, not the PLL output clock frequency. Both values were overwritten in the end, but the wrong limit value was used for the OP system clock frequency, possibly leading to too high frequencies being used. Also remove now duplicated calculation of OP system clock frequency later in the PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus
Use the BIT macro for setting individual bits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus
The CCS pll is used by the CCS driver at the moment, but documenting the interface makes sense. It's non-trivial and the calculator could be used elsewhere. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus
This way the struct will use less memory, with better packing and no waste due to unsigned long. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus
Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include support for C-PHY. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus
The parallel bus PLL calculation has no users. Remove it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus
The VT divisor search can be ended if we've already found the value that corresponds exactly the total divisor, as there are no better (lower) values available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus
Use the correct video timing divisor to calculate the SYS divisor. Instead of the current value, the minimum was used. This could have resulted in a too low SYS divisor. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus
The CCS spec supports a lot of variation in the PLL. Split the PLL in front and back parts to better prepare for supporting it. Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include "clk" in the name). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus
pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to divide it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07MAINTAINERS: add a limited ARM and ARM64 SoC entryKrzysztof Kozlowski
It is expected for ARM and ARM64 SoC related code to go through sub-architecture maintainers. Their addresses were therefore not documented to push patch traffic through sub-architecture maintainers. However when patches touch generic code, e.g. multi_v7_defconfig, the patch might not be picked up by them and instead should go to the SoC maintainers - Arnd and Olof. Add a minimal maintainer's entry for SoC covering only Makefile, so it will not appear on most of submissions (except new devicetree boards). It will though serve as a documentation and reference for cases when submitter does not know where to send his SoC-related patches. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201201211516.24921-2-krzk@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07MAINTAINERS: correct SoC Git address (formerly: arm-soc)Krzysztof Kozlowski
The SoC Git was moved from arm/arm-soc.git to soc/soc.git. Correct the ARM Sub-architectures entry. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201201211516.24921-1-krzk@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07ARM: keystone: remove SECTION_SIZE_BITS/MAX_PHYSMEM_BITSArnd Bergmann
These definitions are evidently left over from the days when sparsemem settings were platform specific. This was no longer the case when the platform got merged. There was no warning in the past, but now the asm/sparsemem.h header ends up being included indirectly, causing this warning: In file included from /git/arm-soc/arch/arm/mach-keystone/keystone.c:24: arch/arm/mach-keystone/memory.h:10:9: warning: 'SECTION_SIZE_BITS' macro redefined [-Wmacro-redefined] #define SECTION_SIZE_BITS 34 ^ arch/arm/include/asm/sparsemem.h:23:9: note: previous definition is here #define SECTION_SIZE_BITS 28 ^ Clearly the definitions never had any effect here, so remove them. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20201203231847.1484900-1-arnd@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07Merge tag 'imx-fixes-5.10-5' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 5.10, round 5: - Fix a regression on SoC revision detection with ANATOP, that is introduced by commit 4a4fb66119eb ("ARM: imx: Add missing of_node_put()"). - Drop PAD_GPIO_6 from imx6qdl-wandboard ENET pin group, as the pin is used by camera sensor now. - Fix I2C3_SCL pinmux on imx6qdl-kontron-samx6i board, so that SoM EEPROM can be accessed. * tag 'imx-fixes-5.10-5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx6qdl-kontron-samx6i: fix I2C_PM scl pin ARM: dts: imx6qdl-wandboard-revd1: Remove PAD_GPIO_6 from enetgrp ARM: imx: Use correct SRC base address Link: https://lore.kernel.org/r/20201201091820.GW4072@dragon Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07Merge tag 'sunxi-fixes-for-5.10-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes A few more RGMII-ID fixes, and a bunch of other more random fixes * tag 'sunxi-fixes-for-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun7i: pcduino3-nano: enable RGMII RX/TX delay on PHY ARM: dts: sun8i: v3s: fix GIC node memory range ARM: dts: sun8i: v40: bananapi-m2-berry: Fix ethernet node ARM: dts: sun8i: r40: bananapi-m2-berry: Fix dcdc1 regulator ARM: dts: sun7i: bananapi: Enable RGMII RX/TX delay on Ethernet PHY ARM: dts: s3: pinecube: align compatible property to other S3 boards ARM: sunxi: Add machine match for the Allwinner V3 SoC arm64: dts: allwinner: h6: orangepi-one-plus: Fix ethernet Link: https://lore.kernel.org/r/1280f1de-1b6d-4cc2-8448-e5a9096a41e8.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07media: dt-bindings: schema indentation fixesRob Herring
Fix a few new indentation warnings found with yamllint (now integrated into the checks). Cc: Ricardo Ribalda <ribalda@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # For adv7604 Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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