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2016-03-09x86/fpu: Fix 'no387' regressionAndy Lutomirski
After fixing FPU option parsing, we now parse the 'no387' boot option too early: no387 clears X86_FEATURE_FPU before it's even probed, so the boot CPU promptly re-enables it. I suspect it gets even more confused on SMP. Fix the probing code to leave X86_FEATURE_FPU off if it's been disabled by setup_clear_cpu_cap(). Signed-off-by: Andy Lutomirski <luto@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com> Cc: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: yu-cheng yu <yu-cheng.yu@intel.com> Fixes: 4f81cbafcce2 ("x86/fpu: Fix early FPU command-line parsing") Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-03-09cxl: Ignore probes for virtual afu pci devicesVaibhav Jain
Add a check at the beginning of cxl_probe function to ignore virtual pci devices created for each afu registered. This fixes the the errors messages logged about missing CXL vsec, when cxl probe is unable to find necessary vsec entries in device pci config space. The error message logged are of the form : cxl-pci 0004:00:00.0: ABORTING: CXL VSEC not found! cxl-pci 0004:00:00.0: cxl_init_adapter failed: -19 Cc: Ian Munsie <imunsie@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: fbarrat@linux.vnet.ibm.com Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Remove cxl_get_phys_dev() kernel APIFrederic Barrat
The cxl_get_phys_dev() API returns a struct device pointer which could belong to either a struct pci_dev (bare-metal) or platform_device (powerVM). To avoid potential problems in drivers, remove that API. It was introduced to allow drivers to read the VPD of the adapter, but the cxl driver now provides the cxl_pci_read_adapter_vpd() API for that purpose. Co-authored-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxlflash: Use new cxl_pci_read_adapter_vpd() APIFrederic Barrat
To read the adapter VPD, drivers can't rely on pci config APIs, as it wouldn't work on powerVM. cxl introduced a new kernel API especially for this, so start using it. Co-authored-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Uma Krishnan <ukrishn@linux.vnet.ibm.com> Acked-by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com> Acked-by: Manoj N. Kumar <manoj@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Add tracepoints around the cxl hcallChristophe Lombard
To ease debugging, add a few tracepoints around the cxl hcalls. Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Adapter failure handlingChristophe Lombard
Check the AFU state whenever an API is called. The hypervisor may issue a reset of the adapter when it detects a fault. When it happens, it launches an error recovery which will either move the AFU to a permanent failure state, or in the disabled state. If the AFU is found to be disabled, detach all existing contexts from it before issuing a AFU reset to re-enable it. Before detaching contexts, notify any kernel driver through the EEH callbacks of the AFU pci device. Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Support the cxl kernel API from a guestFrederic Barrat
Like on bare-metal, the cxl driver creates a virtual PHB and a pci device for the AFU. The configuration space of the device is mapped to the configuration record of the AFU. Reuse the code defined in afu_cr_read8|16|32() when reading the configuration space of the AFU device. Even though the (virtual) AFU device is a pci device, the adapter is not. So a driver using the cxl kernel API cannot read the VPD of the adapter through the usual PCI interface. Therefore, we add a call to the cxl kernel API: ssize_t cxl_read_adapter_vpd(struct pci_dev *dev, void *buf, size_t count); Co-authored-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Parse device tree and create cxl device(s) at bootFrederic Barrat
Add new entry point to scan the device tree at boot in a guest, looking for cxl devices. Co-authored-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Support to flash a new image on the adapter from a guestChristophe Lombard
The new flash.c file contains the logic to flash a new image on the adapter, through a hcall. It is an iterative process, with chunks of data of 1M at a time. There are also 2 phases: write and verify. The flash operation itself is driven from a user-land tool. Once flashing is successful, an rtas call is made to update the device tree with the new properties values for the adapter and the AFU(s) Add a new char device for the adapter, so that the flash tool can access the card, even if there is no valid AFU on it. Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: sysfs support for guestsChristophe Lombard
Filter out a few adapter parameters which don't make sense in a guest. Document the changes. Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09cxl: Add guest-specific codeChristophe Lombard
The new of.c file contains code to parse the device tree to find out about cxl adapters and AFUs. guest.c implements the guest-specific callbacks for the backend API. The process element ID is not known until the context is attached, so we have to separate the context ID assigned by the cxl driver from the process element ID visible to the user applications. In bare-metal, the 2 IDs match. Co-authored-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> [mpe: Fix SMP=n build, fix PSERIES=n build, minor whitespace fixes] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-09gpio: omap: drop dev field from gpio_bank structureGrygorii Strashko
GPIO chip structure already has "parent" field which is used for the same purpose as "dev" field in gpio_bank structure - store pointer on GPIO device. Hence, drop duplicated "dev" field from gpio_bank structure. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-09pinctrl: Broadcom Northstar2 pinctrl device tree bindingsYendapally Reddy Dhananjaya Reddy
Device tree binding documentation for Broadcom NS2 IOMUX Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-09kvm: cap halt polling at exactly halt_poll_nsDavid Matlack
When growing halt-polling, there is no check that the poll time exceeds the limit. It's possible for vcpu->halt_poll_ns grow once past halt_poll_ns, and stay there until a halt which takes longer than vcpu->halt_poll_ns. For example, booting a Linux guest with halt_poll_ns=11000: ... kvm:kvm_halt_poll_ns: vcpu 0: halt_poll_ns 0 (shrink 10000) ... kvm:kvm_halt_poll_ns: vcpu 0: halt_poll_ns 10000 (grow 0) ... kvm:kvm_halt_poll_ns: vcpu 0: halt_poll_ns 20000 (grow 10000) Signed-off-by: David Matlack <dmatlack@google.com> Fixes: aca6ff29c4063a8d467cdee241e6b3bf7dc4a171 Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-09Merge tag 'kvm-arm-for-4.6' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/ARM updates for 4.6 - VHE support so that we can run the kernel at EL2 on ARMv8.1 systems - PMU support for guests - 32bit world switch rewritten in C - Various optimizations to the vgic save/restore code Conflicts: include/uapi/linux/kvm.h
2016-03-09Merge branch 'ib-mfd-regulator-gpio-4.6' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into devel
2016-03-09Merge tag 'gic-4.6' of ↵Thomas Gleixner
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull GIC updates for 4.6 from Marc Zyngier: - Basic GICv3 ACPI support - Alpine MSI widget on top of GICv3 - More RealView GIC support
2016-03-09perf bench mem: Prepare the x86-64 build for upstream memcpy_mcsafe() changesIngo Molnar
The following upcoming upstream commit: 92b0729c34ca ("x86/mm, x86/mce: Add memcpy_mcsafe()") Adds _ASM_EXTABLE_FAULT(), which is not available in user-space and breaks the build. We don't really need _ASM_EXTABLE_FAULT() in user-space, so simply wrap it to nothing. Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: David Ahern <dsahern@gmail.com> Cc: Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-03-09irqchip/gic/realview: Support more RealView DCC variantsLinus Walleij
In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09Documentation/bindings: Document the Alpine MSIX driverAntoine Tenart
Following the addition of the Alpine MSIX driver, this patch adds the corresponding bindings documentation. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09irqchip: Add the Alpine MSIX interrupt controllerAntoine Tenart
This patch adds the Alpine MSIX interrupt controller driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09irqchip/gic-v3: Always return IRQ_SET_MASK_OK_DONE in gic_set_affinityAntoine Tenart
Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the affinity has been updated. When using stacked irqchips, returning IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09spi: respect the maximum segment size of DMA deviceAndy Shevchenko
The device which is actually does DMA may have a limitation of the maximum segment size. Respect this setting when preparing scatter-gather list. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-09spi: rockchip: check requesting dma channel with EPROBE_DEFERShawn Lin
Let's defer probing the driver if the return value of dma_request_slave_channel is ERR_PTR(-EPROBE_DEFER) instead of disabling dma capability directly. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-09spi: rockchip: migrate to dmaengine_terminate_asyncShawn Lin
dmaengine_terminate_all is deprecated, let's use dmaengine_terminate_async for interrupt handling. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-09spi: rockchip: check return value of dmaengine_prep_slave_sgShawn Lin
We should check return value of dmaengine_prep_slave_sg, otherwise we take risk of null pointer. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-03-09dmaengine: fsldma: fix memory leakXuelin Shi
adding unmap of sources and destinations while doing dequeue. Signed-off-by: Xuelin Shi <xuelin.shi@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-09pinctrl: amlogic: Make driver independent from two-domain configurationCarlo Caione
In the Amlogic Meson8 / Meson8b platforms we have two different buses: cbus and aobus, corresponding to 2 different power domains (regular and always-on). On each bus a different set of registers is mapped to manage muxes, GPIOs and in general to control a clear subset of the pins. Considering this architecture, having two different pinctrl devices, one for each bus / power domain, makes much more sense than just having one single device. Right now we have one single pin controller driver that uses two different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the DTS) to manage the set of registers on the two buses. This dual-domain configuration is hardcoded into the driver that strictly requires one domain for each bus in the same pin controller device. With this patch we refactor the driver to allow splitting the driver in two parts. This change is needed to have a proper description of the HW in the device-tree where we want to introduce aobus and cbus. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-09pinctrl: amlogic: Separate some pin functions for Meson8 / Meson8bCarlo Caione
Separate functions for pins controlled by different pin controllers. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-09mfd: lpss: Add PCI IDs for Intel Broxton B-Step platformHuiquan Zhong
Add PCI IDs for Intel Broxton B-Step platform, which have same LPSS devices with A-Step. Signed-off-by: Huiquan Zhong <huiquan.zhong@intel.com> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> cked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-09mfd: Allow i2c modular drivers to build with I2C=mAxel Lin
These drivers can be built as module, so make them depend on I2C rather than I2C=y. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-09mfd: intel-lpss: Remove clock tree on error pathAndy Shevchenko
We forgot to remove the clock tree if something goes wrong in ->probe(). Add a call to intel_lpss_unregister_clock() on error path in ->probe() to fix the potential issue. Fixes: 4b45efe85263 (mfd: Add support for Intel Sunrisepoint LPSS devices) Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-09mfd: tps65010: Fix init when the driver is built-inAaro Koskinen
tps65010 driver's initcall cannot succeed when the driver is built-in, because it expects that the I2C probe is completed at initcall time; this cannot happen as MFD is initialized before I2C. Also on systems where the chip is not present there is unnecessary 30 ms delay during the boot. Instead of waiting for probe to finish, just register the I2C device. If some boards need retry mechanism for startup glitches, that should be done in the actual probe function. Also delete the driver banner message. The patch allows to use tps65010 again with OMAP1 (where it's required to be built-in) and enables e.g. USB and LED functionality on OMAP5912 OSK. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-09Merge branches 'ib-mfd-clk-4.6', 'ib-mfd-input-iio-4.6', ↵Lee Jones
'ib-mfd-regulator-4.6' and 'ib-mfd-regulator-gpio-4.6' into ibs-for-mfd-merged
2016-03-09iio: adc/imx25-gcq: Move incorrect do_divArnd Bergmann
The newly added driver uses do_div() to device a 32-bit number, which now provokes a warning: drivers/iio/adc/fsl-imx25-gcq.c: In function 'mx25_gcq_setup_cfgs': include/asm-generic/div64.h:207:28: warning: comparison of distinct pointer types lacks a cast (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ This replaces the do_div() call with a straight division operator. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 6df2e98c3ea5 ("iio: adc: Add imx25-gcq ADC driver") Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-03-08ext4: remove i_ioend_countJan Kara
Remove counter of pending io ends as it is unused. Signed-off-by: Jan Kara <jack@suse.cz> Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2016-03-08ext4: simplify io_end handling for AIO DIOJan Kara
When mapping blocks for direct IO, we allocate io_end structure before mapping blocks and store pointer to it in the inode. This creates a requirement that any AIO DIO using io_end must be protected by i_mutex. This created problems in the past with dioread_nolock mode which was corrupting io_end pointers. Also io_end is allocated unnecessarily in case where we don't need to convert any extents (which is a common case for example when overwriting file). We fix the problem by allocating io_end only once we return unwritten extent from block mapping function for AIO DIO (so we can save some pointless io_end allocations) and we pass pointer to it in bh->b_private which generic DIO code later passes to our end IO callback. That way we remove any need for global pointer to io_end structure and thus fix the races. The downside of this change is that the checking for unwritten IO in flight in ext4_extents_can_be_merged() is more racy since we now increment i_unwritten / set EXT4_STATE_DIO_UNWRITTEN only after dropping i_data_sem. However the check has been racy already before because ext4_writepages() already increment i_unwritten after dropping i_data_sem and reserved blocks save us from hitting ENOSPC in the worst case. Signed-off-by: Jan Kara <jack@suse.cz>
2016-03-08ext4: move trans handling and completion deferal out of _ext4_get_blockJan Kara
There is no need to handle starting of a transaction and deferal of DIO completion in _ext4_get_block() function. We can move this out to get block functions for direct IO that need it. That way we can add stricter checks verifying things work as we expect. Signed-off-by: Jan Kara <jack@suse.cz> Signed-off-by: Theodore Ts'o <tytso@mit.edu>
2016-03-08PCI: Add QEMU top-level IDs for (sub)vendor & deviceRobin H. Johnson
Introduce PCI_VENDOR/PCI_SUBVENDOR/PCI_SUBDEVICE defines to replace the constants scattered in the kernel already used to detect QEMU. They are defined in the QEMU codebase per docs/specs/pci-ids.txt. Signed-off-by: Robin H. Johnson <robbat2@gentoo.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-03-08Merge tag 'usb-serial-4.6-rc1' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial into usb-next Johan writes: USB-serial updates for v4.6-rc1 Here are some cp210x register-accessor updates and general usb-serial code clean ups. Signed-off-by: Johan Hovold <johan@kernel.org>
2016-03-09arm64: KVM: vgic-v3: Only wipe LRs on vcpu exitMarc Zyngier
So far, we're always writing all possible LRs, setting the empty ones with a zero value. This is obvious doing a low of work for nothing, and we're better off clearing those we've actually dirtied on the exit path (it is very rare to inject more than one interrupt at a time anyway). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09arm64: KVM: vgic-v3: Reset LRs at boot timeMarc Zyngier
In order to let the GICv3 code be more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed (which includes a round trip to EL2...). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09arm64: KVM: vgic-v3: Do not save an LR known to be emptyMarc Zyngier
On exit, any empty LR will be signaled in ICH_ELRSR_EL2. Which means that we do not have to save it, and we can just clear its state in the in-memory copy. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09arm64: KVM: vgic-v3: Save maintenance interrupt state only if requiredMarc Zyngier
Next on our list of useless accesses is the maintenance interrupt status registers (ICH_MISR_EL2, ICH_EISR_EL2). It is pointless to save them if we haven't asked for a maintenance interrupt the first place, which can only happen for two reasons: - Underflow: ICH_HCR_UIE will be set, - EOI: ICH_LR_EOI will be set. These conditions can be checked on the in-memory copies of the regs. Should any of these two condition be valid, we must read GICH_MISR. We can then check for ICH_MISR_EOI, and only when set read ICH_EISR_EL2. This means that in most case, we don't have to save them at all. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09arm64: KVM: vgic-v3: Avoid accessing ICH registersMarc Zyngier
Just like on GICv2, we're a bit hammer-happy with GICv3, and access them more often than we should. Adopt a policy similar to what we do for GICv2, only save/restoring the minimal set of registers. As we don't access the registers linearly anymore (we may skip some), the convoluted accessors become slightly simpler, and we can drop the ugly indexing macro that tended to confuse the reviewers. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09KVM: arm/arm64: vgic-v2: Make GICD_SGIR quicker to hitMarc Zyngier
The GICD_SGIR register lives a long way from the beginning of the handler array, which is searched linearly. As this is hit pretty often, let's move it up. This saves us some precious cycles when the guest is generating IPIs. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exitMarc Zyngier
So far, we're always writing all possible LRs, setting the empty ones with a zero value. This is obvious doing a lot of work for nothing, and we're better off clearing those we've actually dirtied on the exit path (it is very rare to inject more than one interrupt at a time anyway). Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09KVM: arm/arm64: vgic-v2: Reset LRs at boot timeMarc Zyngier
In order to let make the GICv2 code more lazy in the way it accesses the LRs, it is necessary to start with a clean slate. Let's reset the LRs on each CPU when the vgic is probed. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09KVM: arm/arm64: vgic-v2: Do not save an LR known to be emptyMarc Zyngier
On exit, any empty LR will be signaled in GICH_ELRSR*. Which means that we do not have to save it, and we can just clear its state in the in-memory copy. Take this opportunity to move the LR saving code into its own function. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09KVM: arm/arm64: vgic-v2: Move GICH_ELRSR saving to its own functionMarc Zyngier
In order to make the saving path slightly more readable and prepare for some more optimizations, let's move the GICH_ELRSR saving to its own function. No functional change. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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