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2021-01-21drm/amdgpu: remove gpu info firmware of green sardineHuang Rui
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdkfd: Enable userptr support when KFD is enabledFelix Kuehling
ROCm user mode depends on userptr support. Without it, KFD is basically useless. Make sure HSA_AMD selects the same options as DRM_AMDGPU_USERPTR to avoid broken configurations where userptr gets enabled but its dependencies are disabled. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/pm: print the timeout of smc messageHuang Rui
This patch is to help firmware designer to know the smc message timeout status. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu:Add pcie gen5 support in pcie capability.Feifei Xu
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu: Allow GfxOff on Vangogh as defaultJinzhou Su
Send allow GfxOff message to SMU to enter GfxOff mode as default. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu: Assign boolean values to a bool variableJiapeng Zhong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 1009:6-16: WARNING: Assignment of 0/1 to bool variable. ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 200:2-10: WARNING: Assignment of 0/1 to bool variable. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Fix spelling mistake of function nameColin Ian King
There are two spelling mistakes of the function name, fix this by using __func__ instead of a hard coded name string. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Update dcn30_apply_idle_power_optimizations() codeBhawanpreet Lakha
Update the function for idle optimizations -remove hardcoded size -enable no memory-request case -add cursor copy -update mall eligibility check case Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Dynamic cursor cache size for MALL eligibility checkBhawanpreet Lakha
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amd/display: Enable programing of MALL watermarksBhawanpreet Lakha
-Uncomment watermark set d -This populates the wm table so that it can be sent to PMFW -This watermark table is used when we are in mall stutter Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu: Add RLC_PG_DELAY_3 for VangoghJinzhou Su
Driver should enable the CGPG feature for RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence. Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1, and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value in refclk count. Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/amdgpu/pm: no need GPU status set since ↵Prike Liang
mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-21drm/i915/gvt: Add missing forward decl of intel_vgpu for HDRTESTChris Wilson
./drivers/gpu/drm/i915/gvt/cmd_parser.h:53:44: error: ‘struct intel_vgpu’ declared inside parameter list will not be visible outside of this definition or declaration Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210121132558.2893-1-chris@chris-wilson.co.uk
2021-01-21drm/msm/dp: fix build after dp quirk helper changeJani Nikula
Commit 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based quirks"") removed drm_dp_get_edid_quirks() and changed the signature of drm_dp_has_quirk() while they were still being used in msm. Fix the breakage. Functionally, removing the EDID-based quirks has no impact on msm. [The above commit was merged to drm-intel-next; make two wrongs a right by merging this fix through drm-intel-next as well.] Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> References: http://lore.kernel.org/r/20210120105715.4391dd95@canb.auug.org.au Fixes: 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based quirks"") Cc: Lyude Paul <lyude@redhat.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Lyude Paul <lyude@redhat.com> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120110708.32131-1-jani.nikula@intel.com
2021-01-21Merge tag 'gvt-gt-next-2021-01-18' of https://github.com/intel/gvt-linux ↵Joonas Lahtinen
into drm-intel-gt-next gvt-gt-next-2021-01-18 - GVT cmd parser enhancement against guest context (Yan) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210118050739.GY15982@zhen-hp.sh.intel.com
2021-01-21lightnvm: fix memory leak when submit failsPan Bian
The allocated page is not released if error occurs in nvm_submit_io_sync_raw(). __free_page() is moved ealier to avoid possible memory leak issue. Fixes: aff3fb18f957 ("lightnvm: move bad block and chunk state logic to core") Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-01-21Merge tag 'nvme-5.11-2020-01-21' of git://git.infradead.org/nvme into block-5.11Jens Axboe
Pull NVMe fixes from Christoph: "nvme fixes for 5.11: - fix a status code in nvmet (Chaitanya Kulkarni) - avoid double completions in nvme-rdma/nvme-tcp (Chao Leng) - fix the CMB support to cope with NVMe 1.4 controllers (Klaus Jensen) - fix PRINFO handling in the passthrough ioctl (Revanth Rajashekar) - fix a double DMA unmap in nvme-pci" * tag 'nvme-5.11-2020-01-21' of git://git.infradead.org/nvme: nvme-pci: fix error unwind in nvme_map_data nvme-pci: refactor nvme_unmap_data nvmet: set right status on error in id-ns handler nvme-pci: allow use of cmb on v1.4 controllers nvme-tcp: avoid request double completion for concurrent nvme_tcp_timeout nvme-rdma: avoid request double completion for concurrent nvme_rdma_timeout nvme: check the PRINFO bit before deciding the host buffer length
2021-01-21x86/mmx: Use KFPU_387 for MMX string operationsAndy Lutomirski
The default kernel_fpu_begin() doesn't work on systems that support XMM but haven't yet enabled CR4.OSFXSR. This causes crashes when _mmx_memcpy() is called too early because LDMXCSR generates #UD when the aforementioned bit is clear. Fix it by using kernel_fpu_begin_mask(KFPU_387) explicitly. Fixes: 7ad816762f9b ("x86/fpu: Reset MXCSR to default in kernel_fpu_begin()") Reported-by: Krzysztof Mazur <krzysiek@podlesie.net> Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Tested-by: Krzysztof Piotr Olędzki <ole@ans.pl> Tested-by: Krzysztof Mazur <krzysiek@podlesie.net> Cc: <stable@vger.kernel.org> Link: https://lkml.kernel.org/r/e7bf21855fe99e5f3baa27446e32623358f69e8d.1611205691.git.luto@kernel.org
2021-01-21drm/i915/gt: Skip over completed active execlists, againChris Wilson
Now that we are careful to always force-restore contexts upon rewinding (where necessary), we can restore our optimisation to skip over completed active execlists when dequeuing. Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a completed context") References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120121718.26435-2-chris@chris-wilson.co.uk
2021-01-21drm/i915/gt: Do not suspend bonded requests if one hangsChris Wilson
Treat the dependency between bonded requests as weak and leave the remainder of the pair on the GPU if one hangs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120121718.26435-1-chris@chris-wilson.co.uk
2021-01-21drm/i915/dp: split out aux functionality to intel_dp_aux.cJani Nikula
Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a surprisingly clean cut. v2: - Remove intel_dp_pack_aux declaration from intel_dp.h (Anshuman) - Fixed some whitespace/comment checkpatch warnings Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-4-jani.nikula@intel.com
2021-01-21drm/i915/dp: abstract struct intel_dp pps members to a sub-structJani Nikula
Add some namespacing to highlight what belongs where. No functional changes. Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-3-jani.nikula@intel.com
2021-01-21drm/i915/pps: move pps code over from intel_display.c and refactorJani Nikula
intel_display.c has some pps functions that belong to intel_pps.c. Move them over. While at it, refactor the duplicate intel_pps_init() in intel_display.c into an orthogonal intel_pps_setup() in intel_pps.c, and call it earlier in intel_modeset_init_nogem(). Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-2-jani.nikula@intel.com
2021-01-21drm/i915/pps: refactor init abstractionsJani Nikula
Once you realize there is no need to hold the pps mutex when calling pps_init_timestamps() in intel_pps_init(), we can reuse intel_pps_encoder_reset() which has the same code. Since intel_dp_pps_init() is only called from one place now, move it inline to remove one "init" function altogether. Finally, remove some initialization from vlv_initial_power_sequencer_setup() and do it in the caller to highlight the similarity, not the difference, in the platforms. v2: Fix comment (Anshuman) Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-1-jani.nikula@intel.com
2021-01-21x86/fpu: Add kernel_fpu_begin_mask() to selectively initialize stateAndy Lutomirski
Currently, requesting kernel FPU access doesn't distinguish which parts of the extended ("FPU") state are needed. This is nice for simplicity, but there are a few cases in which it's suboptimal: - The vast majority of in-kernel FPU users want XMM/YMM/ZMM state but do not use legacy 387 state. These users want MXCSR initialized but don't care about the FPU control word. Skipping FNINIT would save time. (Empirically, FNINIT is several times slower than LDMXCSR.) - Code that wants MMX doesn't want or need MXCSR initialized. _mmx_memcpy(), for example, can run before CR4.OSFXSR gets set, and initializing MXCSR will fail because LDMXCSR generates an #UD when the aforementioned CR4 bit is not set. - Any future in-kernel users of XFD (eXtended Feature Disable)-capable dynamic states will need special handling. Add a more specific API that allows callers to specify exactly what they want. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Tested-by: Krzysztof Piotr Olędzki <ole@ans.pl> Link: https://lkml.kernel.org/r/aff1cac8b8fc7ee900cf73e8f2369966621b053f.1611205691.git.luto@kernel.org
2021-01-21Merge 9bb48c82aced ("tty: implement write_iter") into tty-linusGreg Kroah-Hartman
We want the single "splice/sendfile to a tty" regression fix into tty-linus so it can get into 5.11-final, while the larger patch series fixing "splice/sendfile from a tty" should wait for 5.12-rc1 so that we get more testing. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-21mm/memblock: Fix typo in comment of memblock_phys_alloc_try_nid()Levi Yun
memblock_phys_alloc_try_nid function's comments has typo NUMA as MUMA. Correct this typo. Signed-off-by: Levi Yun <ppbuk5246@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
2021-01-20tty: implement write_iterLinus Torvalds
This makes the tty layer use the .write_iter() function instead of the traditional .write() functionality. That allows writev(), but more importantly also makes it possible to enable .splice_write() for ttys, reinstating the "splice to tty" functionality that was lost in commit 36e2c7421f02 ("fs: don't allow splice read/write without explicit ops"). Fixes: 36e2c7421f02 ("fs: don't allow splice read/write without explicit ops") Reported-by: Oliver Giles <ohw.giles@gmail.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-01-20mtd: rawnand: omap: Use BCH private fields in the specific OOB layoutMiquel Raynal
The OMAP driver may leverage software BCH logic to locate errors while using its own hardware to detect the presence of errors. This is achieved with a "mixed" mode which initializes manually the software BCH internal logic while providing its own OOB layout. The issue here comes from the fact that the BCH driver has been updated to only use generic NAND objects, and no longer depend on raw NAND structures as it is usable from SPI-NAND as well. However, at the end of the BCH context initialization, the driver checks the validity of the OOB layout. At this stage, the raw NAND fields have not been populated yet while being used by the layout helpers, leading to an invalid layout. The chosen solution here is to include the BCH structure definition and to refer to the BCH fields directly (de-referenced as a const pointer here) to know as early as possible the number of steps and ECC bytes which have been chosen. Note: I don't know which commit exactly triggered the error, but the entire migration to a generic BCH driver got merged in one go, so this should not be a problem for stable backports. Reported-by: Adam Ford <aford173@gmail.com> Fixes: 80fe603160a4 ("mtd: nand: ecc-bch: Stop using raw NAND structures") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Adam Ford <aford173@gmail.com> #logicpd-torpedo-37xx-devkit-28.dts Link: https://lore.kernel.org/linux-mtd/20210119155510.5655-1-miquel.raynal@bootlin.com
2021-01-20Merge tag 'for-5.11-rc4-tag' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux Pull btrfs fixes from David Sterba: "A few more one line fixes for various bugs, stable material. - fix send when emitting clone operation from the same file and root - fix double free on error when cleaning backrefs - lockdep fix during relocation - handle potential error during reloc when starting transaction - skip running delayed refs during commit (leftover from code removal in this dev cycle)" * tag 'for-5.11-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux: btrfs: don't clear ret in btrfs_start_dirty_block_groups btrfs: fix lockdep splat in btrfs_recover_relocation btrfs: do not double free backref nodes on error btrfs: don't get an EINTR during drop_snapshot for reloc btrfs: send: fix invalid clone operations when cloning from the same file and root btrfs: no need to run delayed refs after commit_fs_roots during commit
2021-01-20drm/amdgpu: modify GCR_GENERAL_CNTL for VangoghJinzhou Su
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amdgpu: Remove GFXOFF MASK for VangoghJinzhou Su
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled by user space. 2. GFXOFF is still disabled on Vangogh by default. 3. When GFXOFF feature on Vangogh landed, will enable GFXOFF by default. 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: 3.2.119Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: [FW Promotion] Release 0.0.48Anthony Koo
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Update dram_clock_change_latency for DCN2.1Jake Wang
[WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Allow PSTATE chnage when no displays are enabledAric Cyr
[Why] When no displays are currently enabled, display driver should not disallow PSTATE switching. [How] Allow PSTATE switching if either the active configuration supports it, or there are no active displays. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to ↵Bing Guo
check DesiredBPP. Why: dml20v2_ModeSupportAndSystemConfigurationFull() didn't check against DesiredBPP, so it doesn't work correctly when DesiredBPP can't be satisfied. How: Port the TruncToValidBPP() version from display_mode_vba_21.c to display_mode_vba_20v2.c. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Log link/connector info provided in BIOS object tableGeorge Shen
[Why/How] Add logging statements to assist in debugging errors in the BIOS object table. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Allow dmu_stg to support cached inbox for dmubWyatt Wood
[Why] FW version check doesn't allow dmu_stg to support cached inbox, which yields much better performance than region 4. [How] Check a range of fw versions, rather than a simple greater than check. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Change function decide_dp_link_settings to avoid infinite ↵Bing Guo
looping Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Fix reset sequence with driver direct DMCUB fw loadNicholas Kazlauskas
[Why] DMCUB encounters a page fault/double exception with driver direct load because DMCUB is not held in soft reset after releasing secure reset. The clean shutdown sequence via GPINT is also not executed in this sequence which leaves hardware behavior in an indeterminate state. [How] Move reset earlier in the sequence. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Guard against NULL pointer deref when get_i2c_info failsNicholas Kazlauskas
[Why] If the BIOS table is invalid or corrupt then get_i2c_info can fail and we dereference a NULL pointer. [How] Check that ddc_pin is not NULL before using it and log an error if it is because this is unexpected. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Allow dmub srv hardware reset before HW initNicholas Kazlauskas
[Why] We need hardware reset before hardware init for backdoor loading when we're reusing the framebuffer memory. [How] This doesn't run if the hardware isn't already in reset from software perspective. The reset function has register level checks so just remove the software one here. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Report Freesync to vrr_range debugfs entry in DRMStylon Wang
[Why] Since Linux 5.9.0, DRM has provided vrr_range debugfs for all connectors. Reporting Freesync capability to vrr_range debugfs entry registered in Linux DM no longer works. [How] Report min/max vertical frequency to vrr_range debugfs entrry created by DRM connectors. Remove vrr_range debugfs entry from Linux DM. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Use hardware sequencer functions for PG controlNicholas Kazlauskas
[Why & How] These can differ per ASIC or not be present. Don't call the dcn20 ones directly but rather the ones defined by the ASIC init table. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM CaseSung Lee
[WHY] Previously as MPO + ODM Combine was not supported, finding secondary pipes for each case was mutually exclusive. Now that both are supported at the same time, both cases should be taken into account when finding a secondary pipe. [HOW] If a secondary pipe cannot be found based on previous bottom pipe, search for a second pipe using next_odm_pipe instead. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: disable FEC while using eDPMike Hsieh
[Why] FEC over eDP support is incomplete. [How] Disable FEC over eDP. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Mike Hsieh <chun-wei.hsieh@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/display: Fixed corruptions on HPDRX link loss restoreVladimir Stempen
[why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-20drm/amd/amdgpu: remove redundant flush_delayed_workJingwen Chen
When using cancel_delayed_work_sync, there's no need to flush_delayed_work first. This sequence can lead to a redundant loop of work executing. Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-13 18:20:13 +0000