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2023-08-07drm/i915/adls: s/ADLS_RPLS/RAPTORLAKE_S in platform and subplatform definesDnyaneshwar Bhadane
Driver refers to the platform Alderlake S as ADLS_RPLS in places and RAPTORLAKE_S in some. v2: - Unrolled wrapper IS_ADLS_GRAPHICS_STEP v3: - Replace IS_RAPTORLAKE_S instead of IS_ADLS_RPLS. (Tvrtko/Lucas). - Remove unused macro IS_ADLS_GRAPHICS/DISPLAY_STEP - Change the subject Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-15-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/adln: s/ADLP/ALDERLAKE_P in ADLN definesAnusha Srivatsa
Follow consistent naming convention. Replace ADLP with ALDERLAKE_P Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-14-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace ADLP with ALDERLAKE_P v2: - Replace IS_ADLP_RPLU with IS_RAPTORLAKE_U (Tvrtko/Lucas) - Change the subject Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-13-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/rplp: s/ADLP_RPLP/RAPTORLAKE_P for RPLP definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace ADLP with ALDERLAKE_P. v2: - Replace IS_ADLP_RPLP with IS_RAPTORLAKE_P. (Tvrtko/Lucas) - Change the subject Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-12-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane
Driver refers to the platform Alderlake P as ADLP in places and ALDERLAKE_P in some. Making the consistent change to avoid confusion of the right naming convention for the platform. v2: - Unrolled wrapper IS_ADLP_GRAPHICS_STEP and Replace - Added IS_ALDERLAKE_P() && IS_GRAPHICS_STEP() (Jani/Tvrtko). v3: - Removed unused macros of display steps. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-11-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/tgl: s/TGL/TIGERLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace TGL with TIGERLAKE.Replace IS_TGL_DISPLAY_STEP with IS_TIGERLAKE() && IS_DISPLAY_STEP(). v2: - s/TGL/tgl in the subject prefix(Anusha) v3: - Unrolled wrapper IS_TGL_DISPLAY_STEP and Replace - Replace IS_PLATFORM && DISPLAY_STEP (Jani/Tvrtko). v4: - Removed unused macros Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-10-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace JSL with JASPERLAKE. Unroll IS_JSL_EHL() define with IS_JASPERLAKE() || IS_ELKHARTLAKE() condition. Change in the display step define for Jasperlake. v2: - Change subject prefix skl instead of SKL(Anusha) v3: - Remove the use of define IS_JSL_EHL. - Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE() - Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP (Jani/Tvrtko) v4: - Removed unused macro v5: - Resolved valid checkpatch warning(Jani) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-9-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/rkl: s/RKL/ROCKETLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace RKL with ROCKETLAKE.Replace IS_RKL_GRAPHICS_STEP with IS_ROCKETLAKE && IS_DISPLAY_STEP. v2: - s/RKL/rkl in the subject prefix(Anusha) v3: - Unrolled wrapper IS_RKL_DISPLAY_STEP. - Replace IS_PLATFORM && IS_DISPLAY_STEP (Jani/Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-8-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/cml: s/CML/COMETLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace CML with COMETLAKE. Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-7-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/cfl: s/CFL/COFFEELAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace CFL with COFFEELAKE. Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-6-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace KBL with KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with IS_KABYLAKE () && IS_GRAPHICS_STEP(). v2: - s/KBL/kbl in the subject prefix(Anusha) v3: - Unrolled wrapper IS_KBL_GRAPHICS_STEP. - Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani) v4: - Removed unused macro. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-5-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/skl: s/SKL/SKYLAKE for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace SKL with SKYLAKE and Replace IS_SKL_GRAPHICS_STEP with IS_SKYLAKE() && IS_GRAPHICS_STEP(). v2: - Change subject skl instead of SKL(Anusha) v3: - Unrolled wrapper IS_SKL_GRAPHICS_STEP. - Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani) v4: - Removed the unused macro. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-4-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace BDW with BROADWELL. Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-3-dnyaneshwar.bhadane@intel.com
2023-08-07drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane
Follow consistent naming convention. Replace HSW with HASWELL. Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-2-dnyaneshwar.bhadane@intel.com
2023-08-07ASoC: Intel: sof-sdw-cs42142: fix for codec button mappingjairaj-arava
The CS42142 soundwire codec button mapping is corrected to handle the button detection correctly. Fixes: 43cdea08a4ac ("ASoC: Intel: sof_sdw: Add helper function for cs42l42 codec") Signed-off-by: jairaj-arava <jairaj.arava@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20230807215000.515846-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-07ASoC: Intel: sof-sdw: update jack detection quirk for LunarLake RVPPierre-Louis Bossart
Experimental results show that the headset is only detected with the JD2 quirk. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20230807215000.515846-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-07drm/msm: Disallow relocs on a6xx+Rob Clark
Mesa stopped using these pretty early in a6xx bringup[1]. Take advantage of this to disallow some legacy UABI. [1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/7ef722861b691ce99be3827ed05f8c0ddf2cd66e Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Patchwork: https://patchwork.freedesktop.org/patch/551175/
2023-08-07drm/msm/a6xx: Fix GMU lockdep splatRob Clark
For normal GPU devfreq, we need to acquire the GMU lock while already holding devfreq locks. But in the teardown path, we were calling dev_pm_domain_detach() while already holding the GMU lock, resulting in this lockdep splat: ====================================================== WARNING: possible circular locking dependency detected 6.4.3-debug+ #3 Not tainted ------------------------------------------------------ ring0/391 is trying to acquire lock: ffffff80a025c078 (&devfreq->lock){+.+.}-{3:3}, at: qos_notifier_call+0x30/0x74 but task is already holding lock: ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #4 (&(c->notifiers)->rwsem){++++}-{3:3}: down_write+0x58/0x74 __blocking_notifier_chain_register+0x64/0x84 blocking_notifier_chain_register+0x1c/0x28 freq_qos_add_notifier+0x5c/0x7c dev_pm_qos_add_notifier+0xd4/0xf0 devfreq_add_device+0x42c/0x560 devm_devfreq_add_device+0x6c/0xb8 msm_devfreq_init+0xa8/0x16c [msm] msm_gpu_init+0x368/0x54c [msm] adreno_gpu_init+0x248/0x2b0 [msm] a6xx_gpu_init+0x2d0/0x384 [msm] adreno_bind+0x264/0x2bc [msm] component_bind_all+0x124/0x1f4 msm_drm_bind+0x2d0/0x5f4 [msm] try_to_bring_up_aggregate_device+0x88/0x1a4 __component_add+0xd4/0x128 component_add+0x1c/0x28 dp_display_probe+0x37c/0x3c0 [msm] platform_probe+0x70/0xc0 really_probe+0x148/0x280 __driver_probe_device+0xfc/0x114 driver_probe_device+0x44/0x100 __device_attach_driver+0x64/0xdc bus_for_each_drv+0xb0/0xd8 __device_attach+0xe4/0x140 device_initial_probe+0x1c/0x28 bus_probe_device+0x44/0xb0 deferred_probe_work_func+0xb0/0xc8 process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #3 (dev_pm_qos_mtx){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 dev_pm_qos_remove_notifier+0x3c/0xc8 genpd_remove_device+0x40/0x11c genpd_dev_pm_detach+0x88/0x130 dev_pm_domain_detach+0x2c/0x3c a6xx_gmu_remove+0x44/0xdc [msm] a6xx_destroy+0x7c/0xa4 [msm] adreno_unbind+0x50/0x64 [msm] component_unbind+0x44/0x64 component_unbind_all+0xb4/0xbc msm_drm_uninit.isra.0+0x124/0x17c [msm] msm_drm_bind+0x340/0x5f4 [msm] try_to_bring_up_aggregate_device+0x88/0x1a4 __component_add+0xd4/0x128 component_add+0x1c/0x28 dp_display_probe+0x37c/0x3c0 [msm] platform_probe+0x70/0xc0 really_probe+0x148/0x280 __driver_probe_device+0xfc/0x114 driver_probe_device+0x44/0x100 __device_attach_driver+0x64/0xdc bus_for_each_drv+0xb0/0xd8 __device_attach+0xe4/0x140 device_initial_probe+0x1c/0x28 bus_probe_device+0x44/0xb0 deferred_probe_work_func+0xb0/0xc8 process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #2 (&a6xx_gpu->gmu.lock){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 a6xx_gpu_set_freq+0x38/0x64 [msm] msm_devfreq_target+0x170/0x18c [msm] devfreq_set_target+0x90/0x1e4 devfreq_update_target+0xb4/0xf0 update_devfreq+0x1c/0x28 devfreq_monitor+0x3c/0x10c process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #1 (&df->lock){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 msm_devfreq_get_dev_status+0x4c/0x104 [msm] devfreq_simple_ondemand_func+0x5c/0x128 devfreq_update_target+0x68/0xf0 update_devfreq+0x1c/0x28 devfreq_monitor+0x3c/0x10c process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #0 (&devfreq->lock){+.+.}-{3:3}: __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 qos_notifier_call+0x30/0x74 qos_min_notifier_call+0x1c/0x28 notifier_call_chain+0xf4/0x114 blocking_notifier_call_chain+0x4c/0x78 pm_qos_update_target+0x184/0x190 freq_qos_apply+0x4c/0x64 apply_constraint+0xf8/0xfc __dev_pm_qos_update_request+0x138/0x164 dev_pm_qos_update_request+0x44/0x68 msm_devfreq_boost+0x40/0x70 [msm] msm_devfreq_active+0xc0/0xf0 [msm] msm_gpu_submit+0xc8/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x240/0x324 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 other info that might help us debug this: Chain exists of: &devfreq->lock --> dev_pm_qos_mtx --> &(c->notifiers)->rwsem Possible unsafe locking scenario: CPU0 CPU1 ---- ---- rlock(&(c->notifiers)->rwsem); lock(dev_pm_qos_mtx); lock(&(c->notifiers)->rwsem); lock(&devfreq->lock); *** DEADLOCK *** 4 locks held by ring0/391: #0: ffffff809c811170 (&gpu->lock){+.+.}-{3:3}, at: msm_job_run+0x7c/0x128 [msm] #1: ffffff809c811208 (&gpu->active_lock){+.+.}-{3:3}, at: msm_gpu_submit+0xa8/0x12c [msm] #2: ffffffecbbb46600 (dev_pm_qos_mtx){+.+.}-{3:3}, at: dev_pm_qos_update_request+0x38/0x68 #3: ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78 stack backtrace: CPU: 6 PID: 391 Comm: ring0 Not tainted 6.4.3debug+ #3 Hardware name: Google Villager (rev1+) with LTE (DT) Call trace: dump_backtrace+0xb4/0xf0 show_stack+0x20/0x30 dump_stack_lvl+0x60/0x84 dump_stack+0x18/0x24 print_circular_bug+0x1cc/0x234 check_noncircular+0x78/0xac __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 qos_notifier_call+0x30/0x74 qos_min_notifier_call+0x1c/0x28 notifier_call_chain+0xf4/0x114 blocking_notifier_call_chain+0x4c/0x78 pm_qos_update_target+0x184/0x190 freq_qos_apply+0x4c/0x64 apply_constraint+0xf8/0xfc __dev_pm_qos_update_request+0x138/0x164 dev_pm_qos_update_request+0x44/0x68 msm_devfreq_boost+0x40/0x70 [msm] msm_devfreq_active+0xc0/0xf0 [msm] msm_gpu_submit+0xc8/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x240/0x324 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 Fix this by only synchronizing access to gmu->initialized. Fixes: 4cd15a3e8b36 ("drm/msm/a6xx: Make GPU destroy a bit safer") Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/551171/
2023-08-07drm/msm/a2xx: Call adreno_gpu_init() earlierFabio Estevam
The adreno_is_a20x() and adreno_is_a225() functions rely on the GPU revision, but such information is retrieved inside adreno_gpu_init(), which is called afterwards. Fix this problem by caling adreno_gpu_init() earlier, so that the GPU information revision is available when adreno_is_a20x() and adreno_is_a225() run. Tested on a imx53-qsb board. Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx") Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543456/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Fix up GMU region reservationsKonrad Dybcio
Change the order of region allocations to make the addresses match downstream. This shouldn't matter very much, but helps eliminate one more difference when comparing register accesses. Also, make the log region 16K long. That's what it is, unconditionally on A6xx and A7xx. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543338/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Improve GMU force shutdown sequenceKonrad Dybcio
The GMU force shutdown sequence involves some additional register cleanup which was not implemented previously. Do so. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543340/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_startKonrad Dybcio
While it's not very well understood, there is some sort of a fault handler implemented in the GMU firmware which triggers when a certain bit is set, resulting in the M3 core not booting up the way we expect it to. Write a magic value to a magic register to hopefully prevent that from happening. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Skip empty protection ranges entriesKonrad Dybcio
Some specific SKUs leave certain protection range registers empty. Allow for that behavior. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543334/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTLKonrad Dybcio
We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543332/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Add some missing header definitionsKonrad Dybcio
Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL bitfields. This may be substituted with a mesa header sync. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/543330/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-08-07drm/msm/a6xx: Fix misleading commentRob Clark
The range is actually len+1. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/545099/
2023-08-07drm/msm/adreno: Switch to chip-id for identifying GPURob Clark
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549782/
2023-08-07dt-bindings: drm/msm/gpu: Extend bindings for chip-idRob Clark
Upcoming GPUs use an opaque chip-id for identifying the GPU. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/549778/
2023-08-07drm/msm/adreno: Move adreno info to configRob Clark
Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549777/
2023-08-07drm/msm/adreno: Add helper for formating chip-idRob Clark
This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549774/
2023-08-07drm/msm/adreno: Add adreno familyRob Clark
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549773/
2023-08-07drm/msm/adreno: Bring the a630 family togetherRob Clark
All of these are derivatives of a630. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549770/
2023-08-07drm/msm/adreno: Move speedbin mapping to device tableRob Clark
This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549769/
2023-08-07drm/msm/adreno: Allow SoC specific gpu device table entriesRob Clark
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549767/
2023-08-07drm/msm/adreno: Use quirk to identify cached-coherent supportRob Clark
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549765/
2023-08-07drm/msm/adreno: Use quirk identify hw_aprivRob Clark
Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549764/
2023-08-07drm/msm/adreno: Remove redundant revn paramRob Clark
This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549761/
2023-08-07drm/msm/adreno: Remove redundant gmem size paramRob Clark
Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549759/
2023-08-07drm/msm/adreno: Remove GPU nameRob Clark
No real need to have marketing names in the kernel. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549757/
2023-08-07Merge drm/drm-next into drm-intel-nextRodrigo Vivi
Catching-up with drm-next and drm-intel-gt-next. It will unblock a code refactor around the platform definitions (names vs acronyms). Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-08-07drm/amdgpu: Report vbios version instead of PNLijo Lazar
Report VBIOS version in vbios_version sysfs node instead of part number. Part number remains constant for a SKU type. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Promote DAL to 3.2.246Martin Leung
This version brings along following fixes: - Fix a regression in blank pixel data caused by coding mistake - Fix a bug when searching for insert_above_mpcc - Update add plane to context logic with a new algorithm - Adjust visual confirm dpp height offset to be 1/240 of v addressable - Add interface to enable DPIA trace - Support plane clip with zero recout size - Blocking invalid 420 modes on HDMI TMDS for DCN31 and DCN314 - Make mpc32 functions available to future DCNs - Change HDCP update sequence for DM Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Martin Leung <martin.leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Change HDCP update sequence for DMBhawanpreet Lakha
Refactor the sequence in hdcp_update_display() to use mod_hdcp_update_display(). Previous sequence: - remove()->add() This Sequence was used to update the display, (mod_hdcp_update_display didn't exist at the time). This meant for any hdcp updates (type changes, enable/disable) we would remove, reconstruct, and add. This leads to unnecessary calls to psp eventually New Sequence using mod_hdcp_update_display(): - add() once when stream is enabled - use update() for all updates The update function checks for prev == new states and will not unnecessarily end up calling psp via add/remove. Reviewed-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: rename acquire_idle_pipe_for_layer to ↵Wenjing Liu
acquire_free_pipe_as_sec_dpp_pipe [why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: move idle pipe allocation logic into dcn specific layerWenjing Liu
[why] generic dc resource file should not know what an optimal idle pipe is because this is dcn hardware dependent. [how] We move the optimial pipe searching logic in dcn specific layer. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Use max memclk variable when setting max memclkAlvin Lee
[Description] In overclocking scenarios the max memclk could be higher than the DC mode limit. However, for configs that don't support MCLK switching we need to set the max memclk to the overclocked max instead of the DC mode max or we could result in underflow. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Add vendor Id for referenceMike Hsieh
Add a new vendor ID code for reference Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mike Hsieh <mike.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN314Leo Chen
[Why & How] HDMI TMDS does not have ODM support. Filtering 420 modes that exceed the 4096 FMT limitation on DCN314 will resolve intermittent corruptions issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Blocking invalid 420 modes on HDMI TMDS for DCN31Leo Chen
[Why & How] HDMI TMDS does not have ODM support. Filtering 420 modes that exceed the 4096 FMT limitation on DCN31 will resolve intermittent corruptions issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-07drm/amd/display: Revert "drm/amd/display: Read down-spread percentage from ↵Leo Chen
lut to adjust dprefclk." [Why & How] Revert commit 6917b0b71171 ("drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.") This change was causing 240hz display to not light up after s0i3. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-17 11:09:57 +0000