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2025-03-06dt-bindings: soc: rockchip: Add RK3528 VPU GRF sysconYao Zi
Add compatible string for VPU GRF found on RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250305194217.47052-3-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-06dt-bindings: soc: rockchip: Add RK3528 VO GRF sysconYao Zi
Add compatible string for VO GRF found on RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250305194217.47052-2-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-06arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panelJulien Massot
The Radxa 8 HD touchscreen can be used with various Radxa board and is sold appart from the Radxa NIO 12L development kit. Add a DTS overlay for this panel. Signed-off-by: Julien Massot <julien.massot@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250304-radxa-panel-overlay-v2-2-3ee6797d3f86@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8395-nio-12l: Prepare MIPI DSI portJulien Massot
This board can use a MIPI-DSI panel on the DSI0 connector: in preparation for adding an overlay for the Radxa Display 8HD, add the backlight, and some definitions for pins available through the DSI0 port. Signed-off-by: Julien Massot <julien.massot@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250304-radxa-panel-overlay-v2-1-3ee6797d3f86@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8390-genio-common: Add delay codec for DMICNícolas F. R. A. Prado
The signal from the dual digital microphones connected to the DMIC_BE takes 30ms to settle after being enabled. Add a dmic-codec with corresponding wakeup-delay-ms to prevent an initial "pop" sound when recording with the microphones. Co-developed-by: Zoran Zhan <zoran.zhan@mediatek.com> Signed-off-by: Zoran Zhan <zoran.zhan@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250225-genio700-dmic-v2-8-3076f5b50ef7@collabora.com [Angelo: Resolved merge conflicts] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8390-genio-common: Add routes for DMICNícolas F. R. A. Prado
Add necessary routes for the onboard dual DMIC present on the Genio 700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs into the MT8188 DMIC DAI. Co-developed-by: parkeryang <Parker.Yang@mediatek.com> Signed-off-by: parkeryang <Parker.Yang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250225-genio700-dmic-v2-6-3076f5b50ef7@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipelineAngeloGioacchino Del Regno
This board can use a MIPI-DSI panel on the DSI0 connector: in preparation for adding an overlay for the Radxa Display 8HD, add a pipeline connecting VDOSYS0 components to DSI0. This pipeline remains disabled by default, as it is expected to be enabled only by a devicetree overlay that declares the actual DSI panel node, completing the graph. Link: https://lore.kernel.org/r/20250213112008.56394-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displaysAngeloGioacchino Del Regno
The base SoC devicetree now defines a display controller graph: connect the board specific outputs (eDP internal display, DP external display) to fully migrate Cherry and make it finally possible to make Chromebooks and other board types to coexist without per-board driver modifications. Link: https://lore.kernel.org/r/20250213112008.56394-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8195: Add base display controller graphAngeloGioacchino Del Regno
The display related IPs in MT8195 are flexible and support being interconnected with different instances of DDP IPs and/or with different DDP IPs, forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8195.dtsi devicetree, which is shared between all of the currently supported boards. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Link: https://lore.kernel.org/r/20250213112008.56394-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: airoha: en7581: Fix clock-controller addressLorenzo Bianconi
Fix the following warning for clock-controller node: DTC [C] arch/arm64/boot/dts/airoha/en7581-evb.dtb arch/arm64/boot/dts/airoha/en7581.dtsi:176.37-181.5: Warning (simple_bus_reg): /soc/clock-controller@1fa20000: simple-bus unit address format error, expected "1fb00000" Fixes: 7693017580e9 ("arm64: dts: airoha: en7581: Add Clock Controller node") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250221-en7581-dts-spi-pinctrl-v3-2-4719e2d01555@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation boardLorenzo Bianconi
Introduce the following nodes to EN7581 SoC and EN7581 evaluation board: - rng controller - pinctrl - i2c controllers Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250221-en7581-dts-spi-pinctrl-v3-1-4719e2d01555@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pinsAngeloGioacchino Del Regno
Add a pinctrl configuration for the Touchscreen IC's power line to make sure that the pin is configured as GPIO and to stop relying on correct pin configuration from bootloader. Link: https://lore.kernel.org/r/20250220110948.45596-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displaysAngeloGioacchino Del Regno
The base SoC devicetree now defines a display controller graph: connect the board specific outputs (eDP internal display, DP external display) to fully migrate Cherry and make it finally possible to make Chromebooks and other board types to coexist without per-board driver modifications. Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.) Link: https://lore.kernel.org/r/20250220110948.45596-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10Andy Yan
Enable vop and hdmi on rk3576 evb1, so we can get a display output on this board now. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250305025128.479245-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Enable hdmi display on sige5Andy Yan
Enable hdmi display on sige5 board. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-4-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add hdmi for rk3576Andy Yan
Add hdmi and it's phy dt node for rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add vop for rk3576Andy Yan
Add VOP and VOP_MMU found on rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boardsKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-2-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUSKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-1-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20CJonas Karlman
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard CH340B for debug console use. Add pinctrl for UART0 M0 pins used for serial console. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528Jonas Karlman
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node removed due to missing label reference to pcfg_output_low_pull_down. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04dt-bindings: soc: rockchip: Add RK3528 ioc grf sysconJonas Karlman
The GPIO is accessible via ioc grf syscon registers on RK3528. Add compatible string for RK3528 ioc grf syscon. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250228064024.3200000-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-03arm64: dts: apple: Add touchbar screen nodesSasha Finkelstein
Adds device tree entries for the touchbar screen Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Nick Chan <towinchenmi@gmail.com> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Link: https://lore.kernel.org/r/20250217-adpdrm-v7-4-ca2e44b3c7d8@gmail.com Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-03-03arm64: dts: corstone1000: Add definitions for secondary CPU coresHugues KAMBA MPIANA
Add cpu{1-3} device nodes to the corstone1000 device tree to enable the support for secondary CPU cores. This update facilitates symmetric multiprocessing (SMP) support on the corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores to be properly initialised and utilised. Only FVP platform will have SMP support and hence the secondary cpu definitions are not added to corstone1000.dtsi. Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com> (sudeep.holla: Added psci enable-method for cpu0) Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-28arm64: dts: rockchip: add usb typec host support to rk3588-jaguarHeiko Stuebner
Jaguar has two type-c ports connected to fusb302 controllers that can work both in host and device mode and can also run in display-port altmode. While these ports can work in dual-role data mode, they do not support powering the device itself as power-sink. This causes issues because the current infrastructure does not cope well with dual-role data without dual-role power. So add the necessary nodes for the type-c controllers as well as enable the relevant core usb nodes. So far host modes works reliably, but device-mode does not. So devicemode needs more investigation. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250228150853.329175-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-28arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588Sebastian Reichel
Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but gets disabled automatically when there are no users. This means the system might run into a failure state hanging the whole system for the following use cases: * if the GPU driver is being probed late (e.g. build as a module and firmware is not in initramfs), the regulator might already have been disabled. In that case the power domain is enabled before the regulator. * unbinding the GPU driver will disable the PM domain and the regulator. When the driver is bound again, the PM domain will be enabled before the regulator and error appears. Avoid this by adding an explicit regulator dependency to the power domain. Tested-by: Heiko Stuebner <heiko@sntech.de> Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com> Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 UltraJimmy Hon
HDMI audio is available on the Orange Pi 5 Ultra HDMI1 TX port. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-6-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 UltraJimmy Hon
Enable the only HDMI output port on the Orange Pi 5 Ultra Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-5-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add Orange Pi 5 Ultra boardJimmy Hon
The RK3588 Single Board Computer includes - eMMC - microSD - UART - 2 PWM LEDs - RTC - RTL8125 network controller on PCIe 2.0x1. - M.2 M-key connector routed to PCIe 3.0x4 - PWM controlled heat sink fan. - 2 USB2 ports - lower USB3 port - upper USB3 port with OTG capability - Mali GPU - SPI NOR flash - Mask Rom button - Analog audio using es8388 codec via the headset jack and onboard mic - HDMI1 - HDMI IN the vcc5v0_usb30 regulator shares the same enable gpio pin as the vcc5v0_usb20 regulator. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-4-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 UltraJimmy Hon
Add devicetree binding for the Xunlong Orange Pi 5 Ultra board. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250222193332.1761-3-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and UltraJimmy Hon
The Orange Pi 5 Plus and Orange Pi 5 Max have 2SK3018s attached to the PWM LEDs. The Orange Pi 5 Ultra does not, and thus needs the PWM polarity inverted. Also remove the model/compatible from the dtsi. It should be at the board level only. Fixes: c600d252dc52 ("arm64: dts: rockchip: Add Orange Pi 5 Max board") Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITXJianfeng Liu
Enable the HDMI port next to ethernet port. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5BDetlev Casanova
HDMI audio is available on the Rock 5B HDMI TX ports. Enable it for both ports. Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI audio outputs for rk3588Detlev Casanova
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node as CODEC and the i2s5 device as CPU. Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is i2s6, but only added in the rk3588-extra.dtsi device tree as the second TX HDMI port is not available on base versions of the SoC. The simple-audio-card,mclk-fs value is set to 128 as it is done in the downstream driver. The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so that they can be used as audio codec nodes. Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1Cristian Ciocaltea
Add the necessary DT changes to enable the second HDMI output port on Rockchip RK3588 EVB1. While at it, switch the position of &vop_mmu and @vop to maintain the alphabetical order. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-5-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588Cristian Ciocaltea
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. The HDMI1 PHY PLL clock source cannot be added directly to vop node in rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an optional feature and its PHY node belongs to a separate (extra) DT file. Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its clocks & clock-names properties in the extra DT file. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588Cristian Ciocaltea
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27MAINTAINERS: Add Vincenzo Frascino as Arm Morello MaintainerVincenzo Frascino
Add Vincenzo Frascino <vincenzo.frascino@arm.com> as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-11-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for fvp dtsVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for soc dtsVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-9-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for common functionalitiesVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-8-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm-pmu: Add support for ARM Rainier PMUVincenzo Frascino
Add support for the ARM Rainier CPU core PMU. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-6-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Rainier compatibilityVincenzo Frascino
The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-5-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Morello fvp compatibilityVincenzo Frascino
Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-4-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Morello compatibilityVincenzo Frascino
Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-3-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESSVincenzo Frascino
Update the description and contextually the help text of CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-26arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4BAndy Yan
Enable USB3 OTG and it's related PHY node. And the PHY will also be shared with the upcoming DisplayPort controller. Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250223100757.73531-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add UART clocks for RK3528 SoCYao Zi
Add missing clocks in UART nodes for RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add clock generators for RK3528 SoCYao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64Heiko Stuebner
generated by cgit (git 2.34.1) at 2025-09-28 22:37:40 +0000