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2019-02-08dt-bindings: interrupt-controller: update bindings for MT7623Ryder Lee
This adds missing bindings for MT7623 sysirq. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-08arm64: dts: renesas: cat875: Enable PCIe supportBiju Das
This patch enables PCIEC0 PCI express controller on the sub board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0-cat874: Add pciec0 supportBiju Das
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the CAT874 main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add TMU device nodesBiju Das
This patch adds TMU{0|1|2|3|4} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add CMT device nodesBiju Das
This patch adds CMT{0|1|2|3} device nodes for r8a774c0 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devicesFabrizio Castro
This patch defines OOP tables for all CPUs, similarly to what done by Takeshi Kihara and Yoshihiro Kaneko for the R8A77990. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: r8a77990: Add OPPs table for cpu devicesTakeshi Kihara
This patch define OOP tables for all CPUs. This allows CPUFreq to function. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08arm64: dts: renesas: enable HS400 on R-Car Gen3Niklas Söderlund
Successfully tested on H3 ES2.0 and M3-N ES1.0. Transfer rates where >160MB/s for H3 and >200MB/s for M3-N. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08ARM: dts: r8a7744: Add LVDS supportBiju Das
Add LVDS encoder node to r8a7744 SoC DT. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-08ARM: dts: r8a7744: Add DU supportBiju Das
Add du node to r8a7744 SoC DT. Boards that want to enable the DU need to specify the output topology. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-02-07arm64: dts: sdm845: Add clocks and iommus to WCN3990 WLAN nodeDouglas Anderson
When commit 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") was posted upstream no clocks were specified. However, when the pack was picked into the Chrome OS kernel tree (allegedly directly from the mailing list post) it had clock properties. I presume that the clock should be there, so let's add it. Fixes: 022bccb840b7 ("dts: arm64/sdm845: Add WCN3990 WLAN module device node") Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> [bjorn: Add also the required iommus property] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-07arm64: dts: meson: g12a: add clk measure supportJerome Brunet
Add the clock measure device to the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-07arm64: dts: meson: axg: add clk measure supportJerome Brunet
Add the clock measure device to the axg SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-07arm64: tegra: Update compatible for Tegra186 I2CSowjanya Komatineni
Update I2C Device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Update compatible for Tegra210 I2CSowjanya Komatineni
Update I2C device node compatible string to be appropriate. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Support 200 MHz for SDMMC on Tegra194Sowjanya Komatineni
Change the SDMMC clock source to support a maximum frequency of 200 MHz on Tegra194. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CQE Support for SDMMC4Sowjanya Komatineni
Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add SDMMC auto-calibration settingsSowjanya Komatineni
Add SDMMC initial pad offsets used by auto calibration process. Add SDMMC fixed drive strengths for Tegra210, Tegra186 and Tegra194 which are used when calibration timeouts. Fixed drive strengths are based on Pre SI Analysis of the pads. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888Mikko Perttunen
The Tegra Combined UART is the proper primary serial port on P2888, so use it. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add nodes for TCU on Tegra194Mikko Perttunen
Add nodes required for communication through the Tegra Combined UART. This includes the AON HSP instance, addition of shared interrupts for the TOP0 HSP instance, and finally the TCU node itself. Also mark the HSP instances as compatible to tegra194-hsp, as the hardware is not identical but is compatible to tegra186-hsp. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Enable DFLL clock on SmaugJoseph Lo
Enable DFLL clock for Smaug board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CPU power rail regulator on SmaugJoseph Lo
Add CPU power rail regulator for Smaug board. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Enable DFLL clock on Jetson TX1Joseph Lo
Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add pinmux for PWM-based DFLL support on P2597Joseph Lo
Add pinmux for PWM-based DFLL support. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add CPU clocks on Tegra210Joseph Lo
Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07arm64: tegra: Add DFLL clock on Tegra210Joseph Lo
Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07ARM: dts: gta04: add gps supportAndreas Kemnade
The GTA04 has a w2sg0004 or w2sg0084 gps chip. Not detectable which one is mounted so use the compatibility entry for w2sg0004 for all which will work for both. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: gta04: add ldo 3v3 regulatorAndreas Kemnade
Required for completeness sake to be able to specify a regulator for devices having a non-optional regulator property. It corresponds to the "3V3" net in the schematics. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: gta04: add pinctrl settings for wkup domainAndreas Kemnade
There is one button and a notifier for incoming phone calls/text messages for which we should wakeup from suspend. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07ARM: dts: omap3-gta04a5: Replace LXR reference with a local oneJonathan Neuschäfer
There's no need to use an external link when the file is already here. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-07dt-bindings: arm: mediatek: add support for MT7622 BPI-R64 and MT7629 RFBRyder Lee
Update binding document for MT7622 BPI-R64 and MT7629 reference board. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-07dt-bindings: arm: mediatek: remove unused "mediatek, mt7623a"Ryder Lee
As we fallback to use "mediatek,mt7623" for MT7623a, remove unused root node property "mediatek,mt7623a" in the document. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-07ARM: dts: sun8i: a83t: Enable PMIC power supplies on various boardsChen-Yu Tsai
On the Bananapi M3 and Cubietruck Plus, the DC input jacks are wired to the ACIN pins, which is represented by the AC power supply. Both boards have connectors for LiPo batteries, which are represented by the battery power supply. The H8 Homlet is a set-top box design. The DC input jack is wired to the ACIN pins, but there are no battery connectors. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: cubieboard4: Enable GMACChen-Yu Tsai
The Cubieboard4 has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: a80-optimus: Enable GMACChen-Yu Tsai
The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's core logic and gpio1-ldo for I/O. The latter also powers the SoC side pins. As there is no binding to model a second regulator supply for the PHY, it is omitted. It is however properly modeled for the PIO. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add A80 GMAC RGMII pinmux settingChen-Yu Tsai
The GMAC (gigabit ethernet controller) supports RGMII to connect to the ethernet PHY, for gigabit network speeds. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller nodeChen-Yu Tsai
The A80 has the same GMAC found on the A31 SoC. Add a device node, and an alias for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: Add GMAC clock nodeChen-Yu Tsai
The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The accompanying GMAC clock register has been moved into the "System Control" area. Add a clock node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator suppliesChen-Yu Tsai
The Cubieboard 4 has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator suppliesChen-Yu Tsai
The A80 Optimus has the PMIC providing voltage to all the pin-bank supply rails from its various regulator outputs. All pin-banks that have supply rails are accounted for. PN pin-bank does not have a supply rail. Also remove any "regulator-always-on" properties from regulators that were only marked to provide pin-bank power. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulatorChen-Yu Tsai
The DC1SW output from the AXP809 is unused. Unused regulators should still be listed so as to be considered to be fully constrained. Fixes: aa4a27bc819e ("ARM: dts: sun9i: a80-optimus: Add AXP809 PMIC device node and regulators") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-07dt-bindings: arm: Add bindings for Mediatek MT8183 SoC PlatformErin Lo
This adds dt-binding documentation of cpu for Mediatek MT8183. Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-02-06arm64: dts: meson: fix g12a busesJerome Brunet
Fix apb, cbus, hiu and periph regions which are not aligned with the documentation and the information provided by Amlogic Fixes: 9c8c52f7cb4f ("arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support") Cc: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-06arm64: dts: qcom: sdm845: Define iommus for USB controllersBjorn Andersson
The USB controllers need to be associated with their respective IOMMU bank, so define this on the dwc3 nodes. Also add dma-ranges to the qcom-dwc3 nodes to make the bus' DMA mask propagate to the dwc3 controller instances. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2Bjorn Andersson
With apps_smmu initializing the SMMU we must specify iommus property for the sdhc controller. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: sdm845: wireup the thermal trip points to cpufreqAmit Kucheria
Since all cpus in the big and little clusters, respectively, are in the same frequency domain, use all of them for mitigation in the cooling-map. We end up with two cooling devices - one each for the big and little clusters. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: msm8916: remove bogus argument to the cpu clockNiklas Cassel
The apcs node has #clock-cells = <0>, which means that those who references it should specify 0 arguments. The apcs reference in the cpu node incorrectly specifies an argument, remove this bogus argument. Fixes: 65afdf458360 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required propertiesJoseph Lo
The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required propertiesJoseph Lo
The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06dt-bindings: clock: tegra124-dfll: add Tegra210 supportJoseph Lo
Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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