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2019-01-25arm64: dts: zcu100-revC: Give wifi some time after power-onJan Kiszka
Somewhere along recent changes to power control of the wl1831, power-on became very unreliable on the Ultra96, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, Ultra96 is already happy with 10 ms. Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-25arm64: tegra: Add regulators for Tegra210 DarcyMark Zhang
Add regulators to the Tegra210 Darcy DTS file including support for the MAX77620 PMIC. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Add pinmux for Darcy boardMark Zhang
Add pinmux node for Tegra210 Darcy board. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Add gpio-keys nodes for DarcyMark Zhang
Add gpio-keys nodes for the power button. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Add support for NVIDIA Shield TVMark Zhang
Add initial device-tree support for NVIDIA Shield TV (a.k.a. Darcy) based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Use GIC_SPI for PMIC interrupt on SmaugThierry Reding
Instead of hardcoding the value (0), reuse the symbolic name from dt-bindings/interrupt-controller/arm-gic.h. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25dt-bindings: tegra: Add Shield TV device tree binding documentationMark Zhang
Add the device tree binding documentation for NVIDIA Shield TV. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Fix IRQ type of PMIC on SmaugJoseph Lo
Fix IRQ type of PMIC which should be configured as high-level trigger. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Fix register range of apbmisc on Tegra210Joseph Lo
Fix the register range of apbmisc, that originally inherited from Tegra124. Reported-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25arm64: tegra: Remove property gpio-keys,nameMark Zhang
gpio-keys,name is not a valid property supported by gpio-keys driver so remove it from DTS. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25ARM: dts: sun8i-a23-q8: Set compatible string for LCD panelChen-Yu Tsai
The Q8 tablets follow the A23/A33 tablet reference design, and normally use a "generic" 800x480 LCD panel. The actual panel may vary between production runs, and there are no visible markings denoting its model. This patch uses a panel that has the same dimensions and timings that are close to what was provided in the vendor fex files. Since there are also A33 Q8 tablets with 1024x600 panels, this patch only sets the compatible string for A23 Q8 tablets. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panelChen-Yu Tsai
The Q8 design for A23/A33 tablets have an 18-bit RGB LCD panel connected to the LCD interface on the SoC, the DC1SW output on the PMIC providing power for the LCD, and PH7 toggling the reset pin for the panel. This patch adds a device node for the panel, describing the above, and enables the display pipeline. The actual model or compatible string for the panel should be added in the tablet device tree file. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodesChen-Yu Tsai
Now that the compatible strings for the display pipeline on the A23 have been added to the bindings, add the corresponding compatibles to the device nodes already in the A23/A33 shared dtsi. While the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). Hence the ch1 clock is left out. As the MIPI DSI output device is not officially documented, and there are no reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsiChen-Yu Tsai
The display pipeline has the same structure, resources and connections on both the A23 and A33. The differences include: - compatible strings - extra clock, reset control, and IO region for SAT in the backend only found on the A33 - missing ch1 clock for the TCON However, while the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by addressChen-Yu Tsai
The NAND controller device node was inserted into the wrong position, probably due to a rebase or merge, as the file's structure does not provide enough context for git to accurately match the previous device node block. Fixes: d7b843df13ea ("ARM: dts: sun8i: add NAND controller node for A23/A33") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25cfg80211: extend range deviation for DMGChaitanya Tata
Recently, DMG frequency bands have been extended till 71GHz, so extend the range check till 20GHz (45-71GHZ), else some channels will be marked as disabled. Signed-off-by: Chaitanya Tata <Chaitanya.Tata@bluwireless.co.uk> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-01-25cfg80211: reg: remove warn_on for a normal caseChaitanya Tata
If there are simulatenous queries of regdb, then there might be a case where multiple queries can trigger request_firmware_no_wait and can have parallel callbacks being executed asynchronously. In this scenario we might hit the WARN_ON. So remove the warn_on, as the code already handles multiple callbacks gracefully. Signed-off-by: Chaitanya Tata <chaitanya.tata@bluwireless.co.uk> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-01-25mac80211: Add attribute aligned(2) to struct 'action'Mathieu Malaterre
During refactor in commit 9e478066eae4 ("mac80211: fix MU-MIMO follow-MAC mode") a new struct 'action' was declared with packed attribute as: struct { struct ieee80211_hdr_3addr hdr; u8 category; u8 action_code; } __packed action; But since struct 'ieee80211_hdr_3addr' is declared with an aligned keyword as: struct ieee80211_hdr { __le16 frame_control; __le16 duration_id; u8 addr1[ETH_ALEN]; u8 addr2[ETH_ALEN]; u8 addr3[ETH_ALEN]; __le16 seq_ctrl; u8 addr4[ETH_ALEN]; } __packed __aligned(2); Solve the ambiguity of placing aligned structure in a packed one by adding the aligned(2) attribute to struct 'action'. This removes the following warning (W=1): net/mac80211/rx.c:234:2: warning: alignment 1 of 'struct <anonymous>' is less than 2 [-Wpacked-not-aligned] Cc: Johannes Berg <johannes.berg@intel.com> Suggested-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Mathieu Malaterre <malat@debian.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-01-25mac80211: don't initiate TDLS connection if station is not associated to APBalaji Pothunoori
Following call trace is observed while adding TDLS peer entry in driver during TDLS setup. Call Trace: [<c1301476>] dump_stack+0x47/0x61 [<c10537d2>] __warn+0xe2/0x100 [<fa22415f>] ? sta_apply_parameters+0x49f/0x550 [mac80211] [<c1053895>] warn_slowpath_null+0x25/0x30 [<fa22415f>] sta_apply_parameters+0x49f/0x550 [mac80211] [<fa20ad42>] ? sta_info_alloc+0x1c2/0x450 [mac80211] [<fa224623>] ieee80211_add_station+0xe3/0x160 [mac80211] [<c1876fe3>] nl80211_new_station+0x273/0x420 [<c170f6d9>] genl_rcv_msg+0x219/0x3c0 [<c170f4c0>] ? genl_rcv+0x30/0x30 [<c170ee7e>] netlink_rcv_skb+0x8e/0xb0 [<c170f4ac>] genl_rcv+0x1c/0x30 [<c170e8aa>] netlink_unicast+0x13a/0x1d0 [<c170ec18>] netlink_sendmsg+0x2d8/0x390 [<c16c5acd>] sock_sendmsg+0x2d/0x40 [<c16c6369>] ___sys_sendmsg+0x1d9/0x1e0 Fixing this by allowing TDLS setup request only when we have completed association. Signed-off-by: Balaji Pothunoori <bpothuno@codeaurora.org> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-01-25nl80211: fix NLA_POLICY_NESTED() argumentsJohannes Berg
syzbot reported an out-of-bounds read when passing certain malformed messages into nl80211. The specific place where this happened isn't interesting, the problem is that nested policy parsing was referring to the wrong maximum attribute and thus the policy wasn't long enough. Fix this by referring to the correct attribute. Since this is really not necessary, I'll come up with a separate patch to just pass the policy instead of both, in the common case we can infer the maxattr from the size of the policy array. Reported-by: syzbot+4157b036c5f4713b1f2f@syzkaller.appspotmail.com Cc: stable@vger.kernel.org Fixes: 9bb7e0f24e7e ("cfg80211: add peer measurement with FTM initiator API") Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2019-01-24ibmveth: Do not process frames after calling napi_rescheduleThomas Falcon
The IBM virtual ethernet driver's polling function continues to process frames after rescheduling NAPI, resulting in a warning if it exhausted its budget. Do not restart polling after calling napi_reschedule. Instead let frames be processed in the following instance. Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24net: dev_is_mac_header_xmit() true for ARPHRD_RAWIPMaciej Żenczykowski
__bpf_redirect() and act_mirred checks this boolean to determine whether to prefix an ethernet header. Signed-off-by: Maciej Żenczykowski <maze@google.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24net: usb: asix: ax88772_bind return error when hw_reset failZhang Run
The ax88772_bind() should return error code immediately when the PHY was not reset properly through ax88772a_hw_reset(). Otherwise, The asix_get_phyid() will block when get the PHY Identifier from the PHYSID1 MII registers through asix_mdio_read() due to the PHY isn't ready. Furthermore, it will produce a lot of error message cause system crash.As follows: asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to write reg index 0x0000: -71 asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to send software reset: ffffffb9 asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to write reg index 0x0000: -71 asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to enable software MII access asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to read reg index 0x0000: -71 asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to write reg index 0x0000: -71 asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to enable software MII access asix 1-1:1.0 (unnamed net_device) (uninitialized): Failed to read reg index 0x0000: -71 ... Signed-off-by: Zhang Run <zhang.run@zte.com.cn> Reviewed-by: Yang Wei <yang.wei9@zte.com.cn> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24MAINTAINERS: Update cavium networking driversSudarsana Reddy Kalluru
Following Marvell's acquisition of Cavium, we need to update all the Cavium drivers maintainer's entries to point to our new e-mail addresses. Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com> Signed-off-by: Ameen Rahman <Ameen.Rahman@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24Merge tag 'hyperv-fixes-signed' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux Sasha Levin says: ==================== Hyper-V hv_netvsc commits for 5.0 Three patches from Haiyang Zhang to fix settings hash key using ethtool, and Adrian Vladu's first patch fixing a few spelling mistakes. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24Merge tag 'linux-can-fixes-for-5.0-20190122' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can Marc Kleine-Budde says: ==================== pull-request: can 2019-01-22 this is a pull request of 4 patches for net/master. The first patch by is by Manfred Schlaegl and reverts a patch that caused wrong warning messages in certain use cases. The next patch is by Oliver Hartkopp for the bcm that adds sanity checks for the timer value before using it to detect potential interger overflows. The last two patches are for the flexcan driver, YueHaibing's patch fixes the the return value in the error path of the flexcan_setup_stop_mode() function. The second patch is by Uwe Kleine-König and fixes a NULL pointer deref on older flexcan cores in flexcan_chip_start(). ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24Merge branch 'mlx4_core-fixes'David S. Miller
Tariq Toukan says: ==================== mlx4_core fixes for 5.0-rc This patchset includes two fixes for the mlx4_core driver. First patch by Aya fixes inaccurate parsing of some FW fields, mistakenly including additional (mostly reserved) bits. Second patch by Jack fixes a wrong (yet harmless) error handling of calls to copy_to_user() during the CQs init stage. Series generated against net commit: 49a57857aeea Linux 5.0-rc3 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24net/mlx4_core: Fix error handling when initializing CQ bufs in the driverJack Morgenstein
Procedure mlx4_init_user_cqes() handles returns by copy_to_user incorrectly. copy_to_user() returns the number of bytes not copied. Thus, a non-zero return should be treated as a -EFAULT error (as is done elsewhere in the kernel). However, mlx4_init_user_cqes() error handling simply returns the number of bytes not copied (instead of -EFAULT). Note, though, that this is a harmless bug: procedure mlx4_alloc_cq() (which is the only caller of mlx4_init_user_cqes()) treats any non-zero return as an error, but that returned error value is processed internally, and not passed further up the call stack. In addition, fixes the following sparse warning: warning: incorrect type in argument 1 (different address spaces) expected void [noderef] <asn:1>*to got void *buf Fixes: e45678973dcb ("{net, IB}/mlx4: Initialize CQ buffers in the driver when possible") Reported by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24net/mlx4_core: Add masking for a few queries on HCA capsAya Levin
Driver reads the query HCA capabilities without the corresponding masks. Without the correct masks, the base addresses of the queues are unaligned. In addition some reserved bits were wrongly read. Using the correct masks, ensures alignment of the base addresses and allows future firmware versions safe use of the reserved bits. Fixes: ab9c17a009ee ("mlx4_core: Modify driver initialization flow to accommodate SRIOV for Ethernet") Fixes: 0ff1fb654bec ("{NET, IB}/mlx4: Add device managed flow steering firmware API") Signed-off-by: Aya Levin <ayal@mellanox.com> Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-24arm64: dts: qcom: qcs404: Add QUP I2C and SPI nodesBjorn Andersson
Define all six QUP controllers, both as SPI and I2C, allowing boards to enable these as needed. Associated pinmux states are also defined, to require only pinconf states to be specified by the boards, as they are enabled. Note that SPI has not been tested. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: qcs404: Define remaining UARTsBjorn Andersson
Add the BLSP2 BAM and add the remaining four UARTs found on the QCS404 platform. Note that these has not been tested. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: qcs404: Specify pinctrl state for UARTBjorn Andersson
BLSP1 UART2 is used as debug uart on the EVB development board, define pinmux state for the UART in the platform dtsi and pinconf state for it in the board dts. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Fix lpasscc regBjorn Andersson
Fix up the lpasscc address and size, missed during the conversion to address- and size-cells of 2. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Remove the duplicate header inclusionSai Prakash Ranjan
Remove the duplicate inclusion of qcom,gcc-sdm845.h mistakenly introduced by commit 6e17f8140521 ("arm64: dts: sdm845: add prng-ee node"). Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> [bjorn: Also fix sort order of lpasscc include, while we're there] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add reserve-memory nodesSibi Sankar
Add reserve-memory nodes for mpss and mba required for remoteproc mss pil. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM nodeEvan Green
Add the gpio-ranges property to the TLMM node so that GPIO hogs work. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Extend ranges and describe DMA spaceBjorn Andersson
For devices attached to an IOMMU, translation between IOVA and physical addresses is no longer 1:1 and dma-ranges should be specified to describe the available IOVA address space. On SDM845 the busses are implemented with 36 address bits, so dma-ranges must be defined to reduce the size of the IOVA address space from the 48 bits supported by the SMMU. Without this DMA allocations may end up with IOVAs outside the valid range, that gets truncated by the bus between the device and its translation unit. Also extend ranges to describe the available address space. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Increase address and size cells for socBjorn Andersson
The busses on SDM845 provides 36 address bits, extend the address and size cells to make it possible to describe this in "ranges" and "dma-ranges". While touching all reg properties, addresses are padded to 8 digits. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add rpmh powercontroller nodeRajendra Nayak
Add the DT node for the rpmhpd powercontroller. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: msm8996: Add rpmpd device nodeRajendra Nayak
Add rpmpd device node and its OPP table Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add WCN3990 WLAN module device nodeGovind Singh
Add device node for the ath10k SNOC platform driver probe and add resources required for WCN3990 on SDM845 soc. Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add PDC Global reset driver nodeSibi Sankar
This patch adds the node to support PDC Global reset driver on SDM845 SoCs Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add SCM DT nodeSibi Sankar
Add SCM DT node to enable SCM functionality on SDM845. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Fix pcs_misc region address for UNI PHYManu Gautam
Correct address for pcs_misc register region of USB3 QMP UNI PHY. These registers are used during runtime-suspend/resume routines of phy. Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: ca4db2b538a1 ("arm64: dts: qcom: sdm845: Add USB-related nodes") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add lpasscc nodeTaniya Das
This adds the low pass audio clock controller node to sdm845 based on the example in the bindings. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [bjorn: Disabled lpasscc node, as it's normally protected] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add videocc nodeTaniya Das
This adds the video clock controller node to sdm845 based on the examples in the bindings. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: sdm845: Add gpu clock controller nodeDouglas Anderson
Add the GPU clock controller nodes as per the example. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: sdm845: Add qspi (quad SPI) nodeDouglas Anderson
This adds the Quad SPI controller to the main sdm845 device tree file. Boards will be expected to assign the proper pinctrl depending on how many chip selects they have hooked up and how many data lines. This depends on commit 48735597f7bd ("clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header") to add the needed defines. It also shouldn't land until the patch ("dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation") [1] lands. [1] https://lkml.kernel.org/r/20181002214709.162330-1-ryandcase@chromium.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: msm8998: Enumerate i2c controllersJeffrey Hugo
msm8998 has a dozen i2c controllers which can be used to connect to board specific peripherals. Enumerate the controllers so that boards can wire up as needed. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> [bjorn: Renumbered labels on BLSP2 nodes] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-24arm64: dts: qcom: msm8998-mtp: Increase load on l21 for sdcardJeffrey Hugo
l21 is used as sdcard vmmc, and needs the load increased to prevent voltage drop issues with some sdcards. This addresses -84 errors seen during sdcard init with SDR104 cards. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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