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2019-05-13Merge branch 'pci/dwc'Bjorn Helgaas
- Use generic config space reader in qcom (Marc Gonzalez) - Stop calling IRQ handler cleanup in dwc driver for invalid MSI IRQs (Jisheng Zhang) - Free dwc MSI target page when freeing MSI (Jisheng Zhang) - Fix dwc MSI leak in host init error path (Jisheng Zhang) - Use managed host bridge alloc to simplify dwc (Jisheng Zhang) - Save dwc root pci_bus pointer for use by .remove() methods (Jisheng Zhang) - Allow imx6 asynchronous probing (Lucas Stach) * pci/dwc: PCI: imx6: Allow asynchronous probing PCI: dwc: Save root bus for driver remove hooks PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code PCI: dwc: Free MSI in dw_pcie_host_init() error path PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi() PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid PCI: qcom: Use default config space read function
2019-05-13Merge branch 'remotes/lorenzo/pci/controller-fixes'Bjorn Helgaas
- Restore R-Car PCIe link early in resume (Kazufumi Ikeda) - Fix Hyper-V PCI ejection memory leak (Dexuan Cui) - Cleanup Hyper-V PCI slots on module unload (Dexuan Cui) - Cleanup Hyper-V PCI slot on device removal to address a race (Dexuan Cui) * remotes/lorenzo/pci/controller-fixes: PCI: hv: Add pci_destroy_slot() in pci_devices_present_work(), if necessary PCI: hv: Add hv_pci_remove_slots() when we unload the driver PCI: hv: Fix a memory leak in hv_eject_device_work() PCI: rcar: Add the initialization of PCIe link in resume_noirq()
2019-05-13Merge branch 'pci/host/al'Bjorn Helgaas
- Add Amazon Annapurna Labs PCIe host controller driver (Jonathan Chocron) * pci/host/al: PCI: al: Add Amazon Annapurna Labs PCIe host controller driver
2019-05-13Merge branch 'pci/virtualization'Bjorn Helgaas
- Mark ATS on AMD Stoney Radeon R7 GPU broken to avoid IOMMU issues (Nikolai Kostrigin) - Mark Atheros AR9462 to avoid bus reset that locks up host machine (James Prestwood) * pci/virtualization: PCI: Mark Atheros AR9462 to avoid bus reset PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken
2019-05-13Merge branch 'pci/switchtec'Bjorn Helgaas
- Support all 255 PFF ports in switchtec driver (Wesley Sheng) - Fix unintentional switchtec MRPC event masking that degraded firmware update speed (Wesley Sheng) * pci/switchtec: switchtec: Fix unintended mask of MRPC event switchtec: Increase PFF limit from 48 to 255
2019-05-13Merge branch 'pci/portdrv'Bjorn Helgaas
- Disable Link Management interrupt during suspend to prevent immediate wakeup (Mika Westerberg) * pci/portdrv: PCI/LINK: Disable bandwidth notification interrupt during suspend
2019-05-13Merge branch 'pci/peer-to-peer'Bjorn Helgaas
- Add a whitelist of Root Complexes known to support peer-to-peer DMA between Root Ports (Christian König) * pci/peer-to-peer: PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex
2019-05-13Merge branch 'pci/misc'Bjorn Helgaas
- Mark expected switch fall-throughs (Gustavo A. R. Silva) - Remove unused pci_request_region_exclusive() (Johannes Thumshirn) - Fix x86 PCI IRQ routing table memory leak (Wenwen Wang) - Reset Lenovo ThinkPad P50 if firmware didn't do it on reboot (Lyude Paul) - Add and use pci_dev_id() helper to simplify PCI_DEVID() usage (touches several places outside drivers/pci/) (Heiner Kallweit) - Transition Mobiveil PCI maintenance to Karthikeyan M and Hou Zhiqiang (Subrahmanya Lingappa) * pci/misc: MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI platform/chrome: chromeos_laptop: use pci_dev_id() helper stmmac: pci: Use pci_dev_id() helper iommu/vt-d: Use pci_dev_id() helper iommu/amd: Use pci_dev_id() helper drm/amdkfd: Use pci_dev_id() helper powerpc/powernv/npu: Use pci_dev_id() helper r8169: use pci_dev_id() helper PCI: Add pci_dev_id() helper PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary x86/PCI: Fix PCI IRQ routing table memory leak PCI: Remove unused pci_request_region_exclusive() PCI: Mark expected switch fall-throughs
2019-05-13Merge branch 'pci/msi'Bjorn Helgaas
- Remove unused mask_msi_irq(), unmask_msi_irq(), write_msi_msg(), __write_msi_msg() (Bjorn Helgaas) * pci/msi: PCI/MSI: Remove unused mask_msi_irq() and unmask_msi_irq() PCI/MSI: Remove unused __write_msi_msg() and write_msi_msg()
2019-05-13Merge branch 'pci/hotplug'Bjorn Helgaas
- Fix RPA and RPA DLPAR refcount issues (Tyrel Datwyler) - Stop exporting pci_get_hp_params() (Alexandru Gagniuc) - Simplify _HPP, _HPX parsing (Alexandru Gagniuc) - Add support for _HPX Type 3 settings (Alexandru Gagniuc) - Tell firmware we support _HPX Type 3 via _OSC (Alexandru Gagniuc) * pci/hotplug: PCI/ACPI: Advertise _HPX Type 3 support via _OSC PCI/ACPI: Implement _HPX Type 3 Setting Record PCI/ACPI: Remove the need for 'struct hotplug_params' PCI/ACPI: Do not export pci_get_hp_params() PCI: rpaphp: Get/put device node reference during slot alloc/dealloc PCI: rpadlpar: Fix leaked device_node references in add/remove paths
2019-05-13Merge branch 'pci/enumeration'Bjorn Helgaas
- Enable PCIe services for host controller drivers that use managed host bridge alloc (Jean-Philippe Brucker) - Add quirk to clear PCIe Retrain Link bit to work around Pericom bridge erratum (Stefan Mätje) - Add "external-facing" DT property to identify cases where we require IOMMU protection from untrusted devices (Jean-Philippe Brucker) - Support fixed bus numbers from bridge Enhanced Allocation capabilities (Subbaraya Sundeep) * pci/enumeration: PCI: Assign bus numbers present in EA capability for bridges PCI: OF: Support "external-facing" property dt-bindings: Add "external-facing" PCIe port property PCI: Rework pcie_retrain_link() wait loop PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratum PCI: Factor out pcie_retrain_link() function PCI: Init PCIe feature bits for managed host bridge alloc
2019-05-13Merge branch 'pci/aer'Bjorn Helgaas
- Fix pci_aer_init() stub prototype for non-CONFIG_PCIEAER case (Jisheng Zhang) * pci/aer: PCI/AER: Change pci_aer_init() stub to return void
2019-05-13MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCISubrahmanya Lingappa
Add Karthikeyan Mitran and Hou Zhiqiang as new maintainers of Mobiveil controller driver. Link: https://lore.kernel.org/linux-pci/1557229516-6870-1-git-send-email-l.subrahmanya@mobiveil.co.in Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> [bhelgaas: update names/email addresses to match usage in git history] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
2019-05-07PCI: imx6: Allow asynchronous probingLucas Stach
Establishing a PCIe link can take a while; allow asynchronous probing so that link establishment can happen in the background while other devices are being probed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-05-07PCI: dwc: Save root bus for driver remove hooksJisheng Zhang
Currently DWC host does not support the remove callback, but nothing prevents us from supporting it. Save the root bus for clean up work in driver remove code paths to allow DWC host drivers to implement their remove hook as, eg: static int foo_pcie_remove(struct platform_device *pdev) { ... pci_stop_root_bus(pp->root_bus); pci_remove_root_bus(pp->root_bus); dw_pcie_free_msi(pp); ... } Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify codeJisheng Zhang
Use devm_pci_alloc_host_bridge() to simplify the error code path. This also fixes a leak in the dw_pcie_host_init() error path. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> CC: stable@vger.kernel.org # v4.13+
2019-05-07PCI: dwc: Free MSI in dw_pcie_host_init() error pathJisheng Zhang
If we ever did MSI-related initializations, we need to call dw_pcie_free_msi() in the error code path. Remove the IS_ENABLED(CONFIG_PCI_MSI) check for MSI init because pci_msi_enabled() already has a stub for !CONFIG_PCI_MSI. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()Jisheng Zhang
To avoid a memory leak, free the page allocated for MSI IRQ in dw_pcie_free_msi(). Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalidJisheng Zhang
Check msi_irq variable before calling irq_set_chained_handler() and irq_set_handler_data(), lest we call those functions for an invalid MSI IRQ. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: qcom: Use default config space read functionMarc Gonzalez
Move the device class fudge to a proper fixup function, and remove qcom_pcie_rd_own_conf() which has become useless. dw_pcie_setup_rc() already did the right thing, but it's broken on older qcom chips, such as 8064. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2019-05-01PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root ComplexChristian König
The PCI specs say that peer-to-peer DMA should be supported between any two devices that have a common upstream PCI-to-PCI bridge. But devices under different Root Ports don't share a common upstream bridge, and PCIe r4.0, sec 1.3.1, says routing peer-to-peer transactions between Root Ports in the same Root Complex is optional. Many Root Complexes, including AMD ZEN, *do* support peer-to-peer DMA even between Root Ports. Add a whitelist and allow peer-to-peer DMA if both participants are attached to a Root Complex known to support it. Link: https://lore.kernel.org/linux-pci/20190418115859.2394-1-christian.koenig@amd.com Signed-off-by: Christian König <christian.koenig@amd.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2019-04-29platform/chrome: chromeos_laptop: use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Benson Leung <bleung@chromium.org>
2019-04-29stmmac: pci: Use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-29iommu/vt-d: Use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
2019-04-29iommu/amd: Use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
2019-04-29drm/amdkfd: Use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Christian König <christian.koenig@amd.com>
2019-04-29powerpc/powernv/npu: Use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2019-04-29r8169: use pci_dev_id() helperHeiner Kallweit
Use new helper pci_dev_id() to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David S. Miller <davem@davemloft.net>
2019-04-29PCI: Add pci_dev_id() helperHeiner Kallweit
In several places in the kernel we find PCI_DEVID used like this: PCI_DEVID(dev->bus->number, dev->devfn) Add a "pci_dev_id(struct pci_dev *dev)" helper to simplify callers. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-25PCI: al: Add Amazon Annapurna Labs PCIe host controller driverJonathan Chocron
Add driver for Amazon's Annapurna Labs PCIe host controller. The controller is based on DesignWare's IP. The controller doesn't support accessing the Root Port's config space via ECAM, so we obtain its base address via an AMZN0001 device. Furthermore, the DesignWare PCIe controller doesn't filter out config transactions sent to devices 1 and up on its bus, so they are filtered by the driver. All subordinate buses do support ECAM access. Implementing specific PCI config access functions involves: - Adding an init function to obtain the Root Port's base address from an AMZN0001 device. - Adding a new entry in the MCFG quirk array. [bhelgaas: Note that there is no Kconfig option for this driver because it is only intended for use with the generic ACPI host bridge driver. This driver is only needed because the DesignWare IP doesn't completely support ECAM access to the root bus.] Link: https://lore.kernel.org/lkml/1553774276-24675-1-git-send-email-jonnyc@amazon.com Co-developed-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-25PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessaryLyude Paul
On ThinkPad P50 SKUs with an Nvidia Quadro M1000M instead of the M2000M variant, the BIOS does not always reset the secondary Nvidia GPU during reboot if the laptop is configured in Hybrid Graphics mode. The reason is unknown, but the following steps and possibly a good bit of patience will reproduce the issue: 1. Boot up the laptop normally in Hybrid Graphics mode 2. Make sure nouveau is loaded and that the GPU is awake 3. Allow the Nvidia GPU to runtime suspend itself after being idle 4. Reboot the machine, the more sudden the better (e.g. sysrq-b may help) 5. If nouveau loads up properly, reboot the machine again and go back to step 2 until you reproduce the issue This results in some very strange behavior: the GPU will be left in exactly the same state it was in when the previously booted kernel started the reboot. This has all sorts of bad side effects: for starters, this completely breaks nouveau starting with a mysterious EVO channel failure that happens well before we've actually used the EVO channel for anything: nouveau 0000:01:00.0: disp: chid 0 mthd 0000 data 00000400 00001000 00000002 This causes a timeout trying to bring up the GR ctx: nouveau 0000:01:00.0: timeout WARNING: CPU: 0 PID: 12 at drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c:1547 gf100_grctx_generate+0x7b2/0x850 [nouveau] Hardware name: LENOVO 20EQS64N0B/20EQS64N0B, BIOS N1EET82W (1.55 ) 12/18/2018 Workqueue: events_long drm_dp_mst_link_probe_work [drm_kms_helper] ... nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1) nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1) nouveau 0000:01:00.0: fifo: fault 01 [WRITE] at 0000000000008000 engine 00 [GR] client 15 [HUB/SCC_NB] reason c4 [] on channel -1 [0000000000 unknown] The GPU never manages to recover. Booting without loading nouveau causes issues as well, since the GPU starts sending spurious interrupts that cause other device's IRQs to get disabled by the kernel: irq 16: nobody cared (try booting with the "irqpoll" option) ... handlers: [<000000007faa9e99>] i801_isr [i2c_i801] Disabling IRQ #16 ... serio: RMI4 PS/2 pass-through port at rmi4-00.fn03 i801_smbus 0000:00:1f.4: Timeout waiting for interrupt! i801_smbus 0000:00:1f.4: Transaction timeout rmi4_f03 rmi4-00.fn03: rmi_f03_pt_write: Failed to write to F03 TX register (-110). i801_smbus 0000:00:1f.4: Timeout waiting for interrupt! i801_smbus 0000:00:1f.4: Transaction timeout rmi4_physical rmi4-00: rmi_driver_set_irq_bits: Failed to change enabled interrupts! This causes the touchpad and sometimes other things to get disabled. Since this happens without nouveau, we can't fix this problem from nouveau itself. Add a PCI quirk for the specific P50 variant of this GPU. Make sure the GPU is advertising NoReset- so we don't reset the GPU when the machine is in Dedicated graphics mode (where the GPU being initialized by the BIOS is normal and expected). Map the GPU MMIO space and read the magic 0x2240c register, which will have bit 1 set if the device was POSTed during a previous boot. Once we've confirmed all of this, reset the GPU and re-disable it - bringing it back to a healthy state. Link: https://bugzilla.kernel.org/show_bug.cgi?id=203003 Link: https://lore.kernel.org/lkml/20190212220230.1568-1-lyude@redhat.com Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: nouveau@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: Karol Herbst <kherbst@redhat.com> Cc: Ben Skeggs <skeggsb@gmail.com> Cc: stable@vger.kernel.org
2019-04-23PCI/ACPI: Advertise _HPX Type 3 support via _OSCAlexandru Gagniuc
_OSC now has a way to inform firmware that OS has the capability to interpret _HPX Type 3 setting records. This was added by the following PCI Firmware Specification ECN: ECN: _HPX and PCIe Completion Timeout related _OSC Enhancements Date: September 12, 2018 Affected Document: PCI Firmware Specification, Rev. 3.2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-23PCI/ACPI: Implement _HPX Type 3 Setting RecordAlexandru Gagniuc
The _HPX Type 3 Setting Record is intended to be more generic and allow configuration of settings not possible with Type 2 records. For example, firmware could ensure that the completion timeout value is set accordingly throughout the PCI tree. Implement support for _HPX Type 3 Setting Records, which were added in the ACPI 6.3 spec. Link: https://lore.kernel.org/lkml/20190208162414.3996-4-mr.nuke.me@gmail.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-23PCI/ACPI: Remove the need for 'struct hotplug_params'Alexandru Gagniuc
We used to first parse all the _HPP and _HPX tables before using the information to program registers of PCIe devices. Up through HPX Type 2, there was only one structure of each type, so we could cheat and store it on the stack. With HPX Type 3 we get an arbitrary number of entries, so the above model doesn't scale that well. Instead of parsing all tables at once, parse and program each entry separately. For _HPP and _HPX Types 0 through 2, this is functionally equivalent. The change enables the upcoming _HPX Type 3 to integrate more easily. Link: https://lore.kernel.org/lkml/20190208162414.3996-3-mr.nuke.me@gmail.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [bhelgaas: fix build errors] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-23PCI/ACPI: Do not export pci_get_hp_params()Alexandru Gagniuc
pci_get_hp_params() is only used within drivers/pci, and there is no reason to make it available outside of the PCI core, so stop exporting it. Link: https://lore.kernel.org/lkml/20190208162414.3996-2-mr.nuke.me@gmail.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-22PCI: Mark Atheros AR9462 to avoid bus resetJames Prestwood
When using PCI passthrough with this device, the host machine locks up completely when starting the VM, requiring a hard reboot. Add a quirk to avoid bus resets on this device. Fixes: c3e59ee4e766 ("PCI: Mark Atheros AR93xx to avoid bus reset") Link: https://lore.kernel.org/linux-pci/20190107213248.3034-1-james.prestwood@linux.intel.com Signed-off-by: James Prestwood <james.prestwood@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.14+
2019-04-18PCI/LINK: Disable bandwidth notification interrupt during suspendMika Westerberg
If the bandwidth notification interrupt is left unmasked when entering suspend to idle, it triggers immediately bringing the system back to working state. To keep that from happening, disable the interrupt when entering system sleep and enable it again during resume. Reported-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-18switchtec: Fix unintended mask of MRPC eventWesley Sheng
When running application tool switchtec-user's `firmware update` and `event wait` commands concurrently, sometimes the firmware update speed reduced significantly. It is because when the MRPC event happened after MRPC event occurrence check but before the event mask loop reaches its header register in event ISR, the MRPC event would be masked unintentionally. Since there's no chance to enable it again except for a module reload, all the following MRPC execution completion checks time out. Fix this bug by skipping the mask operation for MRPC event in event ISR, same as what we already do for LINK event. Fixes: 52eabba5bcdb ("switchtec: Add IOCTLs to the Switchtec driver") Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2019-04-17switchtec: Increase PFF limit from 48 to 255Wesley Sheng
The Switchtec devices supports two PCIe Function Frameworks (PFFs) per upstream port (one for the port itself and one for the management endoint), and each PFF may have up to 255 ports. Previously the driver only supported 48 of those ports, and the SWITCHTEC_IOCTL_EVENT_SUMMARY ioctl only returned information about those 48. Increase SWITCHTEC_MAX_PFF_CSR from 48 to 255 so the driver supports all 255 possible ports. Rename SWITCHTEC_IOCTL_EVENT_SUMMARY and associated struct switchtec_ioctl_event_summary to SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY and switchtec_ioctl_event_summary_legacy with so existing applications work unchanged, supporting up to 48 ports. Add replacement SWITCHTEC_IOCTL_EVENT_SUMMARY and struct switchtec_ioctl_event_summary that new and recompiled applications support up to 255 ports. Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
2019-04-17x86/PCI: Fix PCI IRQ routing table memory leakWenwen Wang
In pcibios_irq_init(), the PCI IRQ routing table 'pirq_table' is first found through pirq_find_routing_table(). If the table is not found and CONFIG_PCI_BIOS is defined, the table is then allocated in pcibios_get_irq_routing_table() using kmalloc(). Later, if the I/O APIC is used, this table is actually not used. In that case, the allocated table is not freed, which is a memory leak. Free the allocated table if it is not used. Signed-off-by: Wenwen Wang <wang6495@umn.edu> [bhelgaas: added Ingo's reviewed-by, since the only change since v1 was to use the irq_routing_table local variable name he suggested] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ingo Molnar <mingo@kernel.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2019-04-17PCI: Remove unused pci_request_region_exclusive()Johannes Thumshirn
pci_request_region_exclusive() was introduced with commit e8de1481fd71 ("resource: allow MMIO exclusivity for device drivers") in 2.6.29 which was released 2008. It never had an in tree user since then, so after 11 years later let's remove it. Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-17PCI: Assign bus numbers present in EA capability for bridgesSubbaraya Sundeep
The "Enhanced Allocation (EA) for Memory and I/O Resources" ECN, approved 23 October 2014, sec 6.9.1.2, specifies a second DW in the capability for type 1 (bridge) functions to describe fixed secondary and subordinate bus numbers. This ECN was included in the PCIe r4.0 spec, but sec 6.9.1.2 was omitted, presumably by mistake. Read fixed bus numbers from the EA capability for bridges. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> [bhelgaas: add pci_ea_fixed_busnrs() return value] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-12PCI/AER: Change pci_aer_init() stub to return voidJisheng Zhang
Commit 60ed982a4e78 ("PCI/AER: Move internal declarations to drivers/pci/pci.h") changed pci_aer_init() to return "void", but didn't change the stub for when CONFIG_PCIEAER isn't enabled. Change the stub to match. Fixes: 60ed982a4e78 ("PCI/AER: Move internal declarations to drivers/pci/pci.h") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.19+
2019-04-11PCI: OF: Support "external-facing" propertyJean-Philippe Brucker
Set the "untrusted" attribute to any PCIe port that has an "external-facing" device tree property. Any device downstream of this port will inherit the attribute and have only the strictest IOMMU protection. Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-11dt-bindings: Add "external-facing" PCIe port propertyJean-Philippe Brucker
Provide a way for the firmware to tell the OS which devices are external to the machine and therefore untrusted. The property can describe for example Thunderbolt and other user-accessible ports, which should always have the strongest IOMMU protection. Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Grant Likely <grant.likely@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
2019-04-11PCI: Mark AMD Stoney Radeon R7 GPU ATS as brokenNikolai Kostrigin
ATS is broken on the Radeon R7 GPU (at least for Stoney Ridge based laptop) and causes IOMMU stalls and system failure. Disable ATS on these devices to make them usable again with IOMMU enabled. Thanks to Joerg Roedel <jroedel@suse.de> for help. [bhelgaas: In the email thread mentioned below, Alex suspects the real problem is in sbios or iommu, so it may affect only certain systems, and it may affect other devices in those systems as well. However, per Joerg we lack the ability to debug further, so this quirk is the best we can do for now.] Link: https://bugzilla.kernel.org/show_bug.cgi?id=194521 Link: https://lore.kernel.org/lkml/20190408103725.30426-1-nickel@altlinux.org Fixes: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") Signed-off-by: Nikolai Kostrigin <nickel@altlinux.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joerg Roedel <jroedel@suse.de> CC: stable@vger.kernel.org
2019-04-10PCI: rpaphp: Get/put device node reference during slot alloc/deallocTyrel Datwyler
When allocating the slot structure we store a pointer to the associated device_node. We really should be incrementing the reference count, so add an of_node_get() during slot alloc and an of_node_put() during slot dealloc. Signed-off-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-10PCI: rpadlpar: Fix leaked device_node references in add/remove pathsTyrel Datwyler
The find_dlpar_node() helper returns a device node with its reference incremented. Both the add and remove paths use this helper for find the appropriate node, but fail to release the reference when done. Annotate the find_dlpar_node() helper with a comment about the incremented reference count and call of_node_put() on the obtained device_node in the add and remove paths. Also, fixup a reference leak in the find_vio_slot() helper where we fail to call of_node_put() on the vdevice node after we iterate over its children. Signed-off-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-04-06PCI: Rework pcie_retrain_link() wait loopStefan Mätje
Transform wait code to a "do {} while (time_before())" loop as recommended by reviewer. No functional change intended. Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-04-06PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratumStefan Mätje
Due to an erratum in some Pericom PCIe-to-PCI bridges in reverse mode (conventional PCI on primary side, PCIe on downstream side), the Retrain Link bit needs to be cleared manually to allow the link training to complete successfully. If it is not cleared manually, the link training is continuously restarted and no devices below the PCI-to-PCIe bridge can be accessed. That means drivers for devices below the bridge will be loaded but won't work and may even crash because the driver is only reading 0xffff. See the Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf for details. Devices known as affected so far are: PI7C9X110, PI7C9X111SL, PI7C9X130. Add a new flag, clear_retrain_link, in struct pci_dev. Quirks for affected devices set this bit. Note that pcie_retrain_link() lives in aspm.c because that's currently the only place we use it, but this erratum is not specific to ASPM, and we may retrain links for other reasons in the future. Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu> [bhelgaas: apply regardless of CONFIG_PCIEASPM] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> CC: stable@vger.kernel.org
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