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2025-03-05drm/msm/dpu: move resource allocation to CRTCDmitry Baryshkov
All resource allocation is centered around the LMs. Then other blocks (except DSCs) are allocated basing on the LMs that was selected, and LM powers up the CRTC rather than the encoder. Moreover if at some point the driver supports encoder cloning, allocating resources from the encoder will be incorrect, as all clones will have different encoder IDs, while LMs are to be shared by these encoders. In addition, move mode_changed() to dpu_crtc as encoder no longer has access to topology information Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [quic_abhinavk@quicinc.com: Refactored resource allocation for CDM] Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> [quic_jesszhan@quicinc.com: Changed to grabbing exising global state] Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> [DB: rebased on top of msm-next] [DB: fixed resource allcoation to ignore the active_changed flag] Patchwork: https://patchwork.freedesktop.org/patch/637487/ Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-2-a44c293cf422@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-05drm/msm/dpu: fill CRTC resources in dpu_crtc.cDmitry Baryshkov
Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources from dpu_crtc_assign_resources(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [quic_abhinavk@quicinc.com: cleaned up formatting] Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/637485/ Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-1-a44c293cf422@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-03-05drm/msm/dpu: don't set crtc_state->mode_changed from atomic_check()Dmitry Baryshkov
The MSM driver uses drm_atomic_helper_check() which mandates that none of the atomic_check() callbacks toggles crtc_state->mode_changed. Perform corresponding check before calling the drm_atomic_helper_check() function. Fixes: 8b45a26f2ba9 ("drm/msm/dpu: reserve cdm blocks for writeback in case of YUV output") Reported-by: Simona Vetter <simona.vetter@ffwll.ch> Closes: https://lore.kernel.org/dri-devel/ZtW_S0j5AEr4g0QW@phenom.ffwll.local/ Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> [DB: dropped the WARN_ON] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/633400/ Link: https://lore.kernel.org/r/20250123-drm-dirty-modeset-v2-4-bbfd3a6cd1a4@linaro.org
2025-02-28dt-bindings: display/msm/gmu: Add Adreno 623 GMUJie Zhang
Document Adreno 623 GMU in the dt-binding specification. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/640058/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-27drm/msm/a6xx: Add support for Adreno 623Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640056/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-27drm/msm/a6xx: Fix gpucc register block for A621Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update a6xx_gpu_state code to dump the correct set of gpucc registers. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640055/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-27drm/msm/a6xx: Split out gpucc register blockJie Zhang
Some GPUs have different memory map for GPUCC block. So split out the gpucc range from a6xx_gmu_cx_registers to a separate block to accommodate those GPUs. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/640052/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-27drm/msm/gem: Fix error code msm_parse_deps()Dan Carpenter
The SUBMIT_ERROR() macro turns the error code negative. This extra '-' operation turns it back to positive EINVAL again. The error code is passed to ERR_PTR() and since positive values are not an IS_ERR() it eventually will lead to an oops. Delete the '-'. Fixes: 866e43b945bf ("drm/msm: UAPI error reporting") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637625/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-27drm/msm: Extend gpu devcore dumps with pgtbl infoRob Clark
In the case of iova fault triggered devcore dumps, include additional debug information based on what we think is the current page tables, including the TTBR0 value (which should match what we have in adreno_smmu_fault_info unless things have gone horribly wrong), and the pagetable entries traversed in the process of resolving the faulting iova. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/628117/
2025-02-27drm/msm: Expose DRIVER_SYNCOBJ_TIMELINERob Clark
Initially we didn't want to expose the cap, as it would expose a bug in the vk driver (turnip) with older mesa versions. This was fixed over a year ago (and cherry-picked to stable release branches at the time), see https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25981. So let's go ahead and expose it now. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/639610/
2025-02-27drm/msm/a6xx: Fix stale rpmh votes from GPUAkhil P Oommen
It was observed on sc7180 (A618 gpu) that GPU votes for GX rail and CNOC BCM nodes were not removed after GPU suspend. This was because we skipped sending 'prepare-slumber' request to gmu during suspend sequence in some cases. So, make sure we always call prepare-slumber hfi during suspend. Also, calling prepare-slumber without a prior oob-gpu handshake messes up gmu firmware's internal state. So, do that when required. Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support") Cc: stable@vger.kernel.org Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/639569/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-02-26drm/msm/dpu: rate limit snapshot capture for mmu faultsAbhinav Kumar
There is no recovery mechanism in place yet to recover from mmu faults for DPU. We can only prevent the faults by making sure there is no misconfiguration. Rate-limit the snapshot capture for mmu faults to once per msm_atomic_commit_tail() as that should be sufficient to capture the snapshot for debugging otherwise there will be a lot of DPU snapshots getting captured for the same fault which is redundant and also might affect capturing even one snapshot accurately. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/638362/ Link: https://lore.kernel.org/r/20250219-abhinavk-smmu-fault-handler-v3-5-aa3f0bf4434a@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm: switch msm_kms to use msm_iommu_disp_new()Abhinav Kumar
Switch msm_kms to use msm_iommu_disp_new() so that the newly registered fault handler will kick-in during any mmu faults. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/638360/ Link: https://lore.kernel.org/r/20250219-abhinavk-smmu-fault-handler-v3-4-aa3f0bf4434a@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/iommu: introduce msm_iommu_disp_new() for msm_kmsAbhinav Kumar
Introduce a new API msm_iommu_disp_new() for display use-cases. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/638363/ Link: https://lore.kernel.org/r/20250219-abhinavk-smmu-fault-handler-v3-3-aa3f0bf4434a@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/iommu: rename msm_fault_handler to msm_gpu_fault_handlerAbhinav Kumar
In preparation of registering a separate fault handler for display, lets rename the existing msm_fault_handler to msm_gpu_fault_handler. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/638358/ Link: https://lore.kernel.org/r/20250219-abhinavk-smmu-fault-handler-v3-2-aa3f0bf4434a@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm: register a fault handler for display mmu faultsAbhinav Kumar
In preparation to register a iommu fault handler for display related modules, register a fault handler for the backing mmu object of msm_kms. Currently, the fault handler only captures the display snapshot but we can expand this later if more information needs to be added to debug display mmu faults. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/638359/ Link: https://lore.kernel.org/r/20250219-abhinavk-smmu-fault-handler-v3-1-aa3f0bf4434a@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify savingKrzysztof Kozlowski
Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to avoid hard-coding bit masks and shifts and make the code a bit more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/638324/ Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-2-d28973fa513a@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLLKrzysztof Kozlowski
Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock Framework. pll_7nm_register() still used in one place previous readl+writel, which can be simplified with this new wrapper. This is purely for readability and simplification and should have no functional impact, because the code touched here is before clock is registered via CCF, so there is no concurrency issue. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/638323/ Link: https://lore.kernel.org/r/20250219-drm-msm-phy-pll-cfg-reg-v5-1-d28973fa513a@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Add check for devm_kstrdup()Haoxiang Li
Add check for the return value of devm_kstrdup() in dsi_host_parse_dt() to catch potential exception. Fixes: 958d8d99ccb3 ("drm/msm/dsi: parse vsync source from device tree") Cc: stable@vger.kernel.org Signed-off-by: Haoxiang Li <haoxiang_li2024@163.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/638297/ Link: https://lore.kernel.org/r/20250219040712.2598161-1-haoxiang_li2024@163.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Allow values of 10 and 12 for bits per componentEugene Lepshy
The DRM DSC helper has various bits_per_component values - not just 8. But the DSC 1.1 block supports only 8, 10, and 12. Extend the guard accordingly and add a comment noting this limitation. Signed-off-by: Eugene Lepshy <fekz115@gmail.com> Co-developed-by: Danila Tikhonov <danila@jiaxyga.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637831/ Link: https://lore.kernel.org/r/20250217222431.82522-4-danila@jiaxyga.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topologyMarijn Suijten
When DSC is enabled the number of interfaces is forced to be 1, and documented that it is a "power-optimal" layout to use two DSC encoders together with two Layer Mixers. However, the same layout (two DSC hard-slice encoders with two LMs) is also used when the display is fed with data over two instead of one interface (common on 4k@120Hz smartphone panels with Dual-DSI). Solve this by simply removing the num_intf = 1 assignment as the count is already calculated by computing the number of physical encoders within the virtual encoder. Fixes: 7e9cc175b159 ("drm/msm/disp/dpu1: Add support for DSC in topology") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/637649/ Link: https://lore.kernel.org/r/20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-3-913100d6103f@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Set PHY usescase (and mode) before registering DSI hostMarijn Suijten
Ordering issues here cause an uninitialized (default STANDALONE) usecase to be programmed (which appears to be a MUX) in some cases when msm_dsi_host_register() is called, leading to the slave PLL in bonded-DSI mode to source from a clock parent (dsi1vco) that is off. This should seemingly not be a problem as the actual dispcc clocks from DSI1 that are muxed in the clock tree of DSI0 are way further down, this bit still seems to have an effect on them somehow and causes the right side of the panel controlled by DSI1 to not function. In an ideal world this code is refactored to no longer have such error-prone calls "across subsystems", and instead model the "PLL src" register field as a regular mux so that changing the clock parents programmatically or in DTS via `assigned-clock-parents` has the desired effect. But for the avid reader, the clocks that we *are* muxing into DSI0's tree are way further down, so if this bit turns out to be a simple mux between dsiXvco and out_div, that shouldn't have any effect as this whole tree is off anyway. Fixes: 57bf43389337 ("drm/msm/dsi: Pass down use case to PHY") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/637650/ Link: https://lore.kernel.org/r/20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-2-913100d6103f@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Use existing per-interface slice count in DSC timingMarijn Suijten
When configuring the timing of DSI hosts (interfaces) in dsi_timing_setup() all values written to registers are taking bonded-mode into account by dividing the original mode width by 2 (half the data is sent over each of the two DSI hosts), but the full width instead of the interface width is passed as hdisplay parameter to dsi_update_dsc_timing(). Currently only msm_dsc_get_slices_per_intf() is called within dsi_update_dsc_timing() with the `hdisplay` argument which clearly documents that it wants the width of a single interface (which, again, in bonded DSI mode is half the total width of the mode) resulting in all subsequent values to be completely off. However, as soon as we start to pass the halved hdisplay into dsi_update_dsc_timing() we might as well discard msm_dsc_get_slices_per_intf() since the value it calculates is already available in dsc->slice_count which is per-interface by the current design of MSM DPU/DSI implementations and their use of the DRM DSC helpers. Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/637648/ Link: https://lore.kernel.org/r/20250217-drm-msm-initial-dualpipe-dsc-fixes-v3-1-913100d6103f@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Drop unnecessary -ENOMEM messageKrzysztof Kozlowski
Kernel core already prints detailed report about memory allocation failures, so drivers should not have their own error messages. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637308/ Link: https://lore.kernel.org/r/20250214-drm-msm-cleanups-v2-4-1bec50f37dc1@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Minor whitespace and style cleanupKrzysztof Kozlowski
Cleanup few obvious kernel coding style violations: missing or unnecessary braces in 'if-else', unnecessary break lines, incorrect breaking of long function declarations, unnecessary 'else' after a 'return'. No functional impact expected. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637305/ Link: https://lore.kernel.org/r/20250214-drm-msm-cleanups-v2-3-1bec50f37dc1@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Simplify with dev_err_probe()Krzysztof Kozlowski
dsi_get_config(), dsi_clk_init() and msm_dsi_host_init() are called only from platform driver probe function, so using dev_err_probe() is both appropriate and beneficial: - Properly marks device deferred probe status, - Avoids dmesg flood on probe deferrals, - Already incorporates printing ERR value, - Shows device name (in contrast to pr_err()), - Makes code smaller and simpler. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637306/ Link: https://lore.kernel.org/r/20250214-drm-msm-cleanups-v2-2-1bec50f37dc1@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi: Drop redundant NULL-ifying of clocks on error pathsKrzysztof Kozlowski
dsi_clk_init(), which gets the clocks, is called only through platform driver probe and its failure is a failure of the probe. Therefore NULL-ifying specific clocks is pointless and redundant - the PTR_ERR value stored there won't be used/dereferenced afterwards. What's more, variant-specific clock init calls like dsi_clk_init_6g_v2() are not doing this cleanup. Dropping redundant code allows later to make this a bit simpler. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637303/ Link: https://lore.kernel.org/r/20250214-drm-msm-cleanups-v2-1-1bec50f37dc1@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26dt-bindings: display: qcom,sm8650-mdss: explicitly document mdp0-mem and ↵Neil Armstrong
cpu-cfg interconnect paths The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2 makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg is required, so explicitly document the mdp0-mem/cpu-cfg interconnect paths and complete the example with the missing interconnect paths. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637051/ Link: https://lore.kernel.org/r/20250213-topic-sm8x50-mdss-interconnect-bindings-fix-v4-2-3fa0bc42dd38@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26dt-bindings: display: qcom,sm8550-mdss: explicitly document mdp0-mem and ↵Neil Armstrong
cpu-cfg interconnect paths The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2 makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg is required, so explicitly document the mdp0-mem/cpu-cfg interconnect and add the cpu-cfg path in the example. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/637050/ Link: https://lore.kernel.org/r/20250213-topic-sm8x50-mdss-interconnect-bindings-fix-v4-1-3fa0bc42dd38@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi/phy: Program clock inverters in correct registerKrzysztof Kozlowski
Since SM8250 all downstream sources program clock inverters in PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as reset value (0x0). The most recent Hardware Programming Guide for 3 nm, 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/634489/ Link: https://lore.kernel.org/r/20250129115504.40080-1-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26drm/msm/dsi/phy: Use the header with clock IDsKrzysztof Kozlowski
Use the header with clock IDs to bind the interface between driver and DTS. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/634149/ Link: https://lore.kernel.org/r/20250127132105.107138-2-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-26dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDsKrzysztof Kozlowski
DSI phys, from earliest (28 nm) up to newest (3 nm) generation, provide two clocks. The respective clock ID is used by drivers and DTS, so it should be documented as explicit ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/634146/ Link: https://lore.kernel.org/r/20250127132105.107138-1-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/msm/dpu: simplify dpu_encoder_get_topology() interfaceDmitry Baryshkov
As a preparation for calling dpu_encoder_get_topology() from different code paths, simplify its calling interface, obtaining some data pointers internally instead passing them via arguments. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/633396/ Link: https://lore.kernel.org/r/20250123-drm-dirty-modeset-v2-3-bbfd3a6cd1a4@linaro.org
2025-02-25drm/msm/dpu: move needs_cdm setting to dpu_encoder_get_topology()Dmitry Baryshkov
As a preparation for calling dpu_encoder_get_topology() from different places, move the code setting topology->needs_cdm to that function (instead of patching topology separately). Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/633395/ Link: https://lore.kernel.org/r/20250123-drm-dirty-modeset-v2-2-bbfd3a6cd1a4@linaro.org
2025-02-25drm/msm/dpu: don't use active in atomic_check()Dmitry Baryshkov
The driver isn't supposed to consult crtc_state->active/active_check for resource allocation. Instead all resources should be allocated if crtc_state->enabled is set. Stop consulting active / active_changed in order to determine whether the hardware resources should be (re)allocated. Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset") Reported-by: Simona Vetter <simona.vetter@ffwll.ch> Closes: https://lore.kernel.org/dri-devel/ZtW_S0j5AEr4g0QW@phenom.ffwll.local/ Reviewed-by: Simona Vetter <simona.vetter@ffwll.ch> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/633393/ Link: https://lore.kernel.org/r/20250123-drm-dirty-modeset-v2-1-bbfd3a6cd1a4@linaro.org
2025-02-25drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCsMarijn Suijten
Some SoCs such as SC7280 (used in the Fairphone 5) have only a single DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology (2 LM and 2 DSC for a single interface) make it impossible to use Display Stream Compression panels with mainline, which is exactly what's installed on the Fairphone 5. By loosening the hardcoded `num_dsc = 2` to fall back to `num_dsc = 1` when the catalog only contains one entry, we can trivially support this phone and unblock further panel enablement on mainline. A few more supporting changes in this patch ensure hardcoded constants of 2 DSC encoders are replaced to count or read back the actual number of DSC hardware blocks that are enabled for the given virtual encoder. Likewise DSC_MODE_SPLIT_PANEL can no longer be unconditionally enabled. Cc: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Danila Tikhonov <danila@jiaxyga.com> Patchwork: https://patchwork.freedesktop.org/patch/633318/ Link: https://lore.kernel.org/r/20250122-dpu-111-topology-v2-1-505e95964af9@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/msm: Use str_enable_disable-like helpersKrzysztof Kozlowski
Replace ternary (condition ? "enable" : "disable") syntax with helpers from string_choices.h because: 1. Simple function call with one argument is easier to read. Ternary operator has three arguments and with wrapping might lead to quite long code. 2. Is slightly shorter thus also easier to read. 3. It brings uniformity in the text - same string. 4. Allows deduping by the linker, which results in a smaller binary file. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/632406/ Link: https://lore.kernel.org/r/20250114191724.861601-1-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/msm/dpu: Simplify using local 'ctl' variableKrzysztof Kozlowski
In few places we store 'phys_enc->hw_ctl' to local 'ctl' variable so use it everywhere. No functional change. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/632389/ Link: https://lore.kernel.org/r/20250114155959.583889-1-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/msm/dpu: Add writeback support for SM6150Fange Zhang
On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/632337/ Link: https://lore.kernel.org/r/20250114-add-writeback-support-for-sm6150-v2-1-d707b31aad5c@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/msm/dp: Add support for LTTPR handlingAbel Vesa
Link Training Tunable PHY Repeaters (LTTPRs) are defined in DisplayPort 1.4a specification. As the name suggests, these PHY repeaters are capable of adjusting their output for link training purposes. According to the DisplayPort standard, LTTPRs have two operating modes: - non-transparent - it replies to DPCD LTTPR field specific AUX requests, while passes through all other AUX requests - transparent - it passes through all AUX requests. Switching between these two modes is done by the DPTX by issuing an AUX write to the DPCD PHY_REPEATER_MODE register. The msm DP driver is currently lacking any handling of LTTPRs. This means that if at least one LTTPR is found between DPTX and DPRX, the link training would fail if that LTTPR was not already configured in transparent mode. The section 3.6.6.1 from the DisplayPort v2.0 specification mandates that before link training with the LTTPR is started, the DPTX may place the LTTPR in non-transparent mode by first switching to transparent mode and then to non-transparent mode. This operation seems to be needed only on first link training and doesn't need to be done again until device is unplugged. It has been observed on a few X Elite-based platforms which have such LTTPRs in their board design that the DPTX needs to follow the procedure described above in order for the link training to be successful. So add support for reading the LTTPR DPCD caps to figure out the number of such LTTPRs first. Then, for platforms (or Type-C dongles) that have at least one such an LTTPR, set its operation mode to transparent mode first and then to non-transparent, just like the mentioned section of the specification mandates. Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250203-drm-dp-msm-add-lttpr-transparent-mode-set-v5-4-c865d0e56d6e@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/i915/dp: Use the generic helper to control LTTPR transparent modeAbel Vesa
LTTPRs operating modes are defined by the DisplayPort standard and the generic framework now provides a helper to switch between them, which is handling the explicit disabling of non-transparent mode and its disable->enable sequence mentioned in the DP Standard v2.0 section 3.6.6.1. So use the new drm generic helper instead as it makes the code a bit cleaner. Since the driver specific implementation holds the lttrp_common_caps, if the call to the drm generic helper fails, the lttrp_common_caps need to be updated as the helper has already rolled back to transparent mode. Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250203-drm-dp-msm-add-lttpr-transparent-mode-set-v5-3-c865d0e56d6e@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/nouveau/dp: Use the generic helper to control LTTPR transparent modeAbel Vesa
LTTPRs operating modes are defined by the DisplayPort standard and the generic framework now provides a helper to switch between them, which is handling the explicit disabling of non-transparent mode and its disable->enable sequence mentioned in the DP Standard v2.0 section 3.6.6.1. So use the new drm generic helper instead as it makes the code a bit cleaner. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Danilo Krummrich <dakr@kernel.org> # via IRC Link: https://patchwork.freedesktop.org/patch/msgid/20250203-drm-dp-msm-add-lttpr-transparent-mode-set-v5-2-c865d0e56d6e@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25drm/dp: Add helper to set LTTPRs in transparent modeAbel Vesa
According to the DisplayPort standard, LTTPRs have two operating modes: - non-transparent - it replies to DPCD LTTPR field specific AUX requests, while passes through all other AUX requests - transparent - it passes through all AUX requests. Switching between this two modes is done by the DPTX by issuing an AUX write to the DPCD PHY_REPEATER_MODE register. Add a generic helper that allows switching between these modes. Also add a generic wrapper for the helper that handles the explicit disabling of non-transparent mode and its disable->enable sequence mentioned in the DP Standard v2.0 section 3.6.6.1. Do this in order to move this handling out of the vendor specific driver implementation into the generic framework. Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250203-drm-dp-msm-add-lttpr-transparent-mode-set-v5-1-c865d0e56d6e@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2025-02-25Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get fixes from v6.14-rc4. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-02-25drm: panel: Add a panel driver for the Summit displaySasha Finkelstein
This is the display panel used for the touchbar on laptops that have it. Co-developed-by: Nick Chan <towinchenmi@gmail.com> Signed-off-by: Nick Chan <towinchenmi@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Link: https://lore.kernel.org/r/20250217-adpdrm-v7-3-ca2e44b3c7d8@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250217-adpdrm-v7-3-ca2e44b3c7d8@gmail.com
2025-02-25drm/panel: simple: Add BOE AV123Z7M-N17 panelMaud Spierings
Add support for the BOE AV123Z7M-N17 12.3" LVDS panel. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250224-initial_display-v1-8-5ccbbf613543@gocontroll.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250224-initial_display-v1-8-5ccbbf613543@gocontroll.com
2025-02-25drm/panel: simple: add BOE AV101HDT-A10 panelMaud Spierings
add support for the BOE AV101HDT-A10 10.1" LVDS panel Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250224-initial_display-v1-7-5ccbbf613543@gocontroll.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250224-initial_display-v1-7-5ccbbf613543@gocontroll.com
2025-02-25dt-bindings: display: simple: Add BOE AV123Z7M-N17 panelMaud Spierings
Add support for the BOE AV123Z7M-N17 12.3" LVDS panel. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250224-initial_display-v1-2-5ccbbf613543@gocontroll.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250224-initial_display-v1-2-5ccbbf613543@gocontroll.com
2025-02-25dt-bindings: display: simple: add BOE AV101HDT-A10 panelMaud Spierings
add a compatible string for the BOE AV101HDT-A10 10.1" LVDS panel Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250224-initial_display-v1-1-5ccbbf613543@gocontroll.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250224-initial_display-v1-1-5ccbbf613543@gocontroll.com
2025-02-25drm/mipi-dsi: extend "multi" functions and use them in sony-td4353-jdiTejas Vipin
Removes mipi_dsi_dcs_set_tear_off and replaces it with a multi version as after replacing it in sony-td4353-jdi, it doesn't appear anywhere else. sony-td4353-jdi is converted to use multi style functions, including mipi_dsi_dcs_set_tear_off_multi. Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250220045721.145905-1-tejasvipin76@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250220045721.145905-1-tejasvipin76@gmail.com
generated by cgit (git 2.34.1) at 2025-09-09 15:59:52 +0000