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2022-07-11Merge tag 'ti-k3-dt-for-v5.20' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v5.20 * AM62: fixups, sa2ul enabled, ramoops for sk * others: whitespace and gpio-key cleanup. * tag 'ti-k3-dt-for-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: dts: ti: k3-am62-main: Enable crypto accelerator arm64: dts: ti: k3-am625-sk: Enable ramoops arm64: dts: ti: k3-am642-sk: Add pinmux corresponding to main_uart0 arm64: dts: ti: Align gpio-key node names with dtschema arm64: dts: ti: Adjust whitespace around '=' Link: https://lore.kernel.org/r/20220708232701.vpk45lwogpasaaay@enchilada Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'tegra-for-5.20-arm64-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.20-rc1 This adds and enables various hardware on Tegra234 (host1x, VIC, GPCDMA) as well as the Control BackBone related device tree nodes on Tegra194 and Tegra234. Native timers are enabled on Tegra186, Tegra194 and Tegra234, which allow keeping track of SoC-wide timestamps as well as hardware watchdog functionality. The audio subsystem is enhanced with the Output Processing Engine (OPE) on Tegra210 and later. Finally there are a handful of minor cleanups and fixes. * tag 'tegra-for-5.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Fix SDMMC1 CD on P2888 arm64: tegra: Update compatible for Tegra234 GPCDMA arm64: tegra: Add Host1x and VIC on Tegra234 arm64: tegra: Add Host1x context stream IDs on Tegra186+ arm64: tegra: Enable native timers on Tegra234 arm64: tegra: Enable native timers on Tegra194 arm64: tegra: Enable native timers on Tegra186 arm64: tegra: Add node for CBB 2.0 on Tegra234 arm64: tegra: Add node for CBB 1.0 on Tegra194 arm64: tegra: Align gpio-keys node names with dtschema arm64: tegra: Mark BPMP channels as no-memory-wc arm64: tegra: Add Tegra234 GPCDMA device tree node arm64: tegra: Adjust whitespace around '=' arm64: tegra: Enable OPE on various platforms arm64: tegra: Add OPE device on Tegra210 and later Link: https://lore.kernel.org/r/20220708185608.676474-7-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'tegra-for-5.20-arm-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.20-rc1 Two minor fixes to help reduce the noise from the DT validation tooling. * tag 'tegra-for-5.20-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Align gpio-keys node names with dtschema ARM: tegra: Adjust whitespace around '=' Link: https://lore.kernel.org/r/20220708185608.676474-6-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'tegra-for-5.20-dt-bindings' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.20-rc1 These changes add clock, reset, memory client and power domain definitions for various devices found on Tegra234 along with a few device tree bindings for new hardware. * tag 'tegra-for-5.20-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: tegra-ccplex-cluster: Remove status from required properties dt-bindings: Add headers for Host1x and VIC on Tegra234 dt-bindings: timer: Add Tegra186 & Tegra234 Timer dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB 2.0 binding dt-bindings: arm: tegra: Add NVIDIA Tegra194 AXI2APB binding dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB 1.0 binding dt-bindings: memory: Add Tegra234 MGBE memory clients dt-bindings: Add Tegra234 MGBE clocks and resets dt-bindings: power: Add Tegra234 MGBE power domains dt-bindings: Add headers for Tegra234 GPCDMA Link: https://lore.kernel.org/r/20220708185608.676474-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'sunxi-dt-for-5.20-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt - whitespace fixes - replaced RTC indexes with constants - gpio-key nodes aligned with dtschema - fixed LED node for Orange Pi Win - added OPP table for R40 CPU and thermal points - updated I2C controller compatibles - added compatibles for MBUS, D1 DE2 clocks, D1 USB - enable internal HMIC bias on Pinephone * tag 'sunxi-dt-for-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: pinephone: Enable internal HMIC bias dt-bindings: arm: sunxi: Add several MBUS compatibles dt-bindings: arm: sunxi: Default to the full MBUS binding dt-bindings: usb: generic-ohci: Add Allwinner D1 compatible dt-bindings: usb: generic-ehci: Add Allwinner D1 compatible dt-bindings: usb: sunxi-musb: Add Allwinner D1 compatible arm64: dts: allwinner: a100: Update I2C controller fallback dt-bindings: i2c: mv64xxx: Add variants with offload support ARM: dts: sun8i-r40: Add thermal trip points/cooling maps ARM: dts: sun8i-r40: add opp table for cpu ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based board arm64: dts: allwinner: a64: orangepi-win: Fix LED node name dt-bindings: clock: Add compatible for D1 DE2 clocks ARM: dts: allwinner: align gpio-key node names with dtschema arm64: dts: allwinner: align gpio-key node names with dtschema arm64: dts: allwinner: Use constants for RTC clock indexes ARM: dts: sunxi: Use constants for RTC clock indexes ARM: dts: sun5i: adjust whitespace around '=' Link: https://lore.kernel.org/r/Ysh8qRH0Q5Xv9Qhf@kista.localdomain Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'v5.19-next-dts64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt Some fixes to follow DT spec. MT6795: - Big update of supported devices: cpu-map, L2 cache, PMU, watchdog, MediaTek timer, Arm CCI, pincontroller MT7622: - Change WPS button to active low MT8173: - Add infracfg property to the IOMMU node (also for mt2712e) - Add optional AXI clock to NOR Flash node MT8183: - add Medaitek CCI support - add support for Smart Voltag Scaling (SVS) - add GCE support to mutex - Add panel default rotation to some chromebooks - Add power supply to power domain so that SRAM for the GPU has power MT8186: - compatible added, DTS not yet ready. MT8192: - Add support for Acer Chromebook 514 MT8195: - Add efuse node - Enable USB wakeup support - Add support for Acer Chromebook Spin 513 * tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (66 commits) arm64: dts: mt8183: Add panel rotation arm64: dts: mt7622: fix BPI-R64 WPS button arm64: dts: mt8173: Fix nor_flash node arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4 arm64: dts: mediatek: cherry: Enable support for the SPI NOR flash arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7 arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllers arm64: dts: mediatek: cherry: Enable I2C and SPI controllers arm64: dts: mediatek: cherry: Document gpios and add default pin config arm64: dts: mediatek: cherry: Add support for internal eMMC storage arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMIC arm64: dts: mediatek: cherry: Add platform regulators layout and config arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato dt-bindings: arm: mediatek: Add MT8195 Cherry Tomato Chromebooks arm64: dts: mediatek: asurada: Add SPI NOR flash memory arm64: dts: mediatek: asurada: Enable SCP arm64: dts: mediatek: asurada: Enable MMC arm64: dts: mediatek: asurada: Add SPMI regulators arm64: dts: mediatek: asurada: Add MT6359 PMIC arm64: dts: mediatek: asurada: Enable PCIe and add WiFi ... Link: https://lore.kernel.org/r/b0d5b584-2693-73b3-79f6-3e2292f006ea@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-11Merge tag 'v5.19-next-dts32' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt Airoha EN7523: - Add clock and PCIe support Several style fixes to comply with DT spec. * tag 'v5.19-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: ARM: dts: mediatek: align gpio-key node names with dtschema ARM: dts: mediatek: adjust whitespace around '=' ARM: dts: Add PCIe support for Airoha EN7523 ARM: dts: add clock support for Airoha EN7523 Link: https://lore.kernel.org/r/63536da6-fbe4-2d96-ab91-ae756cd580c4@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-09arm64: dts: allwinner: h616: Add X96 Mate TV box supportAndre Przywara
The X96 Mate is an Allwinner H616 based TV box, featuring: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 2GiB/4GiB RAM (fully usable!) - 16/32/64GiB eMMC - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported) - Unsupported Allwinner WiFi chip - 2 x USB 2.0 host ports - HDMI port - IR receiver - 5V/2A DC power supply via barrel plug Add a basic devicetree for it, with SD card and eMMC working, as well as serial and the essential peripherals, like the AXP PMIC. This DT is somewhat minimal, and should work on many other similar TV boxes with the Allwinner H616 chip. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-8-andre.przywara@arm.com
2022-07-09arm64: dts: allwinner: h616: Add OrangePi Zero 2 board supportAndre Przywara
The OrangePi Zero 2 is a development board with the new H616 SoC. It comes with the following features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 512MiB/1GiB DDR3 DRAM - AXP305 PMIC - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 2MiB bootable SPI NOR flash - 1Gbps Ethernet port (via RTL8211F PHY) - micro-HDMI port - (yet) unsupported Allwinner WiFi/BT chip Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-7-andre.przywara@arm.com
2022-07-09dt-bindings: arm: sunxi: Add two H616 board compatible stringsAndre Przywara
This adds the two board compatible strings of two boards with the Allwinner H616 SoC. One is a development board from OrangePi, the other some TV box from some formerly unused vendor. Add that vendor to the vendor list on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-6-andre.przywara@arm.com
2022-07-09dt-bindings: pinctrl: sunxi: allow vcc-pi-supplyAndre Przywara
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage for GPIO port I. Extend the range of supply port names to include vcc-pi-supply to cover that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-5-andre.przywara@arm.com
2022-07-09arm64: dts: allwinner: Add Allwinner H616 .dtsi fileAndre Przywara
This (relatively) new SoC is similar to the H6, but drops the (broken) PCIe support and the USB 3.0 controller. It also gets the management controller removed, which in turn removes *some*, but not all of the devices formerly dedicated to the ARISC (CPUS). And while there is still the extra sunxi interrupt controller, the package lacks the corresponding NMI pin, so no interrupts for the PMIC. The reserved memory node is actually handled by Trusted Firmware now, but U-Boot fails to propagate this to a separately loaded DTB, so we keep it in here for now, until U-Boot learns to do this properly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-4-andre.przywara@arm.com
2022-07-09dt-bindings: pinctrl: sunxi: Make interrupts optionalAndre Przywara
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an interrupt (it features only two pins). However the binding requires at least naming one upstream interrupt, plus the #interrupt-cells and interrupt-controller properties. Drop the unconditional requirement for the interrupt properties, and make them dependent on being not this particular pinctrl device. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-3-andre.przywara@arm.com
2022-07-09dt-bindings: arm: sunxi: Add H616 EMAC0 compatibleAndre Przywara
The Allwinner H616 contains an "EMAC0" Ethernet MAC compatible to the A64 version. Add it to the list of compatible strings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220708105235.3983266-2-andre.przywara@arm.com
2022-07-09arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MPAlexander Stein
This adds support for TQMa8MPQL module on MBa8MPxL board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-09dt-bindings: arm: add TQMa8MPxL boardMarkus Niebel
TQMa8MPxL is a SOM family using NXP i.MX8MP CPU family MBa8MPxL is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mp-<SOM>" for the module and "tq,imx8mp-<SOM>-<SBC>" Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08arm64: dts: qcom: sc8280xp: fix DP PHY node unit addressesJohan Hovold
Fix up the DP PHY node which had the wrong unit address. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708072556.4687-1-johan+linaro@kernel.org
2022-07-08arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clockJohan Hovold
Fix the usb_0 HS PHY reference clock which was mistakingly replaced with the first usb_2 PHY clock. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220708072358.4583-1-johan+linaro@kernel.org
2022-07-08arm64: dts: qcom: sc7280: fix PCIe clock referenceJohan Hovold
The recent commit that dropped the PCIe PHY clock index failed to update the PCIe node reference. Fixes: 531c738fb360 ("arm64: dts: qcom: sc7280: drop PCIe PHY clock index") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220707064222.15717-1-johan+linaro@kernel.org
2022-07-08docs: arm: index.rst: add google/chromebook-boot-flowMauro Carvalho Chehab
This document was added without placing it at arm book. Fixes: 59228d3b9060 ("dt-bindings: Document how Chromebooks with depthcharge boot") Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/0ae8251f97c642cfd618f2e32eb1e66339e5dfde.1656759989.git.mchehab@kernel.org
2022-07-08ARM: dts: Add BCM63138 generic board dtsWilliam Zhang
Add generic bcm963138.dts file. Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-07-08ARM: dts: update dts files for bcmbca SoC BCM63138William Zhang
Update BCM63138 board compatible string based on binding document. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-07-08ARM: dts: Move BCM963138DVT board dts to ARCH_BCMBCAWilliam Zhang
Use CONFIG_ARCH_BCMBCA to build all the BCMBCA SoC dts and remove CONFIG_ARCH_BCM_63XX from the makefile Signed-off-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-07-08dt-bindings: arm: add BCM63138 SoCWilliam Zhang
Add BCM63138 SoC device tree description to bcmbca binding document. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-07-08arm64: dts: allwinner: pinephone: Enable internal HMIC biasSamuel Holland
Revisions 1.0 and 1.1 of the PinePhone mainboard do not have an external resistor connecting HBIAS to MIC2P. Enable the internal resistor to provide the necessary headeset microphone bias. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220621035452.60272-4-samuel@sholland.org
2022-07-08dt-bindings: arm: sunxi: Add several MBUS compatiblesSamuel Holland
All of the sunxi SoCs since at least the A33 have a similar structure for the MBUS and DRAM controller, but they all have minor differences in MBUS port assignments and DRAM controller behavior. Give each SoC its own compatible. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220702042447.26734-2-samuel@sholland.org
2022-07-08dt-bindings: arm: sunxi: Default to the full MBUS bindingSamuel Holland
Some older SoCs use a deprecated MBUS binding with some clocks missing. Currently, new SoCs must opt in to the complete binding. This should be the default, so new SoCs do not accidentally use the deprecated version. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220702042447.26734-1-samuel@sholland.org
2022-07-08arm64: tegra: Fix SDMMC1 CD on P2888Tamás Szűcs
Hook SDMMC1 CD up with CVM GPIO02 (SOC_GPIO11) used for card detection on J4 (uSD socket) on the carrier. Fixes: ef633bfc21e9 ("arm64: tegra: Enable card detect for SD card on P2888") Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Update compatible for Tegra234 GPCDMAAkhil R
Use the compatible specific to Tegra234 for GPCDMA to support additional features. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Host1x and VIC on Tegra234Mikko Perttunen
Add device tree nodes for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Host1x context stream IDs on Tegra186+Mikko Perttunen
Add Host1x context stream IDs on systems that support Host1x context isolation. Host1x and attached engines can use these stream IDs to allow isolation between memory used by different processes. The specified stream IDs must match those configured by the hypervisor, if one is present. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra234Kartik
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra234. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra194Thierry Reding
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra194. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra186Kartik
Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add node for CBB 2.0 on Tegra234Sumit Gupta
Tegra234 uses the Control Backbone (CBB) version 2.0. Add the nodes that enable error handling from the various CBB 2.0 fabrics found on Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add node for CBB 1.0 on Tegra194Sumit Gupta
Add device tree nodes to enable error handling on the Control Backbone (CBB). Tegra194 uses CBB version 1.0. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Align gpio-keys node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Mark BPMP channels as no-memory-wcMikko Perttunen
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues. Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map. Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed. As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory. Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Tegra234 GPCDMA device tree nodeAkhil R
Add device tree nodes for Tegra234 GPCDMA Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Adjust whitespace around '='Krzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable OPE on various platformsSameer Pujar
Enable OPE module usage on various Jetson platforms. This can be plugged into an audio path using ALSA mixer controls. Add audio-graph-port binding to use OPE device with generic audio-graph based sound card. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add OPE device on Tegra210 and laterSameer Pujar
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08Merge branch 'for-5.20/dt-bindings' into for-5.20/arm64/dtThierry Reding
2022-07-08dt-bindings: tegra-ccplex-cluster: Remove status from required propertiesThierry Reding
The "status" property is implied to be "okay" if it isn't present, so do not mark it as required. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: Add headers for Host1x and VIC on Tegra234Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08dt-bindings: timer: Add Tegra186 & Tegra234 TimerKartik
The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08Merge tag 'renesas-dt-bindings-for-v5.20-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.20 (take two) - Miscellaneous fixes and improvements. * tag 'renesas-dt-bindings-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: hwinfo: renesas,prr: move from soc directory MAINTAINERS: Add Renesas SoC DT bindings to Renesas Architecture sections Link: https://lore.kernel.org/r/cover.1657278851.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08Merge tag 'renesas-arm-dt-for-v5.20-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.20 (take two) - Ethernet MAC and switch support for the RZ/N1 SoC on the RZN1D-DB development board, - AA1024XD12 panel overlay support for the Draak, Ebisu, and Salvator-X(S) development boards, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Add panel overlay for Draak and Ebisu boards arm64: dts: renesas: Add panel overlay for Salvator-X(S) boards arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay support arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order ARM: dts: r9a06g032-rzn1d400-db: Add switch description dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter ARM: dts: r9a06g032: Describe switch ARM: dts: r9a06g032: Describe GMAC2 ARM: dts: r9a06g032: Describe MII converter arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in comment ARM: dts: renesas: Fix DA9063 watchdog subnode names arm64: dts: renesas: r8a779m8: Drop operating points above 1.5 GHz Link: https://lore.kernel.org/r/cover.1657278845.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-08arm64: dts: freescale: imx8qxp: Fix the keys node nameAbel Vesa
The proper name is 'keys', not 'scu-keys'. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-07-08arm64: dts: freescale: imx8: Fix the system-controller node nameViorel Suman
The proper name is 'system-controller', not 'scu'. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-27 23:52:02 +0000